Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1510103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239546

1

T1

2125

T2

77

T3

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	594820	1			T1	5230		T2	380		T3	506
values[0x0]	561289	1			T1	5052		T2	62		T3	76
values[0x1]	593540	1			T1	5264		T2	386		T3	501

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

581783

1

T1

5163

T2

300

T3

385

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27571	1			T1	237		T2	17		T3	13
valid_sources[0x01]	27037	1			T1	225		T2	12		T3	19
valid_sources[0x02]	28196	1			T1	212		T2	9		T3	14
valid_sources[0x03]	26705	1			T1	193		T2	20		T3	22
valid_sources[0x04]	26587	1			T1	281		T2	21		T3	17
valid_sources[0x05]	28667	1			T1	249		T2	14		T3	16
valid_sources[0x06]	27926	1			T1	238		T2	3		T3	21
valid_sources[0x07]	27457	1			T1	193		T2	13		T3	15
valid_sources[0x08]	29118	1			T1	226		T2	11		T3	17
valid_sources[0x09]	25882	1			T1	175		T2	15		T3	19
valid_sources[0x0a]	27398	1			T1	217		T2	9		T3	15
valid_sources[0x0b]	27927	1			T1	256		T2	20		T3	20
valid_sources[0x0c]	27082	1			T1	251		T2	14		T3	18
valid_sources[0x0d]	27307	1			T1	166		T2	10		T3	19
valid_sources[0x0e]	27217	1			T1	295		T2	18		T3	15
valid_sources[0x0f]	27097	1			T1	254		T2	14		T3	22
valid_sources[0x10]	27176	1			T1	233		T2	18		T3	17
valid_sources[0x11]	27940	1			T1	279		T2	7		T3	14
valid_sources[0x12]	28014	1			T1	302		T2	13		T3	17
valid_sources[0x13]	27397	1			T1	226		T2	19		T3	14
valid_sources[0x14]	25979	1			T1	200		T2	13		T3	14
valid_sources[0x15]	27375	1			T1	340		T2	14		T3	18
valid_sources[0x16]	27335	1			T1	206		T2	9		T3	22
valid_sources[0x17]	28645	1			T1	230		T2	11		T3	13
valid_sources[0x18]	26715	1			T1	232		T2	15		T3	17
valid_sources[0x19]	26818	1			T1	268		T2	6		T3	16
valid_sources[0x1a]	26533	1			T1	303		T2	8		T3	12
valid_sources[0x1b]	28385	1			T1	280		T2	15		T3	14
valid_sources[0x1c]	26962	1			T1	199		T2	9		T3	20
valid_sources[0x1d]	28144	1			T1	219		T2	14		T3	9
valid_sources[0x1e]	26893	1			T1	196		T2	10		T3	18
valid_sources[0x1f]	28368	1			T1	194		T2	13		T3	15
valid_sources[0x20]	26630	1			T1	277		T2	9		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25249

1

T1

215

T2

28

T3

42

values[0x0]

all_enables

biggest_size

188895

1

T1

1696

T2

21

T3

28

values[0x1]

all_enables

biggest_size

25402

1

T1

214

T2

28

T3

34

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1522654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248241

1

T1

2317

T2

96

T3

105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	605055	1			T1	5393		T2	403		T3	545
values[0x0]	559844	1			T1	5165		T2	60		T3	79
values[0x1]	605996	1			T1	5422		T2	401		T3	511

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1168737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

602158

1

T1

5505

T2

320

T3

422

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27392	1			T1	215		T2	7		T3	20
valid_sources[0x01]	28275	1			T1	241		T2	10		T3	16
valid_sources[0x02]	27861	1			T1	213		T2	12		T3	18
valid_sources[0x03]	27458	1			T1	247		T2	11		T3	22
valid_sources[0x04]	26872	1			T1	247		T2	22		T3	21
valid_sources[0x05]	27556	1			T1	306		T2	11		T3	12
valid_sources[0x06]	27167	1			T1	235		T2	14		T3	21
valid_sources[0x07]	28304	1			T1	258		T2	14		T3	17
valid_sources[0x08]	27866	1			T1	203		T2	9		T3	12
valid_sources[0x09]	26997	1			T1	196		T2	17		T3	24
valid_sources[0x0a]	27523	1			T1	200		T2	19		T3	21
valid_sources[0x0b]	27421	1			T1	245		T2	9		T3	13
valid_sources[0x0c]	28262	1			T1	276		T2	20		T3	13
valid_sources[0x0d]	27163	1			T1	141		T2	13		T3	25
valid_sources[0x0e]	28158	1			T1	289		T2	10		T3	12
valid_sources[0x0f]	26945	1			T1	233		T2	18		T3	23
valid_sources[0x10]	27540	1			T1	256		T2	7		T3	22
valid_sources[0x11]	28383	1			T1	337		T2	20		T3	21
valid_sources[0x12]	27470	1			T1	317		T2	14		T3	17
valid_sources[0x13]	27214	1			T1	217		T2	15		T3	15
valid_sources[0x14]	27681	1			T1	254		T2	12		T3	25
valid_sources[0x15]	27838	1			T1	238		T2	12		T3	18
valid_sources[0x16]	27208	1			T1	187		T2	16		T3	16
valid_sources[0x17]	28015	1			T1	276		T2	12		T3	18
valid_sources[0x18]	27496	1			T1	233		T2	5		T3	21
valid_sources[0x19]	27907	1			T1	226		T2	13		T3	14
valid_sources[0x1a]	27975	1			T1	341		T2	15		T3	23
valid_sources[0x1b]	28006	1			T1	261		T2	11		T3	21
valid_sources[0x1c]	27310	1			T1	221		T2	15		T3	10
valid_sources[0x1d]	27946	1			T1	175		T2	17		T3	22
valid_sources[0x1e]	28385	1			T1	197		T2	17		T3	17
valid_sources[0x1f]	26934	1			T1	238		T2	12		T3	15
valid_sources[0x20]	28025	1			T1	293		T2	21		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25911

1

T1

228

T2

36

T3

43

values[0x0]

all_enables

biggest_size

196355

1

T1

1876

T2

29

T3

30

values[0x1]

all_enables

biggest_size

25975

1

T1

213

T2

31

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1516119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240574

1

T1

2127

T2

74

T3

110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	595958	1			T1	5363		T2	379		T3	517
values[0x0]	565027	1			T1	5275		T2	57		T3	95
values[0x1]	595708	1			T1	5143		T2	365		T3	532

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1172508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

584185

1

T1

5132

T2

311

T3

432

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26926	1			T1	212		T2	9		T3	15
valid_sources[0x01]	28293	1			T1	195		T2	11		T3	23
valid_sources[0x02]	27708	1			T1	226		T2	13		T3	17
valid_sources[0x03]	26913	1			T1	175		T2	11		T3	15
valid_sources[0x04]	27105	1			T1	279		T2	9		T3	12
valid_sources[0x05]	26658	1			T1	220		T2	18		T3	23
valid_sources[0x06]	27632	1			T1	316		T2	7		T3	19
valid_sources[0x07]	27204	1			T1	240		T2	9		T3	20
valid_sources[0x08]	28119	1			T1	244		T2	19		T3	20
valid_sources[0x09]	26708	1			T1	166		T2	23		T3	18
valid_sources[0x0a]	27987	1			T1	272		T2	13		T3	11
valid_sources[0x0b]	28256	1			T1	281		T2	13		T3	11
valid_sources[0x0c]	27573	1			T1	232		T2	15		T3	21
valid_sources[0x0d]	26890	1			T1	178		T2	3		T3	17
valid_sources[0x0e]	27588	1			T1	232		T2	23		T3	14
valid_sources[0x0f]	26515	1			T1	245		T2	25		T3	16
valid_sources[0x10]	27233	1			T1	225		T2	10		T3	18
valid_sources[0x11]	28488	1			T1	278		T2	12		T3	21
valid_sources[0x12]	27887	1			T1	305		T2	24		T3	21
valid_sources[0x13]	27900	1			T1	209		T2	26		T3	10
valid_sources[0x14]	27195	1			T1	233		T2	9		T3	13
valid_sources[0x15]	27321	1			T1	233		T2	17		T3	13
valid_sources[0x16]	26842	1			T1	169		T2	8		T3	17
valid_sources[0x17]	26803	1			T1	265		T2	10		T3	24
valid_sources[0x18]	27408	1			T1	242		T2	14		T3	14
valid_sources[0x19]	27244	1			T1	246		T2	7		T3	13
valid_sources[0x1a]	27726	1			T1	277		T2	7		T3	15
valid_sources[0x1b]	27848	1			T1	331		T2	8		T3	14
valid_sources[0x1c]	27172	1			T1	180		T2	13		T3	26
valid_sources[0x1d]	27161	1			T1	237		T2	10		T3	23
valid_sources[0x1e]	27536	1			T1	214		T2	8		T3	19
valid_sources[0x1f]	27014	1			T1	235		T2	8		T3	20
valid_sources[0x20]	27010	1			T1	255		T2	7		T3	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25336

1

T1

219

T2

31

T3

35

values[0x0]

all_enables

biggest_size

189880

1

T1

1715

T2

20

T3

44

values[0x1]

all_enables

biggest_size

25358

1

T1

193

T2

23

T3

31