Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7599795	0	0
GntImpliesValid_A	2147483647	7599795	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7599795	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	444116536	0	0
ReadyAndValidImplyGrant_A	2147483647	7599795	0	0
ReqAndReadyImplyGrant_A	2147483647	7599795	0	0
ReqImpliesValid_A	2147483647	34814044	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	37458	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7599795	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11773008	11769504	0	0
T2	2478120	2443128	0	0
T3	16410216	16407288	0	0
T7	4734048	4730304	0	0
T8	1430136	1429344	0	0
T9	214728	213936	0	0
T10	2187360	2183664	0	0
T11	7326264	7326216	0	0
T12	5017248	5016168	0	0
T13	5470440	5470176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11773008	11769504	0	0
T2	2478120	2443128	0	0
T3	16410216	16407288	0	0
T7	4734048	4730304	0	0
T8	1430136	1429344	0	0
T9	214728	213936	0	0
T10	2187360	2183664	0	0
T11	7326264	7326216	0	0
T12	5017248	5016168	0	0
T13	5470440	5470176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11773008	11769504	0	0
T2	2478120	2443128	0	0
T3	16410216	16407288	0	0
T7	4734048	4730304	0	0
T8	1430136	1429344	0	0
T9	214728	213936	0	0
T10	2187360	2183664	0	0
T11	7326264	7326216	0	0
T12	5017248	5016168	0	0
T13	5470440	5470176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	444116536	0	0
T1	11773008	662037	0	0
T2	2478120	57978	0	0
T3	16410216	989007	0	0
T7	4734048	231352	0	0
T8	1430136	92669	0	0
T9	214728	10288	0	0
T10	2187360	128766	0	0
T11	7326264	2302414	0	0
T12	5017248	294069	0	0
T13	5470440	192818	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34814044	0	0
T1	11773008	128977	0	0
T2	2478120	68268	0	0
T3	16410216	289006	0	0
T7	4734048	99684	0	0
T8	1430136	15182	0	0
T9	214728	691	0	0
T10	2187360	12359	0	0
T11	7326264	460505	0	0
T12	5017248	64754	0	0
T13	5470440	1347	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37458	0	21600
T1	981084	28	0	2
T2	206510	501	0	2
T3	1367518	50	0	2
T7	394504	23	0	2
T8	119178	5	0	2
T9	17894	0	0	2
T10	182280	0	0	2
T11	610522	0	0	2
T12	418104	5	0	2
T13	455870	0	0	2
T14	0	1	0	0
T15	0	3	0	0
T16	0	28	0	0
T17	0	18	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	56	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11773008	11769504	0	0
T2	2478120	2443128	0	0
T3	16410216	16407288	0	0
T7	4734048	4730304	0	0
T8	1430136	1429344	0	0
T9	214728	213936	0	0
T10	2187360	2183664	0	0
T11	7326264	7326216	0	0
T12	5017248	5016168	0	0
T13	5470440	5470176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599795	0	0
T1	11773008	42525	0	0
T2	2478120	46211	0	0
T3	16410216	67729	0	0
T7	4734048	15879	0	0
T8	1430136	6853	0	0
T9	214728	359	0	0
T10	2187360	5741	0	0
T11	7326264	7514	0	0
T12	5017248	19564	0	0
T13	5470440	835	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	846194	0	0
GntImpliesValid_A	402144945	846194	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	846194	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	12374026	0	0
ReadyAndValidImplyGrant_A	402144945	846194	0	0
ReqAndReadyImplyGrant_A	402144945	846194	0	0
ReqImpliesValid_A	402144945	2520461	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	846194	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	12374026	0	0
T1	490542	30113	0	0
T2	103255	3679	0	0
T3	683759	48712	0	0
T7	197252	10168	0	0
T8	59589	5075	0	0
T9	8947	315	0	0
T10	91140	4723	0	0
T11	305261	280365	0	0
T12	209052	16351	0	0
T13	227935	347	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2520461	0	0
T1	490542	6265	0	0
T2	103255	5187	0	0
T3	683759	14790	0	0
T7	197252	8358	0	0
T8	59589	1287	0	0
T9	8947	58	0	0
T10	91140	846	0	0
T11	305261	35836	0	0
T12	209052	6225	0	0
T13	227935	124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846194	0	0
T1	490542	4216	0	0
T2	103255	4425	0	0
T3	683759	7736	0	0
T7	197252	1879	0	0
T8	59589	748	0	0
T9	8947	45	0	0
T10	91140	601	0	0
T11	305261	855	0	0
T12	209052	2426	0	0
T13	227935	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	846808	0	0
GntImpliesValid_A	402144945	846808	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	846808	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	12242491	0	0
ReadyAndValidImplyGrant_A	402144945	846808	0	0
ReqAndReadyImplyGrant_A	402144945	846808	0	0
ReqImpliesValid_A	402144945	2481915	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	846808	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	12242491	0	0
T1	490542	33281	0	0
T2	103255	4309	0	0
T3	683759	42226	0	0
T7	197252	9915	0	0
T8	59589	4661	0	0
T9	8947	331	0	0
T10	91140	4678	0	0
T11	305261	243728	0	0
T12	209052	12918	0	0
T13	227935	472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2481915	0	0
T1	490542	20498	0	0
T2	103255	7551	0	0
T3	683759	9270	0	0
T7	197252	11075	0	0
T8	59589	1107	0	0
T9	8947	63	0	0
T10	91140	958	0	0
T11	305261	34549	0	0
T12	209052	2441	0	0
T13	227935	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	846808	0	0
T1	490542	5649	0	0
T2	103255	5921	0	0
T3	683759	6064	0	0
T7	197252	2118	0	0
T8	59589	701	0	0
T9	8947	42	0	0
T10	91140	666	0	0
T11	305261	844	0	0
T12	209052	1736	0	0
T13	227935	107	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	205045	0	0
GntImpliesValid_A	402144945	205045	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	205045	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	2983312	0	0
ReadyAndValidImplyGrant_A	402144945	205045	0	0
ReqAndReadyImplyGrant_A	402144945	205045	0	0
ReqImpliesValid_A	402144945	588397	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	205045	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2983312	0	0
T1	490542	7835	0	0
T2	103255	1027	0	0
T3	683759	7161	0	0
T7	197252	2314	0	0
T8	59589	1428	0	0
T9	8947	93	0	0
T10	91140	1230	0	0
T11	305261	68249	0	0
T12	209052	2113	0	0
T13	227935	113	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	588397	0	0
T1	490542	5970	0	0
T2	103255	1193	0	0
T3	683759	10520	0	0
T7	197252	2059	0	0
T8	59589	238	0	0
T9	8947	9	0	0
T10	91140	192	0	0
T11	305261	4425	0	0
T12	209052	293	0	0
T13	227935	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205045	0	0
T1	490542	1418	0	0
T2	103255	1101	0	0
T3	683759	1748	0	0
T7	197252	645	0	0
T8	59589	174	0	0
T9	8947	9	0	0
T10	91140	163	0	0
T11	305261	199	0	0
T12	209052	278	0	0
T13	227935	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	201065	0	0
GntImpliesValid_A	402144945	201065	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	201065	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3019105	0	0
ReadyAndValidImplyGrant_A	402144945	201065	0	0
ReqAndReadyImplyGrant_A	402144945	201065	0	0
ReqImpliesValid_A	402144945	556047	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	201065	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3019105	0	0
T1	490542	7206	0	0
T2	103255	1561	0	0
T3	683759	9900	0	0
T7	197252	2213	0	0
T8	59589	1625	0	0
T9	8947	78	0	0
T10	91140	1334	0	0
T11	305261	71814	0	0
T12	209052	1961	0	0
T13	227935	134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	556047	0	0
T1	490542	2889	0	0
T2	103255	3915	0	0
T3	683759	7630	0	0
T7	197252	11250	0	0
T8	59589	313	0	0
T9	8947	9	0	0
T10	91140	243	0	0
T11	305261	8116	0	0
T12	209052	314	0	0
T13	227935	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	201065	0	0
T1	490542	1240	0	0
T2	103255	2729	0	0
T3	683759	1801	0	0
T7	197252	1219	0	0
T8	59589	211	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	223	0	0
T12	209052	267	0	0
T13	227935	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	199046	0	0
GntImpliesValid_A	402144945	199046	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	199046	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	5651090	0	0
ReadyAndValidImplyGrant_A	402144945	199046	0	0
ReqAndReadyImplyGrant_A	402144945	199046	0	0
ReqImpliesValid_A	402144945	1173956	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	199046	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	5651090	0	0
T1	490542	16574	0	0
T2	103255	9537	0	0
T3	683759	67734	0	0
T7	197252	5139	0	0
T8	59589	1933	0	0
T9	8947	108	0	0
T10	91140	2828	0	0
T11	305261	45961	0	0
T12	209052	4841	0	0
T13	227935	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	1173956	0	0
T1	490542	1314	0	0
T2	103255	6756	0	0
T3	683759	44715	0	0
T7	197252	10141	0	0
T8	59589	315	0	0
T9	8947	30	0	0
T10	91140	274	0	0
T11	305261	4648	0	0
T12	209052	424	0	0
T13	227935	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199046	0	0
T1	490542	860	0	0
T2	103255	993	0	0
T3	683759	1926	0	0
T7	197252	511	0	0
T8	59589	202	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	211	0	0
T12	209052	279	0	0
T13	227935	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	214061	0	0
GntImpliesValid_A	402144945	214061	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	214061	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	5394157	0	0
ReadyAndValidImplyGrant_A	402144945	214061	0	0
ReqAndReadyImplyGrant_A	402144945	214061	0	0
ReqImpliesValid_A	402144945	1256703	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	214061	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	5394157	0	0
T1	490542	9994	0	0
T2	103255	14411	0	0
T3	683759	7776	0	0
T7	197252	3289	0	0
T8	59589	2775	0	0
T9	8947	149	0	0
T10	91140	8490	0	0
T11	305261	29246	0	0
T12	209052	4273	0	0
T13	227935	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	1256703	0	0
T1	490542	1095	0	0
T2	103255	7121	0	0
T3	683759	5308	0	0
T7	197252	210	0	0
T8	59589	369	0	0
T9	8947	10	0	0
T10	91140	633	0	0
T11	305261	1391	0	0
T12	209052	5556	0	0
T13	227935	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	214061	0	0
T1	490542	898	0	0
T2	103255	1371	0	0
T3	683759	1223	0	0
T7	197252	175	0	0
T8	59589	205	0	0
T9	8947	10	0	0
T10	91140	147	0	0
T11	305261	207	0	0
T12	209052	811	0	0
T13	227935	27	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	222906	0	0
GntImpliesValid_A	402144945	222906	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	222906	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	4483553	0	0
ReadyAndValidImplyGrant_A	402144945	222906	0	0
ReqAndReadyImplyGrant_A	402144945	222906	0	0
ReqImpliesValid_A	402144945	1169965	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	222906	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	4483553	0	0
T1	490542	9399	0	0
T2	103255	5050	0	0
T3	683759	10278	0	0
T7	197252	2382	0	0
T8	59589	2178	0	0
T9	8947	59	0	0
T10	91140	2345	0	0
T11	305261	33450	0	0
T12	209052	3786	0	0
T13	227935	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	1169965	0	0
T1	490542	6113	0	0
T2	103255	5451	0	0
T3	683759	8782	0	0
T7	197252	231	0	0
T8	59589	360	0	0
T9	8947	10	0	0
T10	91140	349	0	0
T11	305261	1854	0	0
T12	209052	363	0	0
T13	227935	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	222906	0	0
T1	490542	1432	0	0
T2	103255	1803	0	0
T3	683759	1340	0	0
T7	197252	181	0	0
T8	59589	177	0	0
T9	8947	10	0	0
T10	91140	152	0	0
T11	305261	205	0	0
T12	209052	276	0	0
T13	227935	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	205290	0	0
GntImpliesValid_A	402144945	205290	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	205290	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	5183819	0	0
ReadyAndValidImplyGrant_A	402144945	205290	0	0
ReqAndReadyImplyGrant_A	402144945	205290	0	0
ReqImpliesValid_A	402144945	1235676	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	205290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	5183819	0	0
T1	490542	7619	0	0
T2	103255	4306	0	0
T3	683759	21530	0	0
T7	197252	1843	0	0
T8	59589	2085	0	0
T9	8947	47	0	0
T10	91140	3330	0	0
T11	305261	27934	0	0
T12	209052	3480	0	0
T13	227935	167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	1235676	0	0
T1	490542	1040	0	0
T2	103255	860	0	0
T3	683759	10227	0	0
T7	197252	219	0	0
T8	59589	348	0	0
T9	8947	6	0	0
T10	91140	251	0	0
T11	305261	1833	0	0
T12	209052	360	0	0
T13	227935	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	205290	0	0
T1	490542	869	0	0
T2	103255	663	0	0
T3	683759	2119	0	0
T7	197252	144	0	0
T8	59589	217	0	0
T9	8947	6	0	0
T10	91140	172	0	0
T11	305261	223	0	0
T12	209052	242	0	0
T13	227935	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	212324	0	0
GntImpliesValid_A	402144945	212324	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	212324	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3028315	0	0
ReadyAndValidImplyGrant_A	402144945	212324	0	0
ReqAndReadyImplyGrant_A	402144945	212324	0	0
ReqImpliesValid_A	402144945	585977	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	212324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3028315	0	0
T1	490542	9864	0	0
T2	103255	1045	0	0
T3	683759	9688	0	0
T7	197252	2011	0	0
T8	59589	1464	0	0
T9	8947	44	0	0
T10	91140	1326	0	0
T11	305261	62522	0	0
T12	209052	9498	0	0
T13	227935	141	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	585977	0	0
T1	490542	1942	0	0
T2	103255	1303	0	0
T3	683759	14344	0	0
T7	197252	4742	0	0
T8	59589	288	0	0
T9	8947	19	0	0
T10	91140	210	0	0
T11	305261	3867	0	0
T12	209052	8389	0	0
T13	227935	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212324	0	0
T1	490542	1378	0	0
T2	103255	1165	0	0
T3	683759	2347	0	0
T7	197252	666	0	0
T8	59589	190	0	0
T9	8947	7	0	0
T10	91140	151	0	0
T11	305261	194	0	0
T12	209052	1750	0	0
T13	227935	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	206871	0	0
GntImpliesValid_A	402144945	206871	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	206871	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3029177	0	0
ReadyAndValidImplyGrant_A	402144945	206871	0	0
ReqAndReadyImplyGrant_A	402144945	206871	0	0
ReqImpliesValid_A	402144945	592369	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	206871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3029177	0	0
T1	490542	6833	0	0
T2	103255	709	0	0
T3	683759	17419	0	0
T7	197252	1085	0	0
T8	59589	1249	0	0
T9	8947	31	0	0
T10	91140	1176	0	0
T11	305261	80444	0	0
T12	209052	3202	0	0
T13	227935	83	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	592369	0	0
T1	490542	1033	0	0
T2	103255	719	0	0
T3	683759	20486	0	0
T7	197252	164	0	0
T8	59589	215	0	0
T9	8947	5	0	0
T10	91140	173	0	0
T11	305261	4257	0	0
T12	209052	2216	0	0
T13	227935	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	206871	0	0
T1	490542	879	0	0
T2	103255	705	0	0
T3	683759	3704	0	0
T7	197252	163	0	0
T8	59589	174	0	0
T9	8947	5	0	0
T10	91140	153	0	0
T11	305261	231	0	0
T12	209052	750	0	0
T13	227935	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	208182	0	0
GntImpliesValid_A	402144945	208182	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	208182	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	2981818	0	0
ReadyAndValidImplyGrant_A	402144945	208182	0	0
ReqAndReadyImplyGrant_A	402144945	208182	0	0
ReqImpliesValid_A	402144945	557833	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	208182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2981818	0	0
T1	490542	8166	0	0
T2	103255	668	0	0
T3	683759	16093	0	0
T7	197252	1058	0	0
T8	59589	1457	0	0
T9	8947	106	0	0
T10	91140	1155	0	0
T11	305261	61537	0	0
T12	209052	5036	0	0
T13	227935	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	557833	0	0
T1	490542	3371	0	0
T2	103255	664	0	0
T3	683759	5777	0	0
T7	197252	176	0	0
T8	59589	288	0	0
T9	8947	25	0	0
T10	91140	177	0	0
T11	305261	2810	0	0
T12	209052	1269	0	0
T13	227935	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208182	0	0
T1	490542	1429	0	0
T2	103255	657	0	0
T3	683759	2806	0	0
T7	197252	153	0	0
T8	59589	191	0	0
T9	8947	14	0	0
T10	91140	153	0	0
T11	305261	181	0	0
T12	209052	789	0	0
T13	227935	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	221262	0	0
GntImpliesValid_A	402144945	221262	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	221262	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3028024	0	0
ReadyAndValidImplyGrant_A	402144945	221262	0	0
ReqAndReadyImplyGrant_A	402144945	221262	0	0
ReqImpliesValid_A	402144945	626635	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	221262	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3028024	0	0
T1	490542	8134	0	0
T2	103255	1360	0	0
T3	683759	16782	0	0
T7	197252	1585	0	0
T8	59589	1351	0	0
T9	8947	77	0	0
T10	91140	1125	0	0
T11	305261	69829	0	0
T12	209052	3149	0	0
T13	227935	82	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	626635	0	0
T1	490542	6076	0	0
T2	103255	2874	0	0
T3	683759	8040	0	0
T7	197252	5203	0	0
T8	59589	369	0	0
T9	8947	12	0	0
T10	91140	175	0	0
T11	305261	6139	0	0
T12	209052	2187	0	0
T13	227935	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221262	0	0
T1	490542	1471	0	0
T2	103255	2108	0	0
T3	683759	3245	0	0
T7	197252	624	0	0
T8	59589	208	0	0
T9	8947	11	0	0
T10	91140	149	0	0
T11	305261	210	0	0
T12	209052	753	0	0
T13	227935	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	199623	0	0
GntImpliesValid_A	402144945	199623	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	199623	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	2937805	0	0
ReadyAndValidImplyGrant_A	402144945	199623	0	0
ReqAndReadyImplyGrant_A	402144945	199623	0	0
ReqImpliesValid_A	402144945	525779	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	199623	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2937805	0	0
T1	490542	6226	0	0
T2	103255	686	0	0
T3	683759	19007	0	0
T7	197252	1339	0	0
T8	59589	1524	0	0
T9	8947	107	0	0
T10	91140	1112	0	0
T11	305261	70333	0	0
T12	209052	2276	0	0
T13	227935	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	525779	0	0
T1	490542	937	0	0
T2	103255	692	0	0
T3	683759	8123	0	0
T7	197252	214	0	0
T8	59589	261	0	0
T9	8947	12	0	0
T10	91140	148	0	0
T11	305261	1743	0	0
T12	209052	302	0	0
T13	227935	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	199623	0	0
T1	490542	802	0	0
T2	103255	680	0	0
T3	683759	2816	0	0
T7	197252	178	0	0
T8	59589	192	0	0
T9	8947	12	0	0
T10	91140	138	0	0
T11	305261	208	0	0
T12	209052	267	0	0
T13	227935	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	208020	0	0
GntImpliesValid_A	402144945	208020	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	208020	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3061536	0	0
ReadyAndValidImplyGrant_A	402144945	208020	0	0
ReqAndReadyImplyGrant_A	402144945	208020	0	0
ReqImpliesValid_A	402144945	547926	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	208020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3061536	0	0
T1	490542	9845	0	0
T2	103255	1230	0	0
T3	683759	6461	0	0
T7	197252	1301	0	0
T8	59589	1442	0	0
T9	8947	77	0	0
T10	91140	1218	0	0
T11	305261	74888	0	0
T12	209052	2048	0	0
T13	227935	98	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	547926	0	0
T1	490542	2179	0	0
T2	103255	2466	0	0
T3	683759	932	0	0
T7	197252	190	0	0
T8	59589	232	0	0
T9	8947	9	0	0
T10	91140	179	0	0
T11	305261	4233	0	0
T12	209052	334	0	0
T13	227935	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	208020	0	0
T1	490542	1355	0	0
T2	103255	1839	0	0
T3	683759	847	0	0
T7	197252	160	0	0
T8	59589	195	0	0
T9	8947	9	0	0
T10	91140	151	0	0
T11	305261	220	0	0
T12	209052	265	0	0
T13	227935	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	210967	0	0
GntImpliesValid_A	402144945	210967	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	210967	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3015609	0	0
ReadyAndValidImplyGrant_A	402144945	210967	0	0
ReqAndReadyImplyGrant_A	402144945	210967	0	0
ReqImpliesValid_A	402144945	576308	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	210967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3015609	0	0
T1	490542	8745	0	0
T2	103255	712	0	0
T3	683759	12928	0	0
T7	197252	1754	0	0
T8	59589	1303	0	0
T9	8947	69	0	0
T10	91140	1081	0	0
T11	305261	58593	0	0
T12	209052	5175	0	0
T13	227935	107	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	576308	0	0
T1	490542	1882	0	0
T2	103255	723	0	0
T3	683759	9223	0	0
T7	197252	5218	0	0
T8	59589	259	0	0
T9	8947	14	0	0
T10	91140	195	0	0
T11	305261	4898	0	0
T12	209052	2132	0	0
T13	227935	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	210967	0	0
T1	490542	1297	0	0
T2	103255	709	0	0
T3	683759	2315	0	0
T7	197252	625	0	0
T8	59589	179	0	0
T9	8947	12	0	0
T10	91140	159	0	0
T11	305261	198	0	0
T12	209052	760	0	0
T13	227935	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	203558	0	0
GntImpliesValid_A	402144945	203558	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	203558	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3036143	0	0
ReadyAndValidImplyGrant_A	402144945	203558	0	0
ReqAndReadyImplyGrant_A	402144945	203558	0	0
ReqImpliesValid_A	402144945	571086	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	203558	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3036143	0	0
T1	490542	7180	0	0
T2	103255	977	0	0
T3	683759	10396	0	0
T7	197252	2247	0	0
T8	59589	1534	0	0
T9	8947	76	0	0
T10	91140	1181	0	0
T11	305261	65074	0	0
T12	209052	4832	0	0
T13	227935	109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	571086	0	0
T1	490542	1102	0	0
T2	103255	1277	0	0
T3	683759	4157	0	0
T7	197252	4914	0	0
T8	59589	354	0	0
T9	8947	11	0	0
T10	91140	191	0	0
T11	305261	4504	0	0
T12	209052	2698	0	0
T13	227935	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	203558	0	0
T1	490542	921	0	0
T2	103255	1118	0	0
T3	683759	1819	0	0
T7	197252	651	0	0
T8	59589	211	0	0
T9	8947	11	0	0
T10	91140	160	0	0
T11	305261	200	0	0
T12	209052	775	0	0
T13	227935	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	235307	0	0
GntImpliesValid_A	402144945	235307	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	235307	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3183877	0	0
ReadyAndValidImplyGrant_A	402144945	235307	0	0
ReqAndReadyImplyGrant_A	402144945	235307	0	0
ReqImpliesValid_A	402144945	630091	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	235307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3183877	0	0
T1	490542	8825	0	0
T2	103255	878	0	0
T3	683759	7215	0	0
T7	197252	1994	0	0
T8	59589	1470	0	0
T9	8947	126	0	0
T10	91140	1990	0	0
T11	305261	71628	0	0
T12	209052	4441	0	0
T13	227935	108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	630091	0	0
T1	490542	3213	0	0
T2	103255	898	0	0
T3	683759	5546	0	0
T7	197252	4957	0	0
T8	59589	263	0	0
T9	8947	19	0	0
T10	91140	326	0	0
T11	305261	5577	0	0
T12	209052	1775	0	0
T13	227935	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	235307	0	0
T1	490542	1576	0	0
T2	103255	879	0	0
T3	683759	1335	0	0
T7	197252	645	0	0
T8	59589	197	0	0
T9	8947	16	0	0
T10	91140	260	0	0
T11	305261	213	0	0
T12	209052	857	0	0
T13	227935	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	212966	0	0
GntImpliesValid_A	402144945	212966	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	212966	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3015459	0	0
ReadyAndValidImplyGrant_A	402144945	212966	0	0
ReqAndReadyImplyGrant_A	402144945	212966	0	0
ReqImpliesValid_A	402144945	585164	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	212966	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3015459	0	0
T1	490542	9520	0	0
T2	103255	1515	0	0
T3	683759	9651	0	0
T7	197252	1208	0	0
T8	59589	1197	0	0
T9	8947	132	0	0
T10	91140	1145	0	0
T11	305261	65666	0	0
T12	209052	2137	0	0
T13	227935	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	585164	0	0
T1	490542	2582	0	0
T2	103255	1854	0	0
T3	683759	3917	0	0
T7	197252	165	0	0
T8	59589	269	0	0
T9	8947	15	0	0
T10	91140	217	0	0
T11	305261	3861	0	0
T12	209052	303	0	0
T13	227935	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	212966	0	0
T1	490542	1349	0	0
T2	103255	1676	0	0
T3	683759	1786	0	0
T7	197252	160	0	0
T8	59589	171	0	0
T9	8947	15	0	0
T10	91140	168	0	0
T11	305261	202	0	0
T12	209052	260	0	0
T13	227935	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	207675	0	0
GntImpliesValid_A	402144945	207675	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	207675	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	2949503	0	0
ReadyAndValidImplyGrant_A	402144945	207675	0	0
ReqAndReadyImplyGrant_A	402144945	207675	0	0
ReqImpliesValid_A	402144945	545123	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	207675	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2949503	0	0
T1	490542	6705	0	0
T2	103255	982	0	0
T3	683759	6927	0	0
T7	197252	2133	0	0
T8	59589	1169	0	0
T9	8947	48	0	0
T10	91140	1346	0	0
T11	305261	75177	0	0
T12	209052	3776	0	0
T13	227935	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	545123	0	0
T1	490542	1050	0	0
T2	103255	1308	0	0
T3	683759	2671	0	0
T7	197252	4772	0	0
T8	59589	229	0	0
T9	8947	8	0	0
T10	91140	187	0	0
T11	305261	5174	0	0
T12	209052	4378	0	0
T13	227935	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	207675	0	0
T1	490542	906	0	0
T2	103255	1136	0	0
T3	683759	1281	0	0
T7	197252	652	0	0
T8	59589	155	0	0
T9	8947	8	0	0
T10	91140	167	0	0
T11	305261	223	0	0
T12	209052	820	0	0
T13	227935	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	209156	0	0
GntImpliesValid_A	402144945	209156	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	209156	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3032054	0	0
ReadyAndValidImplyGrant_A	402144945	209156	0	0
ReqAndReadyImplyGrant_A	402144945	209156	0	0
ReqImpliesValid_A	402144945	525054	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	209156	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3032054	0	0
T1	490542	6570	0	0
T2	103255	1087	0	0
T3	683759	11209	0	0
T7	197252	1236	0	0
T8	59589	1226	0	0
T9	8947	78	0	0
T10	91140	1077	0	0
T11	305261	72934	0	0
T12	209052	1856	0	0
T13	227935	109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	525054	0	0
T1	490542	968	0	0
T2	103255	1289	0	0
T3	683759	3551	0	0
T7	197252	166	0	0
T8	59589	267	0	0
T9	8947	10	0	0
T10	91140	181	0	0
T11	305261	2900	0	0
T12	209052	276	0	0
T13	227935	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	209156	0	0
T1	490542	882	0	0
T2	103255	1179	0	0
T3	683759	1629	0	0
T7	197252	159	0	0
T8	59589	170	0	0
T9	8947	10	0	0
T10	91140	155	0	0
T11	305261	221	0	0
T12	209052	260	0	0
T13	227935	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	211857	0	0
GntImpliesValid_A	402144945	211857	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	211857	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	3058208	0	0
ReadyAndValidImplyGrant_A	402144945	211857	0	0
ReqAndReadyImplyGrant_A	402144945	211857	0	0
ReqImpliesValid_A	402144945	591202	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	211857	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	3058208	0	0
T1	490542	6723	0	0
T2	103255	658	0	0
T3	683759	5795	0	0
T7	197252	1202	0	0
T8	59589	1398	0	0
T9	8947	57	0	0
T10	91140	1149	0	0
T11	305261	71252	0	0
T12	209052	2094	0	0
T13	227935	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	591202	0	0
T1	490542	1045	0	0
T2	103255	658	0	0
T3	683759	792	0	0
T7	197252	173	0	0
T8	59589	209	0	0
T9	8947	10	0	0
T10	91140	194	0	0
T11	305261	3793	0	0
T12	209052	301	0	0
T13	227935	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	211857	0	0
T1	490542	885	0	0
T2	103255	649	0	0
T3	683759	746	0	0
T7	197252	160	0	0
T8	59589	187	0	0
T9	8947	10	0	0
T10	91140	151	0	0
T11	305261	223	0	0
T12	209052	279	0	0
T13	227935	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	221259	0	0
GntImpliesValid_A	402144945	221259	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	221259	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	2990641	0	0
ReadyAndValidImplyGrant_A	402144945	221259	0	0
ReqAndReadyImplyGrant_A	402144945	221259	0	0
ReqImpliesValid_A	402144945	584558	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	0	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	221259	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2990641	0	0
T1	490542	6466	0	0
T2	103255	1572	0	0
T3	683759	11605	0	0
T7	197252	1592	0	0
T8	59589	1538	0	0
T9	8947	83	0	0
T10	91140	1142	0	0
T11	305261	62833	0	0
T12	209052	2315	0	0
T13	227935	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	584558	0	0
T1	490542	1006	0	0
T2	103255	3162	0	0
T3	683759	8811	0	0
T7	197252	5369	0	0
T8	59589	217	0	0
T9	8947	11	0	0
T10	91140	188	0	0
T11	305261	5703	0	0
T12	209052	329	0	0
T13	227935	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	221259	0	0
T1	490542	866	0	0
T2	103255	2358	0	0
T3	683759	2124	0	0
T7	197252	637	0	0
T8	59589	200	0	0
T9	8947	11	0	0
T10	91140	151	0	0
T11	305261	205	0	0
T12	209052	303	0	0
T13	227935	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	845707	0	0
GntImpliesValid_A	402144945	845707	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	845707	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	11499864	0	0
ReadyAndValidImplyGrant_A	402144945	845707	0	0
ReqAndReadyImplyGrant_A	402144945	845707	0	0
ReqImpliesValid_A	402144945	2335882	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	13409	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	845707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	11499864	0	0
T1	490542	28017	0	0
T2	103255	18	0	0
T3	683759	43640	0	0
T7	197252	9005	0	0
T8	59589	4669	0	0
T9	8947	212	0	0
T10	91140	4147	0	0
T11	305261	263042	0	0
T12	209052	15244	0	0
T13	227935	231	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	2335882	0	0
T1	490542	6127	0	0
T2	103255	4406	0	0
T3	683759	21444	0	0
T7	197252	1976	0	0
T8	59589	1275	0	0
T9	8947	74	0	0
T10	91140	1018	0	0
T11	305261	20168	0	0
T12	209052	7426	0	0
T13	227935	97	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	13409	0	900
T1	490542	2	0	1
T2	103255	42	0	1
T3	683759	29	0	1
T7	197252	0	0	1
T8	59589	0	0	1
T9	8947	0	0	1
T10	91140	0	0	1
T11	305261	0	0	1
T12	209052	4	0	1
T13	227935	0	0	1
T14	0	1	0	0
T16	0	15	0	0
T17	0	12	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	56	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	845707	0	0
T1	490542	4263	0	0
T2	103255	4406	0	0
T3	683759	7716	0	0
T7	197252	1374	0	0
T8	59589	801	0	0
T9	8947	39	0	0
T10	91140	636	0	0
T11	305261	783	0	0
T12	209052	2602	0	0
T13	227935	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402144945	402021100	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402144945	844646	0	0
GntImpliesValid_A	402144945	844646	0	0
GrantKnown_A	402144945	402021100	0	0
IdxKnown_A	402144945	402021100	0	0
IndexIsCorrect_A	402144945	844646	0	0
LockArbDecision_A	402144945	0	0	0
NoReadyValidNoGrant_A	402144945	338936950	0	0
ReadyAndValidImplyGrant_A	402144945	844646	0	0
ReqAndReadyImplyGrant_A	402144945	844646	0	0
ReqImpliesValid_A	402144945	13449937	0	0
ReqStaysHighUntilGranted0_M	402144945	0	0	0
RoundRobin_A	402144945	24049	0	900
ValidKnown_A	402144945	402021100	0	0
gen_data_port_assertion.DataFlow_A	402144945	844646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	338936950	0	0
T1	490542	402197	0	0
T2	103255	1	0	0
T3	683759	568874	0	0
T7	197252	163339	0	0
T8	59589	46918	0	0
T9	8947	7785	0	0
T10	91140	78438	0	0
T11	305261	275915	0	0
T12	209052	177267	0	0
T13	227935	189616	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	13449937	0	0
T1	490542	49280	0	0
T2	103255	5941	0	0
T3	683759	59950	0	0
T7	197252	17742	0	0
T8	59589	5850	0	0
T9	8947	242	0	0
T10	91140	4854	0	0
T11	305261	288226	0	0
T12	209052	14463	0	0
T13	227935	392	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	24049	0	900
T1	490542	26	0	1
T2	103255	459	0	1
T3	683759	21	0	1
T7	197252	23	0	1
T8	59589	5	0	1
T9	8947	0	0	1
T10	91140	0	0	1
T11	305261	0	0	1
T12	209052	1	0	1
T13	227935	0	0	1
T15	0	3	0	0
T16	0	13	0	0
T17	0	6	0	0
T18	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	402021100	0	0
T1	490542	490396	0	0
T2	103255	101797	0	0
T3	683759	683637	0	0
T7	197252	197096	0	0
T8	59589	59556	0	0
T9	8947	8914	0	0
T10	91140	90986	0	0
T11	305261	305259	0	0
T12	209052	209007	0	0
T13	227935	227924	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402144945	844646	0	0
T1	490542	5684	0	0
T2	103255	5941	0	0
T3	683759	7256	0	0
T7	197252	2000	0	0
T8	59589	797	0	0
T9	8947	26	0	0
T10	91140	584	0	0
T11	305261	835	0	0
T12	209052	1759	0	0
T13	227935	81	0	0