Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1416307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

225084

1

T1

18

T2

40

T3

1937

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	559056	1			T1	64		T2	182		T3	4902
values[0x0]	525693	1			T1	56		T2	28		T3	4746
values[0x1]	556642	1			T1	68		T2	216		T3	4814

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1094417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

546974

1

T1

66

T2

152

T3

4720

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25452	1			T1	7		T2	2		T3	268
valid_sources[0x01]	25868	1			T2	1		T3	194		T7	6
valid_sources[0x02]	25449	1			T1	16		T2	4		T3	167
valid_sources[0x03]	25858	1			T1	2		T2	20		T3	256
valid_sources[0x04]	25691	1			T2	7		T3	226		T7	2
valid_sources[0x05]	25358	1			T2	7		T3	228		T7	1
valid_sources[0x06]	25730	1			T2	5		T3	235		T7	1
valid_sources[0x07]	25743	1			T2	7		T3	284		T7	3
valid_sources[0x08]	25073	1			T2	5		T3	255		T7	8
valid_sources[0x09]	25078	1			T1	1		T2	5		T3	245
valid_sources[0x0a]	25937	1			T1	2		T2	26		T3	228
valid_sources[0x0b]	25065	1			T1	13		T2	12		T3	244
valid_sources[0x0c]	25470	1			T2	4		T3	319		T7	1
valid_sources[0x0d]	26124	1			T2	9		T3	181		T7	5
valid_sources[0x0e]	25761	1			T2	1		T3	272		T7	5
valid_sources[0x0f]	26410	1			T2	13		T3	215		T7	4
valid_sources[0x10]	25281	1			T2	7		T3	209		T7	5
valid_sources[0x11]	24990	1			T1	10		T2	11		T3	205
valid_sources[0x12]	25245	1			T2	11		T3	221		T7	4
valid_sources[0x13]	25483	1			T1	4		T2	12		T3	188
valid_sources[0x14]	25493	1			T1	2		T2	7		T3	264
valid_sources[0x15]	26257	1			T1	3		T2	15		T3	234
valid_sources[0x16]	26200	1			T1	6		T2	4		T3	239
valid_sources[0x17]	25612	1			T1	19		T2	4		T3	172
valid_sources[0x18]	26771	1			T1	7		T2	14		T3	295
valid_sources[0x19]	24218	1			T1	5		T2	1		T3	163
valid_sources[0x1a]	26338	1			T2	12		T3	229		T7	2
valid_sources[0x1b]	25283	1			T2	1		T3	220		T8	3
valid_sources[0x1c]	25912	1			T2	2		T3	268		T7	6
valid_sources[0x1d]	26427	1			T1	1		T2	8		T3	236
valid_sources[0x1e]	25395	1			T2	1		T3	170		T7	4
valid_sources[0x1f]	24996	1			T2	5		T3	242		T7	3
valid_sources[0x20]	25395	1			T2	31		T3	213		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23918

1

T1

3

T2

14

T3

183

values[0x0]

all_enables

biggest_size

177299

1

T1

15

T2

12

T3

1546

values[0x1]

all_enables

biggest_size

23867

1

T2

14

T3

208

T7

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1430387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233577

1

T1

23

T2

39

T3

2095

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569601	1			T1	59		T2	205		T3	4783
values[0x0]	524630	1			T1	59		T2	32		T3	4715
values[0x1]	569733	1			T1	54		T2	221		T3	4886

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1097492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

566472

1

T1

58

T2

156

T3

4849

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26243	1			T1	3		T2	10		T3	288
valid_sources[0x01]	25664	1			T1	2		T2	8		T3	194
valid_sources[0x02]	26547	1			T1	5		T2	7		T3	253
valid_sources[0x03]	25975	1			T1	1		T2	8		T3	235
valid_sources[0x04]	25404	1			T1	3		T2	6		T3	179
valid_sources[0x05]	25407	1			T1	3		T2	11		T3	259
valid_sources[0x06]	25534	1			T1	2		T2	8		T3	217
valid_sources[0x07]	26536	1			T1	2		T2	6		T3	244
valid_sources[0x08]	26141	1			T1	5		T2	8		T3	163
valid_sources[0x09]	25672	1			T1	5		T2	9		T3	225
valid_sources[0x0a]	26308	1			T1	1		T2	7		T3	271
valid_sources[0x0b]	26355	1			T1	1		T2	7		T3	267
valid_sources[0x0c]	26147	1			T1	3		T2	4		T3	232
valid_sources[0x0d]	25744	1			T1	4		T2	8		T3	278
valid_sources[0x0e]	25417	1			T1	3		T2	7		T3	239
valid_sources[0x0f]	25710	1			T1	1		T2	5		T3	181
valid_sources[0x10]	25792	1			T1	2		T2	8		T3	190
valid_sources[0x11]	25721	1			T1	1		T2	7		T3	209
valid_sources[0x12]	25650	1			T1	4		T2	13		T3	188
valid_sources[0x13]	25562	1			T1	2		T2	5		T3	219
valid_sources[0x14]	26652	1			T1	3		T2	7		T3	262
valid_sources[0x15]	26188	1			T1	2		T2	7		T3	174
valid_sources[0x16]	26101	1			T1	5		T2	5		T3	177
valid_sources[0x17]	25543	1			T1	3		T2	8		T3	196
valid_sources[0x18]	27214	1			T1	3		T2	3		T3	210
valid_sources[0x19]	26076	1			T1	2		T2	6		T3	200
valid_sources[0x1a]	26027	1			T1	3		T2	4		T3	291
valid_sources[0x1b]	25731	1			T2	10		T3	207		T8	4
valid_sources[0x1c]	25926	1			T1	4		T2	6		T3	193
valid_sources[0x1d]	26941	1			T1	2		T2	11		T3	238
valid_sources[0x1e]	25850	1			T1	4		T2	12		T3	198
valid_sources[0x1f]	25354	1			T1	2		T2	10		T3	236
valid_sources[0x20]	25658	1			T1	4		T2	12		T3	215

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24747

1

T1

4

T2

12

T3

205

values[0x0]

all_enables

biggest_size

183953

1

T1

16

T2

16

T3

1697

values[0x1]

all_enables

biggest_size

24877

1

T1

3

T2

11

T3

193

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1431313	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

227567

1

T1

28

T2

41

T3

2058

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	563217	1			T1	74		T2	191		T3	4832
values[0x0]	532186	1			T1	66		T2	31		T3	4850
values[0x1]	563477	1			T1	58		T2	187		T3	4958

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1105306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

553574

1

T1

66

T2

146

T3

4916

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26327	1			T2	8		T3	260		T7	1
valid_sources[0x01]	26555	1			T2	3		T3	215		T7	3
valid_sources[0x02]	26087	1			T1	3		T2	4		T3	165
valid_sources[0x03]	25926	1			T2	10		T3	216		T7	4
valid_sources[0x04]	26616	1			T2	4		T3	227		T7	2
valid_sources[0x05]	25715	1			T2	4		T3	232		T7	3
valid_sources[0x06]	25749	1			T2	4		T3	239		T7	3
valid_sources[0x07]	25625	1			T2	4		T3	219		T7	5
valid_sources[0x08]	25397	1			T2	10		T3	207		T7	1
valid_sources[0x09]	26494	1			T2	7		T3	218		T8	5
valid_sources[0x0a]	26581	1			T2	6		T3	232		T7	2
valid_sources[0x0b]	26150	1			T1	6		T2	3		T3	258
valid_sources[0x0c]	26243	1			T2	7		T3	227		T10	2
valid_sources[0x0d]	25626	1			T2	12		T3	227		T7	2
valid_sources[0x0e]	25175	1			T2	7		T3	222		T7	3
valid_sources[0x0f]	25737	1			T2	9		T3	178		T7	1
valid_sources[0x10]	26286	1			T1	18		T2	7		T3	238
valid_sources[0x11]	25623	1			T2	14		T3	213		T7	5
valid_sources[0x12]	25514	1			T1	6		T2	8		T3	242
valid_sources[0x13]	25561	1			T1	3		T2	8		T3	237
valid_sources[0x14]	26436	1			T2	11		T3	253		T7	3
valid_sources[0x15]	25273	1			T2	5		T3	227		T7	2
valid_sources[0x16]	26418	1			T2	4		T3	262		T10	1
valid_sources[0x17]	25349	1			T2	7		T3	210		T7	3
valid_sources[0x18]	25590	1			T2	10		T3	212		T7	2
valid_sources[0x19]	25568	1			T2	3		T3	231		T7	5
valid_sources[0x1a]	26525	1			T2	1		T3	245		T7	2
valid_sources[0x1b]	25559	1			T2	3		T3	203		T7	2
valid_sources[0x1c]	26825	1			T2	9		T3	203		T7	2
valid_sources[0x1d]	26476	1			T2	6		T3	223		T8	7
valid_sources[0x1e]	25120	1			T2	7		T3	200		T7	1
valid_sources[0x1f]	25630	1			T2	7		T3	200		T7	1
valid_sources[0x20]	25742	1			T3	184		T7	1		T8	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23978

1

T1

3

T2

15

T3

221

values[0x0]

all_enables

biggest_size

179898

1

T1

24

T2

13

T3

1655

values[0x1]

all_enables

biggest_size

23691

1

T1

1

T2

13

T3

182