Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7417460	0	0
GntImpliesValid_A	2147483647	7417460	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7417460	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	438391241	0	0
ReadyAndValidImplyGrant_A	2147483647	7417460	0	0
ReqAndReadyImplyGrant_A	2147483647	7417460	0	0
ReqImpliesValid_A	2147483647	32278184	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42133	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7417460	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64752	63408	0	0
T2	1320672	1319976	0	0
T3	9206808	9206520	0	0
T7	258168	257784	0	0
T8	7192320	7190280	0	0
T9	413136	411792	0	0
T10	50472	46944	0	0
T11	1293072	1292280	0	0
T12	263640	263256	0	0
T13	11410368	11409216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64752	63408	0	0
T2	1320672	1319976	0	0
T3	9206808	9206520	0	0
T7	258168	257784	0	0
T8	7192320	7190280	0	0
T9	413136	411792	0	0
T10	50472	46944	0	0
T11	1293072	1292280	0	0
T12	263640	263256	0	0
T13	11410368	11409216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64752	63408	0	0
T2	1320672	1319976	0	0
T3	9206808	9206520	0	0
T7	258168	257784	0	0
T8	7192320	7190280	0	0
T9	413136	411792	0	0
T10	50472	46944	0	0
T11	1293072	1292280	0	0
T12	263640	263256	0	0
T13	11410368	11409216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	438391241	0	0
T1	64752	743	0	0
T2	1320672	18849	0	0
T3	9206808	503039	0	0
T7	258168	12889	0	0
T8	7192320	251796	0	0
T9	413136	24043	0	0
T10	50472	1123	0	0
T11	1293072	86681	0	0
T12	263640	12965	0	0
T13	11410368	619478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32278184	0	0
T1	64752	613	0	0
T2	1320672	50129	0	0
T3	9206808	146496	0	0
T7	258168	1157	0	0
T8	7192320	802	0	0
T9	413136	2589	0	0
T10	50472	1390	0	0
T11	1293072	15010	0	0
T12	263640	905	0	0
T13	11410368	28367	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42133	0	21600
T2	110056	383	0	2
T3	767234	90	0	2
T7	21514	0	0	2
T8	599360	0	0	2
T9	34428	0	0	2
T10	4206	4	0	2
T11	107756	0	0	2
T12	21970	0	0	2
T13	950864	0	0	2
T14	250246	3	0	2
T15	0	15	0	0
T16	0	25	0	0
T17	0	11	0	0
T18	0	292	0	0
T19	0	3	0	0
T20	0	1	0	0
T21	0	11	0	0
T22	0	3	0	0
T23	0	75	0	0
T24	0	7	0	0
T25	0	1	0	0
T26	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	64752	63408	0	0
T2	1320672	1319976	0	0
T3	9206808	9206520	0	0
T7	258168	257784	0	0
T8	7192320	7190280	0	0
T9	413136	411792	0	0
T10	50472	46944	0	0
T11	1293072	1292280	0	0
T12	263640	263256	0	0
T13	11410368	11409216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7417460	0	0
T1	64752	558	0	0
T2	1320672	29316	0	0
T3	9206808	39254	0	0
T7	258168	496	0	0
T8	7192320	518	0	0
T9	413136	1198	0	0
T10	50472	1228	0	0
T11	1293072	6511	0	0
T12	263640	504	0	0
T13	11410368	496	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	813988	0	0
GntImpliesValid_A	401861567	813988	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	813988	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	11277481	0	0
ReadyAndValidImplyGrant_A	401861567	813988	0	0
ReqAndReadyImplyGrant_A	401861567	813988	0	0
ReqImpliesValid_A	401861567	2245577	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	813988	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	11277481	0	0
T1	2698	51	0	0
T2	55028	2079	0	0
T3	383617	27746	0	0
T7	10757	561	0	0
T8	299680	291	0	0
T9	17214	973	0	0
T10	2103	135	0	0
T11	53878	4751	0	0
T12	10985	376	0	0
T13	475432	22683	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2245577	0	0
T1	2698	74	0	0
T2	55028	3426	0	0
T3	383617	6281	0	0
T7	10757	117	0	0
T8	299680	105	0	0
T9	17214	201	0	0
T10	2103	217	0	0
T11	53878	1204	0	0
T12	10985	91	0	0
T13	475432	3270	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	813988	0	0
T1	2698	62	0	0
T2	55028	2752	0	0
T3	383617	3812	0	0
T7	10757	71	0	0
T8	299680	76	0	0
T9	17214	133	0	0
T10	2103	173	0	0
T11	53878	639	0	0
T12	10985	48	0	0
T13	475432	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	820848	0	0
GntImpliesValid_A	401861567	820848	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	820848	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	11307972	0	0
ReadyAndValidImplyGrant_A	401861567	820848	0	0
ReqAndReadyImplyGrant_A	401861567	820848	0	0
ReqImpliesValid_A	401861567	2269951	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	820848	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	11307972	0	0
T1	2698	46	0	0
T2	55028	2170	0	0
T3	383617	30066	0	0
T7	10757	367	0	0
T8	299680	273	0	0
T9	17214	988	0	0
T10	2103	144	0	0
T11	53878	5019	0	0
T12	10985	367	0	0
T13	475432	15152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2269951	0	0
T1	2698	83	0	0
T2	55028	5003	0	0
T3	383617	18907	0	0
T7	10757	98	0	0
T8	299680	59	0	0
T9	17214	188	0	0
T10	2103	237	0	0
T11	53878	1379	0	0
T12	10985	100	0	0
T13	475432	2715	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	820848	0	0
T1	2698	64	0	0
T2	55028	3586	0	0
T3	383617	5097	0	0
T7	10757	48	0	0
T8	299680	58	0	0
T9	17214	134	0	0
T10	2103	188	0	0
T11	53878	761	0	0
T12	10985	51	0	0
T13	475432	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	197562	0	0
GntImpliesValid_A	401861567	197562	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	197562	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2786029	0	0
ReadyAndValidImplyGrant_A	401861567	197562	0	0
ReqAndReadyImplyGrant_A	401861567	197562	0	0
ReqImpliesValid_A	401861567	546997	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	197562	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2786029	0	0
T1	2698	11	0	0
T2	55028	529	0	0
T3	383617	9786	0	0
T7	10757	46	0	0
T8	299680	42	0	0
T9	17214	293	0	0
T10	2103	33	0	0
T11	53878	1504	0	0
T12	10985	122	0	0
T13	475432	5661	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	546997	0	0
T1	2698	10	0	0
T2	55028	1158	0	0
T3	383617	16493	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	45	0	0
T10	2103	27	0	0
T11	53878	305	0	0
T12	10985	39	0	0
T13	475432	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197562	0	0
T1	2698	10	0	0
T2	55028	843	0	0
T3	383617	2517	0	0
T7	10757	7	0	0
T8	299680	12	0	0
T9	17214	38	0	0
T10	2103	27	0	0
T11	53878	198	0	0
T12	10985	17	0	0
T13	475432	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	196956	0	0
GntImpliesValid_A	401861567	196956	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	196956	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2772876	0	0
ReadyAndValidImplyGrant_A	401861567	196956	0	0
ReqAndReadyImplyGrant_A	401861567	196956	0	0
ReqImpliesValid_A	401861567	451163	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	196956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2772876	0	0
T1	2698	26	0	0
T2	55028	430	0	0
T3	383617	4706	0	0
T7	10757	89	0	0
T8	299680	66	0	0
T9	17214	223	0	0
T10	2103	27	0	0
T11	53878	1497	0	0
T12	10985	115	0	0
T13	475432	4568	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	451163	0	0
T1	2698	25	0	0
T2	55028	1291	0	0
T3	383617	790	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	41	0	0
T10	2103	21	0	0
T11	53878	290	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196956	0	0
T1	2698	25	0	0
T2	55028	860	0	0
T3	383617	613	0	0
T7	10757	13	0	0
T8	299680	19	0	0
T9	17214	28	0	0
T10	2103	21	0	0
T11	53878	209	0	0
T12	10985	15	0	0
T13	475432	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	207009	0	0
GntImpliesValid_A	401861567	207009	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	207009	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	5279645	0	0
ReadyAndValidImplyGrant_A	401861567	207009	0	0
ReqAndReadyImplyGrant_A	401861567	207009	0	0
ReqImpliesValid_A	401861567	1172998	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	207009	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	5279645	0	0
T1	2698	97	0	0
T2	55028	1848	0	0
T3	383617	3103	0	0
T7	10757	312	0	0
T8	299680	317	0	0
T9	17214	559	0	0
T10	2103	102	0	0
T11	53878	1690	0	0
T12	10985	129	0	0
T13	475432	6956	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	1172998	0	0
T1	2698	20	0	0
T2	55028	2845	0	0
T3	383617	703	0	0
T7	10757	20	0	0
T8	299680	14	0	0
T9	17214	84	0	0
T10	2103	37	0	0
T11	53878	238	0	0
T12	10985	13	0	0
T13	475432	462	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207009	0	0
T1	2698	13	0	0
T2	55028	741	0	0
T3	383617	637	0	0
T7	10757	13	0	0
T8	299680	14	0	0
T9	17214	33	0	0
T10	2103	30	0	0
T11	53878	156	0	0
T12	10985	13	0	0
T13	475432	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	212891	0	0
GntImpliesValid_A	401861567	212891	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	212891	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	5895440	0	0
ReadyAndValidImplyGrant_A	401861567	212891	0	0
ReqAndReadyImplyGrant_A	401861567	212891	0	0
ReqImpliesValid_A	401861567	1282248	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	212891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	5895440	0	0
T1	2698	94	0	0
T2	55028	2382	0	0
T3	383617	6619	0	0
T7	10757	111	0	0
T8	299680	277	0	0
T9	17214	1579	0	0
T10	2103	94	0	0
T11	53878	1587	0	0
T12	10985	89	0	0
T13	475432	3598	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	1282248	0	0
T1	2698	12	0	0
T2	55028	10952	0	0
T3	383617	8740	0	0
T7	10757	10	0	0
T8	299680	53	0	0
T9	17214	146	0	0
T10	2103	37	0	0
T11	53878	252	0	0
T12	10985	18	0	0
T13	475432	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	212891	0	0
T1	2698	12	0	0
T2	55028	2016	0	0
T3	383617	1591	0	0
T7	10757	10	0	0
T8	299680	16	0	0
T9	17214	31	0	0
T10	2103	28	0	0
T11	53878	189	0	0
T12	10985	18	0	0
T13	475432	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	202890	0	0
GntImpliesValid_A	401861567	202890	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	202890	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	5333018	0	0
ReadyAndValidImplyGrant_A	401861567	202890	0	0
ReqAndReadyImplyGrant_A	401861567	202890	0	0
ReqImpliesValid_A	401861567	1098196	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	202890	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	5333018	0	0
T1	2698	102	0	0
T2	55028	1708	0	0
T3	383617	5105	0	0
T7	10757	151	0	0
T8	299680	97	0	0
T9	17214	316	0	0
T10	2103	46	0	0
T11	53878	1362	0	0
T12	10985	60	0	0
T13	475432	9233	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	1098196	0	0
T1	2698	23	0	0
T2	55028	2905	0	0
T3	383617	3180	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	60	0	0
T10	2103	33	0	0
T11	53878	280	0	0
T12	10985	9	0	0
T13	475432	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	202890	0	0
T1	2698	19	0	0
T2	55028	857	0	0
T3	383617	1107	0	0
T7	10757	10	0	0
T8	299680	11	0	0
T9	17214	36	0	0
T10	2103	17	0	0
T11	53878	189	0	0
T12	10985	9	0	0
T13	475432	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	195641	0	0
GntImpliesValid_A	401861567	195641	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	195641	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	5094634	0	0
ReadyAndValidImplyGrant_A	401861567	195641	0	0
ReqAndReadyImplyGrant_A	401861567	195641	0	0
ReqImpliesValid_A	401861567	1036757	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	195641	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	5094634	0	0
T1	2698	86	0	0
T2	55028	1612	0	0
T3	383617	2949	0	0
T7	10757	95	0	0
T8	299680	195	0	0
T9	17214	344	0	0
T10	2103	132	0	0
T11	53878	1577	0	0
T12	10985	96	0	0
T13	475432	7620	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	1036757	0	0
T1	2698	11	0	0
T2	55028	510	0	0
T3	383617	687	0	0
T7	10757	17	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	46	0	0
T11	53878	214	0	0
T12	10985	31	0	0
T13	475432	2437	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	195641	0	0
T1	2698	11	0	0
T2	55028	400	0	0
T3	383617	648	0	0
T7	10757	9	0	0
T8	299680	13	0	0
T9	17214	32	0	0
T10	2103	25	0	0
T11	53878	142	0	0
T12	10985	18	0	0
T13	475432	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	205914	0	0
GntImpliesValid_A	401861567	205914	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	205914	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2825452	0	0
ReadyAndValidImplyGrant_A	401861567	205914	0	0
ReqAndReadyImplyGrant_A	401861567	205914	0	0
ReqImpliesValid_A	401861567	514647	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	205914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2825452	0	0
T1	2698	25	0	0
T2	55028	351	0	0
T3	383617	7153	0	0
T7	10757	60	0	0
T8	299680	37	0	0
T9	17214	272	0	0
T10	2103	27	0	0
T11	53878	1368	0	0
T12	10985	83	0	0
T13	475432	2102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	514647	0	0
T1	2698	26	0	0
T2	55028	368	0	0
T3	383617	4610	0	0
T7	10757	9	0	0
T8	299680	12	0	0
T9	17214	45	0	0
T10	2103	21	0	0
T11	53878	246	0	0
T12	10985	12	0	0
T13	475432	436	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	205914	0	0
T1	2698	25	0	0
T2	55028	359	0	0
T3	383617	1584	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	35	0	0
T10	2103	21	0	0
T11	53878	177	0	0
T12	10985	12	0	0
T13	475432	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	204841	0	0
GntImpliesValid_A	401861567	204841	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	204841	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2839366	0	0
ReadyAndValidImplyGrant_A	401861567	204841	0	0
ReqAndReadyImplyGrant_A	401861567	204841	0	0
ReqImpliesValid_A	401861567	528859	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	204841	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2839366	0	0
T1	2698	13	0	0
T2	55028	467	0	0
T3	383617	4698	0	0
T7	10757	87	0	0
T8	299680	49	0	0
T9	17214	204	0	0
T10	2103	35	0	0
T11	53878	1588	0	0
T12	10985	130	0	0
T13	475432	5473	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	528859	0	0
T1	2698	12	0	0
T2	55028	1430	0	0
T3	383617	780	0	0
T7	10757	24	0	0
T8	299680	14	0	0
T9	17214	31	0	0
T10	2103	43	0	0
T11	53878	329	0	0
T12	10985	31	0	0
T13	475432	124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	204841	0	0
T1	2698	12	0	0
T2	55028	948	0	0
T3	383617	637	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	36	0	0
T11	53878	201	0	0
T12	10985	16	0	0
T13	475432	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	213140	0	0
GntImpliesValid_A	401861567	213140	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	213140	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2846470	0	0
ReadyAndValidImplyGrant_A	401861567	213140	0	0
ReqAndReadyImplyGrant_A	401861567	213140	0	0
ReqImpliesValid_A	401861567	544528	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	213140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2846470	0	0
T1	2698	18	0	0
T2	55028	430	0	0
T3	383617	5432	0	0
T7	10757	102	0	0
T8	299680	55	0	0
T9	17214	258	0	0
T10	2103	30	0	0
T11	53878	1584	0	0
T12	10985	121	0	0
T13	475432	4453	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	544528	0	0
T1	2698	19	0	0
T2	55028	2223	0	0
T3	383617	4731	0	0
T7	10757	13	0	0
T8	299680	21	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	303	0	0
T12	10985	21	0	0
T13	475432	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213140	0	0
T1	2698	18	0	0
T2	55028	1326	0	0
T3	383617	1060	0	0
T7	10757	13	0	0
T8	299680	13	0	0
T9	17214	37	0	0
T10	2103	24	0	0
T11	53878	208	0	0
T12	10985	19	0	0
T13	475432	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	197111	0	0
GntImpliesValid_A	401861567	197111	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	197111	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2821295	0	0
ReadyAndValidImplyGrant_A	401861567	197111	0	0
ReqAndReadyImplyGrant_A	401861567	197111	0	0
ReqImpliesValid_A	401861567	499061	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	197111	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2821295	0	0
T1	2698	20	0	0
T2	55028	393	0	0
T3	383617	4620	0	0
T7	10757	114	0	0
T8	299680	60	0	0
T9	17214	225	0	0
T10	2103	30	0	0
T11	53878	1312	0	0
T12	10985	197	0	0
T13	475432	5998	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	499061	0	0
T1	2698	19	0	0
T2	55028	1574	0	0
T3	383617	747	0	0
T7	10757	29	0	0
T8	299680	13	0	0
T9	17214	41	0	0
T10	2103	24	0	0
T11	53878	310	0	0
T12	10985	25	0	0
T13	475432	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	197111	0	0
T1	2698	19	0	0
T2	55028	983	0	0
T3	383617	591	0	0
T7	10757	16	0	0
T8	299680	13	0	0
T9	17214	28	0	0
T10	2103	24	0	0
T11	53878	194	0	0
T12	10985	21	0	0
T13	475432	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	213561	0	0
GntImpliesValid_A	401861567	213561	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	213561	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2891402	0	0
ReadyAndValidImplyGrant_A	401861567	213561	0	0
ReqAndReadyImplyGrant_A	401861567	213561	0	0
ReqImpliesValid_A	401861567	596886	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	213561	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2891402	0	0
T1	2698	18	0	0
T2	55028	566	0	0
T3	383617	6021	0	0
T7	10757	150	0	0
T8	299680	46	0	0
T9	17214	214	0	0
T10	2103	35	0	0
T11	53878	1316	0	0
T12	10985	148	0	0
T13	475432	6199	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	596886	0	0
T1	2698	19	0	0
T2	55028	1225	0	0
T3	383617	11345	0	0
T7	10757	17	0	0
T8	299680	19	0	0
T9	17214	39	0	0
T10	2103	33	0	0
T11	53878	317	0	0
T12	10985	22	0	0
T13	475432	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	213561	0	0
T1	2698	18	0	0
T2	55028	895	0	0
T3	383617	1691	0	0
T7	10757	17	0	0
T8	299680	14	0	0
T9	17214	37	0	0
T10	2103	31	0	0
T11	53878	199	0	0
T12	10985	22	0	0
T13	475432	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	211790	0	0
GntImpliesValid_A	401861567	211790	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	211790	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2829724	0	0
ReadyAndValidImplyGrant_A	401861567	211790	0	0
ReqAndReadyImplyGrant_A	401861567	211790	0	0
ReqImpliesValid_A	401861567	552174	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	211790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2829724	0	0
T1	2698	13	0	0
T2	55028	409	0	0
T3	383617	4817	0	0
T7	10757	111	0	0
T8	299680	39	0	0
T9	17214	295	0	0
T10	2103	23	0	0
T11	53878	1307	0	0
T12	10985	135	0	0
T13	475432	4335	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	552174	0	0
T1	2698	14	0	0
T2	55028	448	0	0
T3	383617	832	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	59	0	0
T10	2103	17	0	0
T11	53878	219	0	0
T12	10985	18	0	0
T13	475432	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211790	0	0
T1	2698	13	0	0
T2	55028	428	0	0
T3	383617	647	0	0
T7	10757	13	0	0
T8	299680	8	0	0
T9	17214	39	0	0
T10	2103	17	0	0
T11	53878	185	0	0
T12	10985	18	0	0
T13	475432	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	196412	0	0
GntImpliesValid_A	401861567	196412	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	196412	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2866278	0	0
ReadyAndValidImplyGrant_A	401861567	196412	0	0
ReqAndReadyImplyGrant_A	401861567	196412	0	0
ReqImpliesValid_A	401861567	496606	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	196412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2866278	0	0
T1	2698	15	0	0
T2	55028	421	0	0
T3	383617	5647	0	0
T7	10757	101	0	0
T8	299680	70	0	0
T9	17214	101	0	0
T10	2103	26	0	0
T11	53878	1301	0	0
T12	10985	73	0	0
T13	475432	3452	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	496606	0	0
T1	2698	16	0	0
T2	55028	1318	0	0
T3	383617	2700	0	0
T7	10757	27	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	22	0	0
T11	53878	253	0	0
T12	10985	19	0	0
T13	475432	1541	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	196412	0	0
T1	2698	15	0	0
T2	55028	869	0	0
T3	383617	1089	0	0
T7	10757	15	0	0
T8	299680	14	0	0
T9	17214	16	0	0
T10	2103	21	0	0
T11	53878	185	0	0
T12	10985	15	0	0
T13	475432	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	209101	0	0
GntImpliesValid_A	401861567	209101	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	209101	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2774368	0	0
ReadyAndValidImplyGrant_A	401861567	209101	0	0
ReqAndReadyImplyGrant_A	401861567	209101	0	0
ReqImpliesValid_A	401861567	553228	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	209101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2774368	0	0
T1	2698	10	0	0
T2	55028	492	0	0
T3	383617	4982	0	0
T7	10757	66	0	0
T8	299680	41	0	0
T9	17214	270	0	0
T10	2103	23	0	0
T11	53878	1497	0	0
T12	10985	133	0	0
T13	475432	6350	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	553228	0	0
T1	2698	9	0	0
T2	55028	1469	0	0
T3	383617	5730	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	75	0	0
T10	2103	20	0	0
T11	53878	280	0	0
T12	10985	22	0	0
T13	475432	1359	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	209101	0	0
T1	2698	9	0	0
T2	55028	980	0	0
T3	383617	1082	0	0
T7	10757	9	0	0
T8	299680	10	0	0
T9	17214	40	0	0
T10	2103	19	0	0
T11	53878	190	0	0
T12	10985	21	0	0
T13	475432	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	227835	0	0
GntImpliesValid_A	401861567	227835	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	227835	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2940644	0	0
ReadyAndValidImplyGrant_A	401861567	227835	0	0
ReqAndReadyImplyGrant_A	401861567	227835	0	0
ReqImpliesValid_A	401861567	580772	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	227835	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2940644	0	0
T1	2698	11	0	0
T2	55028	439	0	0
T3	383617	8263	0	0
T7	10757	111	0	0
T8	299680	76	0	0
T9	17214	447	0	0
T10	2103	29	0	0
T11	53878	1249	0	0
T12	10985	122	0	0
T13	475432	3420	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	580772	0	0
T1	2698	10	0	0
T2	55028	468	0	0
T3	383617	7276	0	0
T7	10757	36	0	0
T8	299680	34	0	0
T9	17214	83	0	0
T10	2103	23	0	0
T11	53878	266	0	0
T12	10985	28	0	0
T13	475432	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	227835	0	0
T1	2698	10	0	0
T2	55028	453	0	0
T3	383617	2143	0	0
T7	10757	16	0	0
T8	299680	19	0	0
T9	17214	63	0	0
T10	2103	23	0	0
T11	53878	177	0	0
T12	10985	15	0	0
T13	475432	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	207481	0	0
GntImpliesValid_A	401861567	207481	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	207481	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2865730	0	0
ReadyAndValidImplyGrant_A	401861567	207481	0	0
ReqAndReadyImplyGrant_A	401861567	207481	0	0
ReqImpliesValid_A	401861567	545655	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	207481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2865730	0	0
T1	2698	14	0	0
T2	55028	431	0	0
T3	383617	8575	0	0
T7	10757	81	0	0
T8	299680	50	0	0
T9	17214	335	0	0
T10	2103	30	0	0
T11	53878	1175	0	0
T12	10985	153	0	0
T13	475432	3628	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	545655	0	0
T1	2698	17	0	0
T2	55028	456	0	0
T3	383617	7695	0	0
T7	10757	11	0	0
T8	299680	21	0	0
T9	17214	35	0	0
T10	2103	28	0	0
T11	53878	314	0	0
T12	10985	23	0	0
T13	475432	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207481	0	0
T1	2698	15	0	0
T2	55028	443	0	0
T3	383617	1651	0	0
T7	10757	11	0	0
T8	299680	14	0	0
T9	17214	35	0	0
T10	2103	26	0	0
T11	53878	179	0	0
T12	10985	16	0	0
T13	475432	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	203846	0	0
GntImpliesValid_A	401861567	203846	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	203846	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2764683	0	0
ReadyAndValidImplyGrant_A	401861567	203846	0	0
ReqAndReadyImplyGrant_A	401861567	203846	0	0
ReqImpliesValid_A	401861567	515985	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	203846	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2764683	0	0
T1	2698	25	0	0
T2	55028	432	0	0
T3	383617	5310	0	0
T7	10757	128	0	0
T8	299680	59	0	0
T9	17214	225	0	0
T10	2103	30	0	0
T11	53878	1237	0	0
T12	10985	89	0	0
T13	475432	5912	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	515985	0	0
T1	2698	26	0	0
T2	55028	1361	0	0
T3	383617	5319	0	0
T7	10757	37	0	0
T8	299680	13	0	0
T9	17214	34	0	0
T10	2103	26	0	0
T11	53878	241	0	0
T12	10985	30	0	0
T13	475432	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203846	0	0
T1	2698	25	0	0
T2	55028	896	0	0
T3	383617	1045	0	0
T7	10757	21	0	0
T8	299680	13	0	0
T9	17214	31	0	0
T10	2103	25	0	0
T11	53878	166	0	0
T12	10985	17	0	0
T13	475432	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	211216	0	0
GntImpliesValid_A	401861567	211216	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	211216	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2891829	0	0
ReadyAndValidImplyGrant_A	401861567	211216	0	0
ReqAndReadyImplyGrant_A	401861567	211216	0	0
ReqImpliesValid_A	401861567	588103	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	211216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2891829	0	0
T1	2698	18	0	0
T2	55028	420	0	0
T3	383617	4439	0	0
T7	10757	133	0	0
T8	299680	88	0	0
T9	17214	247	0	0
T10	2103	28	0	0
T11	53878	1396	0	0
T12	10985	81	0	0
T13	475432	4188	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	588103	0	0
T1	2698	21	0	0
T2	55028	2389	0	0
T3	383617	715	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	52	0	0
T10	2103	24	0	0
T11	53878	317	0	0
T12	10985	15	0	0
T13	475432	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	211216	0	0
T1	2698	19	0	0
T2	55028	1404	0	0
T3	383617	607	0	0
T7	10757	17	0	0
T8	299680	20	0	0
T9	17214	34	0	0
T10	2103	23	0	0
T11	53878	190	0	0
T12	10985	15	0	0
T13	475432	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	203480	0	0
GntImpliesValid_A	401861567	203480	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	203480	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2822323	0	0
ReadyAndValidImplyGrant_A	401861567	203480	0	0
ReqAndReadyImplyGrant_A	401861567	203480	0	0
ReqImpliesValid_A	401861567	569356	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	203480	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2822323	0	0
T1	2698	11	0	0
T2	55028	435	0	0
T3	383617	4698	0	0
T7	10757	131	0	0
T8	299680	49	0	0
T9	17214	206	0	0
T10	2103	25	0	0
T11	53878	1205	0	0
T12	10985	68	0	0
T13	475432	3719	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	569356	0	0
T1	2698	14	0	0
T2	55028	460	0	0
T3	383617	705	0	0
T7	10757	21	0	0
T8	299680	17	0	0
T9	17214	58	0	0
T10	2103	20	0	0
T11	53878	244	0	0
T12	10985	14	0	0
T13	475432	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	203480	0	0
T1	2698	12	0	0
T2	55028	447	0	0
T3	383617	627	0	0
T7	10757	18	0	0
T8	299680	13	0	0
T9	17214	27	0	0
T10	2103	20	0	0
T11	53878	165	0	0
T12	10985	12	0	0
T13	475432	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	207521	0	0
GntImpliesValid_A	401861567	207521	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	207521	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	2896245	0	0
ReadyAndValidImplyGrant_A	401861567	207521	0	0
ReqAndReadyImplyGrant_A	401861567	207521	0	0
ReqImpliesValid_A	401861567	527212	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	0	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	207521	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2896245	0	0
T1	2698	17	0	0
T2	55028	403	0	0
T3	383617	4917	0	0
T7	10757	125	0	0
T8	299680	56	0	0
T9	17214	323	0	0
T10	2103	32	0	0
T11	53878	1196	0	0
T12	10985	105	0	0
T13	475432	2856	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	527212	0	0
T1	2698	18	0	0
T2	55028	442	0	0
T3	383617	740	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	46	0	0
T10	2103	28	0	0
T11	53878	223	0	0
T12	10985	18	0	0
T13	475432	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	207521	0	0
T1	2698	17	0	0
T2	55028	422	0	0
T3	383617	636	0	0
T7	10757	16	0	0
T8	299680	10	0	0
T9	17214	39	0	0
T10	2103	27	0	0
T11	53878	155	0	0
T12	10985	11	0	0
T13	475432	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	826495	0	0
GntImpliesValid_A	401861567	826495	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	826495	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	10485803	0	0
ReadyAndValidImplyGrant_A	401861567	826495	0	0
ReqAndReadyImplyGrant_A	401861567	826495	0	0
ReqImpliesValid_A	401861567	2078185	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	15850	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	826495	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	10485803	0	0
T1	2698	1	0	0
T2	55028	1	0	0
T3	383617	24190	0	0
T7	10757	338	0	0
T8	299680	181	0	0
T9	17214	784	0	0
T10	2103	6	0	0
T11	53878	4976	0	0
T12	10985	287	0	0
T13	475432	20309	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	2078185	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	5842	0	0
T7	10757	59	0	0
T8	299680	77	0	0
T9	17214	145	0	0
T10	2103	190	0	0
T11	53878	1365	0	0
T12	10985	80	0	0
T13	475432	2693	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	15850	0	900
T2	55028	353	0	1
T3	383617	1	0	1
T7	10757	0	0	1
T8	299680	0	0	1
T9	17214	0	0	1
T10	2103	4	0	1
T11	53878	0	0	1
T12	10985	0	0	1
T13	475432	0	0	1
T14	125123	0	0	1
T15	0	15	0	0
T16	0	8	0	0
T17	0	5	0	0
T18	0	292	0	0
T21	0	11	0	0
T22	0	3	0	0
T23	0	75	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	826495	0	0
T1	2698	57	0	0
T2	55028	3641	0	0
T3	383617	3740	0	0
T7	10757	44	0	0
T8	299680	66	0	0
T9	17214	124	0	0
T10	2103	190	0	0
T11	53878	758	0	0
T12	10985	49	0	0
T13	475432	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401861567	401747197	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401861567	829931	0	0
GntImpliesValid_A	401861567	829931	0	0
GrantKnown_A	401861567	401747197	0	0
IdxKnown_A	401861567	401747197	0	0
IndexIsCorrect_A	401861567	829931	0	0
LockArbDecision_A	401861567	0	0	0
NoReadyValidNoGrant_A	401861567	338282534	0	0
ReadyAndValidImplyGrant_A	401861567	829931	0	0
ReqAndReadyImplyGrant_A	401861567	829931	0	0
ReqImpliesValid_A	401861567	12483040	0	0
ReqStaysHighUntilGranted0_M	401861567	0	0	0
RoundRobin_A	401861567	26283	0	900
ValidKnown_A	401861567	401747197	0	0
gen_data_port_assertion.DataFlow_A	401861567	829931	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	338282534	0	0
T1	2698	1	0	0
T2	55028	1	0	0
T3	383617	309197	0	0
T7	10757	9319	0	0
T8	299680	249282	0	0
T9	17214	14362	0	0
T10	2103	1	0	0
T11	53878	43987	0	0
T12	10985	9686	0	0
T13	475432	461613	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	12483040	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	30948	0	0
T7	10757	524	0	0
T8	299680	213	0	0
T9	17214	996	0	0
T10	2103	192	0	0
T11	53878	5621	0	0
T12	10985	211	0	0
T13	475432	12873	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	26283	0	900
T2	55028	30	0	1
T3	383617	89	0	1
T7	10757	0	0	1
T8	299680	0	0	1
T9	17214	0	0	1
T10	2103	0	0	1
T11	53878	0	0	1
T12	10985	0	0	1
T13	475432	0	0	1
T14	125123	3	0	1
T16	0	17	0	0
T17	0	6	0	0
T19	0	3	0	0
T20	0	1	0	0
T24	0	7	0	0
T25	0	1	0	0
T26	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	401747197	0	0
T1	2698	2642	0	0
T2	55028	54999	0	0
T3	383617	383605	0	0
T7	10757	10741	0	0
T8	299680	299595	0	0
T9	17214	17158	0	0
T10	2103	1956	0	0
T11	53878	53845	0	0
T12	10985	10969	0	0
T13	475432	475384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401861567	829931	0	0
T1	2698	58	0	0
T2	55028	2767	0	0
T3	383617	4402	0	0
T7	10757	64	0	0
T8	299680	49	0	0
T9	17214	120	0	0
T10	2103	192	0	0
T11	53878	699	0	0
T12	10985	36	0	0
T13	475432	44	0	0