Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1677526 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266278 1 T1 125 T2 112 T3 371


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 658686 1 T1 472 T2 451 T3 954
values[0x0] 626307 1 T1 88 T2 91 T3 965
values[0x1] 658811 1 T1 551 T2 462 T3 990


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1297544 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 646260 1 T1 421 T2 377 T3 919


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29861 1 T1 20 T2 14 T3 46
valid_sources[0x01] 29622 1 T1 25 T2 11 T3 41
valid_sources[0x02] 29832 1 T1 48 T2 12 T3 57
valid_sources[0x03] 30935 1 T1 15 T2 19 T3 48
valid_sources[0x04] 30094 1 T1 15 T2 11 T3 57
valid_sources[0x05] 29586 1 T1 5 T2 15 T3 45
valid_sources[0x06] 30919 1 T1 9 T2 25 T3 48
valid_sources[0x07] 29883 1 T1 15 T2 25 T3 38
valid_sources[0x08] 29916 1 T1 25 T2 20 T3 53
valid_sources[0x09] 30517 1 T1 16 T2 14 T3 41
valid_sources[0x0a] 32753 1 T1 4 T2 18 T3 43
valid_sources[0x0b] 29939 1 T1 21 T2 15 T3 46
valid_sources[0x0c] 31730 1 T1 7 T2 16 T3 51
valid_sources[0x0d] 29496 1 T1 22 T2 14 T3 51
valid_sources[0x0e] 31689 1 T1 11 T2 17 T3 42
valid_sources[0x0f] 30523 1 T1 16 T2 23 T3 39
valid_sources[0x10] 30200 1 T1 11 T2 16 T3 43
valid_sources[0x11] 29528 1 T1 13 T2 20 T3 35
valid_sources[0x12] 30462 1 T1 20 T2 18 T3 41
valid_sources[0x13] 30028 1 T1 10 T2 13 T3 57
valid_sources[0x14] 30278 1 T1 16 T2 14 T3 51
valid_sources[0x15] 30424 1 T1 20 T2 13 T3 42
valid_sources[0x16] 30679 1 T1 31 T2 12 T3 45
valid_sources[0x17] 29876 1 T1 11 T2 14 T3 59
valid_sources[0x18] 31526 1 T1 20 T2 21 T3 47
valid_sources[0x19] 30876 1 T1 17 T2 14 T3 48
valid_sources[0x1a] 30115 1 T1 12 T2 21 T3 49
valid_sources[0x1b] 29190 1 T1 19 T2 11 T3 46
valid_sources[0x1c] 30646 1 T1 11 T2 7 T3 39
valid_sources[0x1d] 31575 1 T1 11 T2 17 T3 48
valid_sources[0x1e] 30655 1 T1 6 T2 11 T3 41
valid_sources[0x1f] 30782 1 T1 49 T2 15 T3 47
valid_sources[0x20] 31059 1 T1 13 T2 17 T3 50


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27737 1 T1 43 T2 34 T3 24
values[0x0] all_enables biggest_size 210808 1 T1 28 T2 43 T3 307
values[0x1] all_enables biggest_size 27733 1 T1 54 T2 35 T3 40


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1695303 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 275795 1 T1 128 T2 112 T3 406


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 675624 1 T1 526 T2 476 T3 1058
values[0x0] 622455 1 T1 113 T2 102 T3 972
values[0x1] 673019 1 T1 494 T2 450 T3 1009


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1301174 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 669924 1 T1 439 T2 399 T3 1004


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29955 1 T1 23 T2 22 T3 45
valid_sources[0x01] 29856 1 T1 20 T2 22 T3 57
valid_sources[0x02] 31700 1 T1 15 T2 20 T3 42
valid_sources[0x03] 30141 1 T1 9 T2 19 T3 49
valid_sources[0x04] 30968 1 T1 16 T2 17 T3 56
valid_sources[0x05] 31042 1 T1 16 T2 10 T3 38
valid_sources[0x06] 30894 1 T1 22 T2 20 T3 53
valid_sources[0x07] 30291 1 T1 24 T2 13 T3 54
valid_sources[0x08] 31219 1 T1 25 T2 16 T3 58
valid_sources[0x09] 31090 1 T1 24 T2 18 T3 50
valid_sources[0x0a] 31727 1 T1 12 T2 23 T3 41
valid_sources[0x0b] 30979 1 T1 19 T2 24 T3 48
valid_sources[0x0c] 30293 1 T1 10 T2 13 T3 49
valid_sources[0x0d] 30810 1 T1 16 T2 14 T3 50
valid_sources[0x0e] 30337 1 T1 21 T2 13 T3 52
valid_sources[0x0f] 30678 1 T1 18 T2 14 T3 50
valid_sources[0x10] 30336 1 T1 11 T2 11 T3 46
valid_sources[0x11] 31001 1 T1 11 T2 26 T3 64
valid_sources[0x12] 30988 1 T1 21 T2 9 T3 44
valid_sources[0x13] 31163 1 T1 20 T2 21 T3 45
valid_sources[0x14] 30473 1 T1 22 T2 14 T3 53
valid_sources[0x15] 31325 1 T1 16 T2 14 T3 53
valid_sources[0x16] 31639 1 T1 14 T2 22 T3 50
valid_sources[0x17] 31391 1 T1 14 T2 16 T3 45
valid_sources[0x18] 30472 1 T1 22 T2 15 T3 41
valid_sources[0x19] 29557 1 T1 10 T2 17 T3 43
valid_sources[0x1a] 30893 1 T1 25 T2 15 T3 37
valid_sources[0x1b] 30892 1 T1 22 T2 14 T3 50
valid_sources[0x1c] 30818 1 T1 13 T2 9 T3 46
valid_sources[0x1d] 31808 1 T1 13 T2 17 T3 49
valid_sources[0x1e] 30991 1 T1 14 T2 24 T3 41
valid_sources[0x1f] 30377 1 T1 21 T2 14 T3 46
valid_sources[0x20] 29876 1 T1 16 T2 12 T3 50


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28923 1 T1 39 T2 36 T3 39
values[0x0] all_enables biggest_size 217967 1 T1 56 T2 37 T3 339
values[0x1] all_enables biggest_size 28905 1 T1 33 T2 39 T3 28


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1690243 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 267664 1 T1 117 T2 98 T3 415


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 662357 1 T1 479 T2 493 T3 1012
values[0x0] 630783 1 T1 87 T2 63 T3 987
values[0x1] 664767 1 T1 473 T2 457 T3 974


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1306642 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 651265 1 T1 397 T2 394 T3 999


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29761 1 T1 13 T2 14 T3 49
valid_sources[0x01] 29964 1 T1 18 T2 21 T3 51
valid_sources[0x02] 30910 1 T1 13 T2 20 T3 53
valid_sources[0x03] 30702 1 T1 13 T2 19 T3 43
valid_sources[0x04] 30516 1 T1 11 T2 12 T3 50
valid_sources[0x05] 30579 1 T1 10 T2 9 T3 42
valid_sources[0x06] 31085 1 T1 11 T2 8 T3 45
valid_sources[0x07] 31157 1 T1 18 T2 9 T3 44
valid_sources[0x08] 30708 1 T1 17 T2 21 T3 42
valid_sources[0x09] 31336 1 T1 16 T2 17 T3 43
valid_sources[0x0a] 31113 1 T1 23 T2 15 T3 41
valid_sources[0x0b] 30766 1 T1 22 T2 20 T3 51
valid_sources[0x0c] 31067 1 T1 15 T2 13 T3 55
valid_sources[0x0d] 30104 1 T1 17 T2 11 T3 49
valid_sources[0x0e] 31433 1 T1 22 T2 15 T3 51
valid_sources[0x0f] 30520 1 T1 22 T2 18 T3 41
valid_sources[0x10] 30230 1 T1 14 T2 13 T3 48
valid_sources[0x11] 31173 1 T1 22 T2 20 T3 54
valid_sources[0x12] 31790 1 T1 9 T2 23 T3 44
valid_sources[0x13] 30550 1 T1 19 T2 18 T3 52
valid_sources[0x14] 29989 1 T1 18 T2 12 T3 43
valid_sources[0x15] 30773 1 T1 19 T2 12 T3 45
valid_sources[0x16] 30992 1 T1 18 T2 10 T3 43
valid_sources[0x17] 30360 1 T1 18 T2 23 T3 47
valid_sources[0x18] 29810 1 T1 18 T2 16 T3 56
valid_sources[0x19] 30173 1 T1 20 T2 14 T3 39
valid_sources[0x1a] 30509 1 T1 14 T2 19 T3 49
valid_sources[0x1b] 29933 1 T1 23 T2 14 T3 46
valid_sources[0x1c] 30306 1 T1 10 T2 11 T3 44
valid_sources[0x1d] 31426 1 T1 19 T2 16 T3 40
valid_sources[0x1e] 30814 1 T1 19 T2 15 T3 51
valid_sources[0x1f] 29185 1 T1 14 T2 19 T3 39
valid_sources[0x20] 30473 1 T1 6 T2 24 T3 40


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27865 1 T1 40 T2 37 T3 36
values[0x0] all_enables biggest_size 211937 1 T1 43 T2 28 T3 336
values[0x1] all_enables biggest_size 27862 1 T1 34 T2 33 T3 43

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%