Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8151307	0	0
GntImpliesValid_A	2147483647	8151307	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8151307	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	460566972	0	0
ReadyAndValidImplyGrant_A	2147483647	8151307	0	0
ReqAndReadyImplyGrant_A	2147483647	8151307	0	0
ReqImpliesValid_A	2147483647	36401503	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46597	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8151307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2973096	2968944	0	0
T2	2684472	2682048	0	0
T3	8510760	8510616	0	0
T4	11278272	11277144	0	0
T5	1121688	1117560	0	0
T7	16781280	16736160	0	0
T8	10947888	10947144	0	0
T9	43488	42816	0	0
T10	978936	943320	0	0
T11	149640	138528	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2973096	2968944	0	0
T2	2684472	2682048	0	0
T3	8510760	8510616	0	0
T4	11278272	11277144	0	0
T5	1121688	1117560	0	0
T7	16781280	16736160	0	0
T8	10947888	10947144	0	0
T9	43488	42816	0	0
T10	978936	943320	0	0
T11	149640	138528	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2973096	2968944	0	0
T2	2684472	2682048	0	0
T3	8510760	8510616	0	0
T4	11278272	11277144	0	0
T5	1121688	1117560	0	0
T7	16781280	16736160	0	0
T8	10947888	10947144	0	0
T9	43488	42816	0	0
T10	978936	943320	0	0
T11	149640	138528	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	460566972	0	0
T1	2973096	65421	0	0
T2	2684472	35902	0	0
T3	8510760	327218	0	0
T4	11278272	603459	0	0
T5	1121688	18942	0	0
T7	16781280	992854	0	0
T8	10947888	582531	0	0
T9	43488	444	0	0
T10	978936	23121	0	0
T11	149640	9191	0	0
T12	0	640	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36401503	0	0
T1	2973096	89396	0	0
T2	2684472	97016	0	0
T3	8510760	22655	0	0
T4	11278272	26941	0	0
T5	1121688	39006	0	0
T7	16781280	247547	0	0
T8	10947888	27098	0	0
T9	43488	467	0	0
T10	978936	24159	0	0
T11	149640	1542	0	0
T12	0	196	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46597	0	21600
T1	247758	482	0	2
T2	223706	415	0	2
T3	709230	0	0	2
T4	939856	0	0	2
T5	93474	1303	0	2
T7	1398440	36	0	2
T8	912324	0	0	2
T9	3624	0	0	2
T10	81578	139	0	2
T11	12470	0	0	2
T13	0	35	0	0
T14	0	19	0	0
T15	0	1	0	0
T16	0	37	0	0
T17	0	15	0	0
T18	0	188	0	0
T19	0	33	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2973096	2968944	0	0
T2	2684472	2682048	0	0
T3	8510760	8510616	0	0
T4	11278272	11277144	0	0
T5	1121688	1117560	0	0
T7	16781280	16736160	0	0
T8	10947888	10947144	0	0
T9	43488	42816	0	0
T10	978936	943320	0	0
T11	149640	138528	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151307	0	0
T1	2973096	59895	0	0
T2	2684472	59801	0	0
T3	8510760	8921	0	0
T4	11278272	419	0	0
T5	1121688	27649	0	0
T7	16781280	61271	0	0
T8	10947888	525	0	0
T9	43488	426	0	0
T10	978936	19479	0	0
T11	149640	596	0	0
T12	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	916572	0	0
GntImpliesValid_A	420496456	916572	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	916572	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	12497737	0	0
ReadyAndValidImplyGrant_A	420496456	916572	0	0
ReqAndReadyImplyGrant_A	420496456	916572	0	0
ReqImpliesValid_A	420496456	2589341	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	916572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	12497737	0	0
T1	123879	4641	0	0
T2	111853	4288	0	0
T3	354615	3269	0	0
T4	469928	16030	0	0
T5	46737	1821	0	0
T7	699220	41474	0	0
T8	456162	22531	0	0
T9	1812	39	0	0
T10	40789	1600	0	0
T11	6235	367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	2589341	0	0
T1	123879	10450	0	0
T2	111853	7790	0	0
T3	354615	1197	0	0
T4	469928	1690	0	0
T5	46737	4165	0	0
T7	699220	8928	0	0
T8	456162	2032	0	0
T9	1812	70	0	0
T10	40789	3014	0	0
T11	6235	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	916572	0	0
T1	123879	7544	0	0
T2	111853	6038	0	0
T3	354615	804	0	0
T4	469928	49	0	0
T5	46737	2992	0	0
T7	699220	5850	0	0
T8	456162	60	0	0
T9	1812	54	0	0
T10	40789	2301	0	0
T11	6235	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	900039	0	0
GntImpliesValid_A	420496456	900039	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	900039	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	12563196	0	0
ReadyAndValidImplyGrant_A	420496456	900039	0	0
ReqAndReadyImplyGrant_A	420496456	900039	0	0
ReqImpliesValid_A	420496456	2550749	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	900039	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	12563196	0	0
T1	123879	4073	0	0
T2	111853	4223	0	0
T3	354615	3045	0	0
T4	469928	15215	0	0
T5	46737	1812	0	0
T7	699220	47759	0	0
T8	456162	18585	0	0
T9	1812	46	0	0
T10	40789	1675	0	0
T11	6235	400	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	2550749	0	0
T1	123879	6308	0	0
T2	111853	9229	0	0
T3	354615	1028	0	0
T4	469928	2002	0	0
T5	46737	2804	0	0
T7	699220	13527	0	0
T8	456162	1683	0	0
T9	1812	63	0	0
T10	40789	2548	0	0
T11	6235	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	900039	0	0
T1	123879	5189	0	0
T2	111853	6725	0	0
T3	354615	736	0	0
T4	469928	41	0	0
T5	46737	2307	0	0
T7	699220	6740	0	0
T8	456162	63	0	0
T9	1812	54	0	0
T10	40789	2105	0	0
T11	6235	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	231622	0	0
GntImpliesValid_A	420496456	231622	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	231622	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3138832	0	0
ReadyAndValidImplyGrant_A	420496456	231622	0	0
ReqAndReadyImplyGrant_A	420496456	231622	0	0
ReqImpliesValid_A	420496456	673826	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	231622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3138832	0	0
T1	123879	1566	0	0
T2	111853	899	0	0
T3	354615	1	0	0
T4	469928	4713	0	0
T5	46737	294	0	0
T7	699220	5963	0	0
T8	456162	2870	0	0
T9	1812	6	0	0
T10	40789	718	0	0
T11	6235	137	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	673826	0	0
T1	123879	2545	0	0
T2	111853	2249	0	0
T3	354615	0	0	0
T4	469928	181	0	0
T5	46737	312	0	0
T7	699220	944	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	834	0	0
T11	6235	22	0	0
T12	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231622	0	0
T1	123879	2054	0	0
T2	111853	1573	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	302	0	0
T7	699220	779	0	0
T8	456162	9	0	0
T9	1812	5	0	0
T10	40789	770	0	0
T11	6235	20	0	0
T12	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	230183	0	0
GntImpliesValid_A	420496456	230183	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	230183	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3076467	0	0
ReadyAndValidImplyGrant_A	420496456	230183	0	0
ReqAndReadyImplyGrant_A	420496456	230183	0	0
ReqImpliesValid_A	420496456	640165	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	230183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3076467	0	0
T1	123879	1590	0	0
T2	111853	610	0	0
T3	354615	1540	0	0
T4	469928	4285	0	0
T5	46737	536	0	0
T7	699220	7534	0	0
T8	456162	5423	0	0
T9	1812	8	0	0
T10	40789	444	0	0
T11	6235	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	640165	0	0
T1	123879	3603	0	0
T2	111853	1740	0	0
T3	354615	1129	0	0
T4	469928	13	0	0
T5	46737	1058	0	0
T7	699220	8662	0	0
T8	456162	154	0	0
T9	1812	9	0	0
T10	40789	1302	0	0
T11	6235	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230183	0	0
T1	123879	2595	0	0
T2	111853	1174	0	0
T3	354615	477	0	0
T4	469928	13	0	0
T5	46737	796	0	0
T7	699220	1617	0	0
T8	456162	15	0	0
T9	1812	8	0	0
T10	40789	867	0	0
T11	6235	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	224746	0	0
GntImpliesValid_A	420496456	224746	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	224746	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	5079310	0	0
ReadyAndValidImplyGrant_A	420496456	224746	0	0
ReqAndReadyImplyGrant_A	420496456	224746	0	0
ReqImpliesValid_A	420496456	1166717	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	224746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	5079310	0	0
T1	123879	6561	0	0
T2	111853	2970	0	0
T3	354615	0	0	0
T4	469928	4095	0	0
T5	46737	1946	0	0
T7	699220	19488	0	0
T8	456162	1752	0	0
T9	1812	30	0	0
T10	40789	3089	0	0
T11	6235	133	0	0
T12	0	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	1166717	0	0
T1	123879	7985	0	0
T2	111853	6406	0	0
T3	354615	0	0	0
T4	469928	396	0	0
T5	46737	3794	0	0
T7	699220	6864	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	2136	0	0
T11	6235	19	0	0
T12	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224746	0	0
T1	123879	2115	0	0
T2	111853	1543	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	799	0	0
T7	699220	2271	0	0
T8	456162	18	0	0
T9	1812	6	0	0
T10	40789	714	0	0
T11	6235	14	0	0
T12	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	210002	0	0
GntImpliesValid_A	420496456	210002	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	210002	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	5613400	0	0
ReadyAndValidImplyGrant_A	420496456	210002	0	0
ReqAndReadyImplyGrant_A	420496456	210002	0	0
ReqImpliesValid_A	420496456	1168638	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	210002	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	5613400	0	0
T1	123879	18030	0	0
T2	111853	3170	0	0
T3	354615	0	0	0
T4	469928	21103	0	0
T5	46737	1667	0	0
T7	699220	42868	0	0
T8	456162	2165	0	0
T9	1812	38	0	0
T10	40789	2914	0	0
T11	6235	106	0	0
T12	0	218	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	1168638	0	0
T1	123879	2359	0	0
T2	111853	9587	0	0
T3	354615	0	0	0
T4	469928	3051	0	0
T5	46737	3469	0	0
T7	699220	2766	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	714	0	0
T11	6235	10	0	0
T12	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	210002	0	0
T1	123879	630	0	0
T2	111853	2110	0	0
T3	354615	0	0	0
T4	469928	10	0	0
T5	46737	756	0	0
T7	699220	763	0	0
T8	456162	13	0	0
T9	1812	8	0	0
T10	40789	413	0	0
T11	6235	10	0	0
T12	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	219619	0	0
GntImpliesValid_A	420496456	219619	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	219619	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	5086989	0	0
ReadyAndValidImplyGrant_A	420496456	219619	0	0
ReqAndReadyImplyGrant_A	420496456	219619	0	0
ReqImpliesValid_A	420496456	1244635	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	219619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	5086989	0	0
T1	123879	7149	0	0
T2	111853	3892	0	0
T3	354615	0	0	0
T4	469928	10324	0	0
T5	46737	1817	0	0
T7	699220	43288	0	0
T8	456162	1834	0	0
T9	1812	61	0	0
T10	40789	1945	0	0
T11	6235	649	0	0
T12	0	335	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	1244635	0	0
T1	123879	6284	0	0
T2	111853	784	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	403	0	0
T7	699220	16467	0	0
T8	456162	11	0	0
T9	1812	24	0	0
T10	40789	508	0	0
T11	6235	200	0	0
T12	0	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	219619	0	0
T1	123879	1657	0	0
T2	111853	620	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	320	0	0
T7	699220	2045	0	0
T8	456162	11	0	0
T9	1812	13	0	0
T10	40789	392	0	0
T11	6235	17	0	0
T12	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	227888	0	0
GntImpliesValid_A	420496456	227888	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	227888	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	4708891	0	0
ReadyAndValidImplyGrant_A	420496456	227888	0	0
ReqAndReadyImplyGrant_A	420496456	227888	0	0
ReqImpliesValid_A	420496456	1420428	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	227888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	4708891	0	0
T1	123879	5885	0	0
T2	111853	3134	0	0
T3	354615	5982	0	0
T4	469928	3321	0	0
T5	46737	1946	0	0
T7	699220	23906	0	0
T8	456162	4579	0	0
T9	1812	51	0	0
T10	40789	4453	0	0
T11	6235	137	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	1420428	0	0
T1	123879	5616	0	0
T2	111853	7043	0	0
T3	354615	3115	0	0
T4	469928	787	0	0
T5	46737	420	0	0
T7	699220	1859	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	898	0	0
T11	6235	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227888	0	0
T1	123879	1646	0	0
T2	111853	1510	0	0
T3	354615	460	0	0
T4	469928	9	0	0
T5	46737	308	0	0
T7	699220	786	0	0
T8	456162	11	0	0
T9	1812	12	0	0
T10	40789	417	0	0
T11	6235	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	224241	0	0
GntImpliesValid_A	420496456	224241	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	224241	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3077773	0	0
ReadyAndValidImplyGrant_A	420496456	224241	0	0
ReqAndReadyImplyGrant_A	420496456	224241	0	0
ReqImpliesValid_A	420496456	628184	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	224241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3077773	0	0
T1	123879	938	0	0
T2	111853	1102	0	0
T3	354615	3280	0	0
T4	469928	5139	0	0
T5	46737	643	0	0
T7	699220	12455	0	0
T8	456162	6655	0	0
T9	1812	7	0	0
T10	40789	384	0	0
T11	6235	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	628184	0	0
T1	123879	1349	0	0
T2	111853	2876	0	0
T3	354615	2452	0	0
T4	469928	28	0	0
T5	46737	967	0	0
T7	699220	8930	0	0
T8	456162	773	0	0
T9	1812	6	0	0
T10	40789	389	0	0
T11	6235	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224241	0	0
T1	123879	1142	0	0
T2	111853	1988	0	0
T3	354615	996	0	0
T4	469928	18	0	0
T5	46737	804	0	0
T7	699220	2160	0	0
T8	456162	22	0	0
T9	1812	6	0	0
T10	40789	380	0	0
T11	6235	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	231494	0	0
GntImpliesValid_A	420496456	231494	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	231494	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3152092	0	0
ReadyAndValidImplyGrant_A	420496456	231494	0	0
ReqAndReadyImplyGrant_A	420496456	231494	0	0
ReqImpliesValid_A	420496456	648314	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	231494	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3152092	0	0
T1	123879	1738	0	0
T2	111853	1235	0	0
T3	354615	1600	0	0
T4	469928	5469	0	0
T5	46737	737	0	0
T7	699220	10476	0	0
T8	456162	3698	0	0
T9	1812	10	0	0
T10	40789	373	0	0
T11	6235	133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	648314	0	0
T1	123879	3843	0	0
T2	111853	3053	0	0
T3	354615	1126	0	0
T4	469928	499	0	0
T5	46737	1757	0	0
T7	699220	12464	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	398	0	0
T11	6235	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	231494	0	0
T1	123879	2789	0	0
T2	111853	2143	0	0
T3	354615	496	0	0
T4	469928	16	0	0
T5	46737	1246	0	0
T7	699220	2265	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	224228	0	0
GntImpliesValid_A	420496456	224228	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	224228	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3075652	0	0
ReadyAndValidImplyGrant_A	420496456	224228	0	0
ReqAndReadyImplyGrant_A	420496456	224228	0	0
ReqImpliesValid_A	420496456	612679	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	224228	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3075652	0	0
T1	123879	1380	0	0
T2	111853	586	0	0
T3	354615	1	0	0
T4	469928	4777	0	0
T5	46737	302	0	0
T7	699220	6734	0	0
T8	456162	6256	0	0
T9	1812	10	0	0
T10	40789	418	0	0
T11	6235	122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	612679	0	0
T1	123879	2883	0	0
T2	111853	3700	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	312	0	0
T7	699220	5679	0	0
T8	456162	1031	0	0
T9	1812	9	0	0
T10	40789	439	0	0
T11	6235	17	0	0
T12	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	224228	0	0
T1	123879	2130	0	0
T2	111853	2142	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	306	0	0
T7	699220	1305	0	0
T8	456162	17	0	0
T9	1812	9	0	0
T10	40789	422	0	0
T11	6235	17	0	0
T12	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	236452	0	0
GntImpliesValid_A	420496456	236452	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	236452	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3128080	0	0
ReadyAndValidImplyGrant_A	420496456	236452	0	0
ReqAndReadyImplyGrant_A	420496456	236452	0	0
ReqImpliesValid_A	420496456	620711	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	236452	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3128080	0	0
T1	123879	1318	0	0
T2	111853	613	0	0
T3	354615	1	0	0
T4	469928	2446	0	0
T5	46737	307	0	0
T7	699220	6587	0	0
T8	456162	5342	0	0
T9	1812	11	0	0
T10	40789	407	0	0
T11	6235	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	620711	0	0
T1	123879	2145	0	0
T2	111853	1485	0	0
T3	354615	0	0	0
T4	469928	170	0	0
T5	46737	313	0	0
T7	699220	2920	0	0
T8	456162	799	0	0
T9	1812	10	0	0
T10	40789	414	0	0
T11	6235	16	0	0
T12	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	236452	0	0
T1	123879	1730	0	0
T2	111853	1048	0	0
T3	354615	0	0	0
T4	469928	8	0	0
T5	46737	309	0	0
T7	699220	1207	0	0
T8	456162	18	0	0
T9	1812	10	0	0
T10	40789	404	0	0
T11	6235	16	0	0
T12	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	213964	0	0
GntImpliesValid_A	420496456	213964	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	213964	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3026778	0	0
ReadyAndValidImplyGrant_A	420496456	213964	0	0
ReqAndReadyImplyGrant_A	420496456	213964	0	0
ReqImpliesValid_A	420496456	528585	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	213964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3026778	0	0
T1	123879	617	0	0
T2	111853	842	0	0
T3	354615	3431	0	0
T4	469928	3895	0	0
T5	46737	488	0	0
T7	699220	9365	0	0
T8	456162	5886	0	0
T9	1812	11	0	0
T10	40789	393	0	0
T11	6235	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	528585	0	0
T1	123879	2710	0	0
T2	111853	1380	0	0
T3	354615	2458	0	0
T4	469928	11	0	0
T5	46737	1066	0	0
T7	699220	3142	0	0
T8	456162	153	0	0
T9	1812	10	0	0
T10	40789	412	0	0
T11	6235	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	213964	0	0
T1	123879	1662	0	0
T2	111853	1110	0	0
T3	354615	1048	0	0
T4	469928	11	0	0
T5	46737	776	0	0
T7	699220	1344	0	0
T8	456162	19	0	0
T9	1812	10	0	0
T10	40789	396	0	0
T11	6235	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	226331	0	0
GntImpliesValid_A	420496456	226331	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	226331	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3101606	0	0
ReadyAndValidImplyGrant_A	420496456	226331	0	0
ReqAndReadyImplyGrant_A	420496456	226331	0	0
ReqImpliesValid_A	420496456	702790	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	226331	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3101606	0	0
T1	123879	612	0	0
T2	111853	970	0	0
T3	354615	1399	0	0
T4	469928	2273	0	0
T5	46737	383	0	0
T7	699220	8056	0	0
T8	456162	4562	0	0
T9	1812	10	0	0
T10	40789	470	0	0
T11	6235	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	702790	0	0
T1	123879	1719	0	0
T2	111853	2388	0	0
T3	354615	1159	0	0
T4	469928	9	0	0
T5	46737	1223	0	0
T7	699220	5366	0	0
T8	456162	491	0	0
T9	1812	9	0	0
T10	40789	1325	0	0
T11	6235	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	226331	0	0
T1	123879	1164	0	0
T2	111853	1678	0	0
T3	354615	463	0	0
T4	469928	9	0	0
T5	46737	802	0	0
T7	699220	1821	0	0
T8	456162	19	0	0
T9	1812	9	0	0
T10	40789	891	0	0
T11	6235	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	222410	0	0
GntImpliesValid_A	420496456	222410	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	222410	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3127339	0	0
ReadyAndValidImplyGrant_A	420496456	222410	0	0
ReqAndReadyImplyGrant_A	420496456	222410	0	0
ReqImpliesValid_A	420496456	617133	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	222410	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3127339	0	0
T1	123879	597	0	0
T2	111853	614	0	0
T3	354615	1	0	0
T4	469928	4925	0	0
T5	46737	330	0	0
T7	699220	18228	0	0
T8	456162	4779	0	0
T9	1812	9	0	0
T10	40789	430	0	0
T11	6235	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	617133	0	0
T1	123879	618	0	0
T2	111853	2650	0	0
T3	354615	0	0	0
T4	469928	740	0	0
T5	46737	340	0	0
T7	699220	14380	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	449	0	0
T11	6235	14	0	0
T12	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	222410	0	0
T1	123879	606	0	0
T2	111853	1631	0	0
T3	354615	0	0	0
T4	469928	11	0	0
T5	46737	334	0	0
T7	699220	3294	0	0
T8	456162	16	0	0
T9	1812	8	0	0
T10	40789	433	0	0
T11	6235	7	0	0
T12	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	225961	0	0
GntImpliesValid_A	420496456	225961	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	225961	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3148351	0	0
ReadyAndValidImplyGrant_A	420496456	225961	0	0
ReqAndReadyImplyGrant_A	420496456	225961	0	0
ReqImpliesValid_A	420496456	618300	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	225961	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3148351	0	0
T1	123879	1022	0	0
T2	111853	903	0	0
T3	354615	1	0	0
T4	469928	3561	0	0
T5	46737	654	0	0
T7	699220	6999	0	0
T8	456162	3870	0	0
T9	1812	10	0	0
T10	40789	382	0	0
T11	6235	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	618300	0	0
T1	123879	3229	0	0
T2	111853	2259	0	0
T3	354615	0	0	0
T4	469928	404	0	0
T5	46737	970	0	0
T7	699220	2894	0	0
T8	456162	61	0	0
T9	1812	9	0	0
T10	40789	389	0	0
T11	6235	24	0	0
T12	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	225961	0	0
T1	123879	2124	0	0
T2	111853	1580	0	0
T3	354615	0	0	0
T4	469928	12	0	0
T5	46737	811	0	0
T7	699220	1246	0	0
T8	456162	16	0	0
T9	1812	9	0	0
T10	40789	379	0	0
T11	6235	15	0	0
T12	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	237620	0	0
GntImpliesValid_A	420496456	237620	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	237620	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3100757	0	0
ReadyAndValidImplyGrant_A	420496456	237620	0	0
ReqAndReadyImplyGrant_A	420496456	237620	0	0
ReqImpliesValid_A	420496456	612828	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	237620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3100757	0	0
T1	123879	800	0	0
T2	111853	1027	0	0
T3	354615	1	0	0
T4	469928	4744	0	0
T5	46737	457	0	0
T7	699220	12910	0	0
T8	456162	4251	0	0
T9	1812	13	0	0
T10	40789	439	0	0
T11	6235	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	612828	0	0
T1	123879	831	0	0
T2	111853	3307	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	479	0	0
T7	699220	10203	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	462	0	0
T11	6235	10	0	0
T12	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	237620	0	0
T1	123879	814	0	0
T2	111853	2166	0	0
T3	354615	0	0	0
T4	469928	13	0	0
T5	46737	467	0	0
T7	699220	2324	0	0
T8	456162	12	0	0
T9	1812	13	0	0
T10	40789	444	0	0
T11	6235	10	0	0
T12	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	233879	0	0
GntImpliesValid_A	420496456	233879	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	233879	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3126886	0	0
ReadyAndValidImplyGrant_A	420496456	233879	0	0
ReqAndReadyImplyGrant_A	420496456	233879	0	0
ReqImpliesValid_A	420496456	669224	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	233879	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3126886	0	0
T1	123879	1488	0	0
T2	111853	616	0	0
T3	354615	1515	0	0
T4	469928	3297	0	0
T5	46737	615	0	0
T7	699220	10398	0	0
T8	456162	6536	0	0
T9	1812	12	0	0
T10	40789	414	0	0
T11	6235	58	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	669224	0	0
T1	123879	3649	0	0
T2	111853	2510	0	0
T3	354615	1206	0	0
T4	469928	13	0	0
T5	46737	2031	0	0
T7	699220	16094	0	0
T8	456162	556	0	0
T9	1812	11	0	0
T10	40789	436	0	0
T11	6235	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	233879	0	0
T1	123879	2567	0	0
T2	111853	1562	0	0
T3	354615	498	0	0
T4	469928	13	0	0
T5	46737	1322	0	0
T7	699220	2496	0	0
T8	456162	23	0	0
T9	1812	11	0	0
T10	40789	419	0	0
T11	6235	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	216189	0	0
GntImpliesValid_A	420496456	216189	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	216189	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3103169	0	0
ReadyAndValidImplyGrant_A	420496456	216189	0	0
ReqAndReadyImplyGrant_A	420496456	216189	0	0
ReqImpliesValid_A	420496456	586646	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	216189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3103169	0	0
T1	123879	1744	0	0
T2	111853	1238	0	0
T3	354615	1453	0	0
T4	469928	3800	0	0
T5	46737	348	0	0
T7	699220	12657	0	0
T8	456162	4751	0	0
T9	1812	16	0	0
T10	40789	420	0	0
T11	6235	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	586646	0	0
T1	123879	2501	0	0
T2	111853	6270	0	0
T3	354615	1124	0	0
T4	469928	10	0	0
T5	46737	1416	0	0
T7	699220	14100	0	0
T8	456162	12	0	0
T9	1812	17	0	0
T10	40789	441	0	0
T11	6235	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	216189	0	0
T1	123879	2121	0	0
T2	111853	3753	0	0
T3	354615	472	0	0
T4	469928	10	0	0
T5	46737	881	0	0
T7	699220	2671	0	0
T8	456162	12	0	0
T9	1812	16	0	0
T10	40789	424	0	0
T11	6235	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	230566	0	0
GntImpliesValid_A	420496456	230566	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	230566	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3076099	0	0
ReadyAndValidImplyGrant_A	420496456	230566	0	0
ReqAndReadyImplyGrant_A	420496456	230566	0	0
ReqImpliesValid_A	420496456	624773	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	230566	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3076099	0	0
T1	123879	1633	0	0
T2	111853	1608	0	0
T3	354615	1	0	0
T4	469928	2663	0	0
T5	46737	740	0	0
T7	699220	7720	0	0
T8	456162	5057	0	0
T9	1812	15	0	0
T10	40789	394	0	0
T11	6235	148	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	624773	0	0
T1	123879	2462	0	0
T2	111853	3986	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	908	0	0
T7	699220	9635	0	0
T8	456162	689	0	0
T9	1812	14	0	0
T10	40789	407	0	0
T11	6235	28	0	0
T12	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	230566	0	0
T1	123879	2046	0	0
T2	111853	2796	0	0
T3	354615	0	0	0
T4	469928	9	0	0
T5	46737	823	0	0
T7	699220	1696	0	0
T8	456162	12	0	0
T9	1812	14	0	0
T10	40789	394	0	0
T11	6235	18	0	0
T12	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	220243	0	0
GntImpliesValid_A	420496456	220243	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	220243	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3168545	0	0
ReadyAndValidImplyGrant_A	420496456	220243	0	0
ReqAndReadyImplyGrant_A	420496456	220243	0	0
ReqImpliesValid_A	420496456	606201	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	220243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3168545	0	0
T1	123879	980	0	0
T2	111853	602	0	0
T3	354615	1	0	0
T4	469928	4734	0	0
T5	46737	777	0	0
T7	699220	10638	0	0
T8	456162	5611	0	0
T9	1812	16	0	0
T10	40789	922	0	0
T11	6235	694	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	606201	0	0
T1	123879	1153	0	0
T2	111853	1650	0	0
T3	354615	0	0	0
T4	469928	994	0	0
T5	46737	1981	0	0
T7	699220	9584	0	0
T8	456162	482	0	0
T9	1812	17	0	0
T10	40789	1101	0	0
T11	6235	182	0	0
T12	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	220243	0	0
T1	123879	1065	0	0
T2	111853	1125	0	0
T3	354615	0	0	0
T4	469928	15	0	0
T5	46737	1378	0	0
T7	699220	2039	0	0
T8	456162	18	0	0
T9	1812	16	0	0
T10	40789	1005	0	0
T11	6235	91	0	0
T12	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	227341	0	0
GntImpliesValid_A	420496456	227341	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	227341	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	3058058	0	0
ReadyAndValidImplyGrant_A	420496456	227341	0	0
ReqAndReadyImplyGrant_A	420496456	227341	0	0
ReqImpliesValid_A	420496456	627736	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	0	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	227341	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	3058058	0	0
T1	123879	1055	0	0
T2	111853	757	0	0
T3	354615	3159	0	0
T4	469928	2765	0	0
T5	46737	319	0	0
T7	699220	8300	0	0
T8	456162	3839	0	0
T9	1812	13	0	0
T10	40789	423	0	0
T11	6235	119	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	627736	0	0
T1	123879	2350	0	0
T2	111853	2531	0	0
T3	354615	2292	0	0
T4	469928	11	0	0
T5	46737	333	0	0
T7	699220	1976	0	0
T8	456162	35	0	0
T9	1812	14	0	0
T10	40789	437	0	0
T11	6235	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	227341	0	0
T1	123879	1701	0	0
T2	111853	1643	0	0
T3	354615	972	0	0
T4	469928	11	0	0
T5	46737	325	0	0
T7	699220	1275	0	0
T8	456162	10	0	0
T9	1812	13	0	0
T10	40789	424	0	0
T11	6235	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	926413	0	0
GntImpliesValid_A	420496456	926413	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	926413	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	11946320	0	0
ReadyAndValidImplyGrant_A	420496456	926413	0	0
ReqAndReadyImplyGrant_A	420496456	926413	0	0
ReqImpliesValid_A	420496456	2443928	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	21937	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	926413	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	11946320	0	0
T1	123879	3	0	0
T2	111853	2	0	0
T3	354615	2364	0	0
T4	469928	14988	0	0
T5	46737	2	0	0
T7	699220	39249	0	0
T8	456162	13722	0	0
T9	1812	1	0	0
T10	40789	13	0	0
T11	6235	464	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	2443928	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	893	0	0
T4	469928	1794	0	0
T5	46737	3809	0	0
T7	699220	8773	0	0
T8	456162	727	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	21937	0	900
T1	123879	271	0	1
T2	111853	373	0	1
T3	354615	0	0	1
T4	469928	0	0	1
T5	46737	376	0	1
T7	699220	0	0	1
T8	456162	0	0	1
T9	1812	0	0	1
T10	40789	118	0	1
T11	6235	0	0	1
T14	0	19	0	0
T15	0	1	0	0
T16	0	32	0	0
T17	0	8	0	0
T18	0	10	0	0
T19	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	926413	0	0
T1	123879	6783	0	0
T2	111853	6768	0	0
T3	354615	723	0	0
T4	469928	44	0	0
T5	46737	3809	0	0
T7	699220	5997	0	0
T8	456162	47	0	0
T9	1812	57	0	0
T10	40789	2756	0	0
T11	6235	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420496456	420367974	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420496456	893304	0	0
GntImpliesValid_A	420496456	893304	0	0
GrantKnown_A	420496456	420367974	0	0
IdxKnown_A	420496456	420367974	0	0
IndexIsCorrect_A	420496456	893304	0	0
LockArbDecision_A	420496456	0	0	0
NoReadyValidNoGrant_A	420496456	353384645	0	0
ReadyAndValidImplyGrant_A	420496456	893304	0	0
ReqAndReadyImplyGrant_A	420496456	893304	0	0
ReqImpliesValid_A	420496456	13798972	0	0
ReqStaysHighUntilGranted0_M	420496456	0	0	0
RoundRobin_A	420496456	24660	0	900
ValidKnown_A	420496456	420367974	0	0
gen_data_port_assertion.DataFlow_A	420496456	893304	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	353384645	0	0
T1	123879	1	0	0
T2	111853	1	0	0
T3	354615	295173	0	0
T4	469928	454897	0	0
T5	46737	1	0	0
T7	699220	579802	0	0
T8	456162	437977	0	0
T9	1812	1	0	0
T10	40789	1	0	0
T11	6235	4764	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	13798972	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	3476	0	0
T4	469928	14093	0	0
T5	46737	4676	0	0
T7	699220	61390	0	0
T8	456162	17314	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	553	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	24660	0	900
T1	123879	211	0	1
T2	111853	42	0	1
T3	354615	0	0	1
T4	469928	0	0	1
T5	46737	927	0	1
T7	699220	36	0	1
T8	456162	0	0	1
T9	1812	0	0	1
T10	40789	21	0	1
T11	6235	0	0	1
T13	0	35	0	0
T16	0	5	0	0
T17	0	7	0	0
T18	0	178	0	0
T19	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	420367974	0	0
T1	123879	123706	0	0
T2	111853	111752	0	0
T3	354615	354609	0	0
T4	469928	469881	0	0
T5	46737	46565	0	0
T7	699220	697340	0	0
T8	456162	456131	0	0
T9	1812	1784	0	0
T10	40789	39305	0	0
T11	6235	5772	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420496456	893304	0	0
T1	123879	6021	0	0
T2	111853	5375	0	0
T3	354615	776	0	0
T4	469928	51	0	0
T5	46737	4676	0	0
T7	699220	7280	0	0
T8	456162	48	0	0
T9	1812	56	0	0
T10	40789	1950	0	0
T11	6235	71	0	0