Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1503282 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238300 1 T1 329 T2 16 T3 374


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 591233 1 T1 711 T2 35 T3 979
values[0x0] 559297 1 T1 714 T2 33 T3 874
values[0x1] 591052 1 T1 733 T2 32 T3 951


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1160819 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 580763 1 T1 783 T2 39 T3 936


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27600 1 T1 35 T3 37 T7 28
valid_sources[0x01] 25720 1 T1 38 T3 13 T7 30
valid_sources[0x02] 26431 1 T1 36 T3 5 T7 11
valid_sources[0x03] 26634 1 T1 30 T2 5 T3 15
valid_sources[0x04] 28417 1 T1 25 T3 128 T7 19
valid_sources[0x05] 27490 1 T1 37 T7 7 T8 31
valid_sources[0x06] 27105 1 T1 32 T3 38 T7 20
valid_sources[0x07] 27705 1 T1 35 T3 15 T7 29
valid_sources[0x08] 27344 1 T1 31 T3 19 T7 39
valid_sources[0x09] 27884 1 T1 34 T3 51 T7 45
valid_sources[0x0a] 26411 1 T1 34 T3 41 T7 29
valid_sources[0x0b] 27295 1 T1 23 T3 81 T7 19
valid_sources[0x0c] 26651 1 T1 41 T3 45 T7 14
valid_sources[0x0d] 27426 1 T1 39 T3 55 T7 10
valid_sources[0x0e] 27650 1 T1 28 T3 32 T7 3
valid_sources[0x0f] 27280 1 T1 39 T3 78 T7 1
valid_sources[0x10] 27222 1 T1 23 T3 43 T7 21
valid_sources[0x11] 27083 1 T1 46 T3 51 T7 16
valid_sources[0x12] 27557 1 T1 38 T3 97 T7 5
valid_sources[0x13] 26790 1 T1 44 T3 115 T7 11
valid_sources[0x14] 26960 1 T1 33 T3 17 T7 27
valid_sources[0x15] 27512 1 T1 34 T3 14 T7 20
valid_sources[0x16] 26722 1 T1 35 T3 36 T7 21
valid_sources[0x17] 27252 1 T1 32 T3 90 T7 27
valid_sources[0x18] 27115 1 T1 30 T3 24 T7 9
valid_sources[0x19] 26278 1 T1 25 T3 45 T7 21
valid_sources[0x1a] 26833 1 T1 43 T3 130 T7 33
valid_sources[0x1b] 27438 1 T1 31 T3 70 T7 29
valid_sources[0x1c] 27216 1 T1 33 T3 31 T7 12
valid_sources[0x1d] 26850 1 T1 27 T3 35 T7 5
valid_sources[0x1e] 28164 1 T1 33 T3 103 T7 33
valid_sources[0x1f] 27457 1 T1 23 T3 55 T7 20
valid_sources[0x20] 26725 1 T1 27 T3 61 T7 9


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24911 1 T1 30 T2 2 T3 34
values[0x0] all_enables biggest_size 188322 1 T1 268 T2 12 T3 300
values[0x1] all_enables biggest_size 25067 1 T1 31 T2 2 T3 40


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1516250 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246625 1 T1 257 T2 19 T3 431


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 603392 1 T1 675 T2 33 T3 933
values[0x0] 556360 1 T1 612 T2 42 T3 976
values[0x1] 603123 1 T1 664 T2 34 T3 976


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1164179 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 598696 1 T1 651 T2 36 T3 1017


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28432 1 T1 67 T2 1 T3 43
valid_sources[0x01] 27569 1 T1 14 T2 1 T3 33
valid_sources[0x02] 27044 1 T1 20 T3 43 T7 37
valid_sources[0x03] 27838 1 T1 26 T2 3 T3 93
valid_sources[0x04] 28045 1 T1 44 T3 39 T7 37
valid_sources[0x05] 28291 1 T1 59 T3 52 T7 24
valid_sources[0x06] 27479 1 T1 30 T2 2 T3 49
valid_sources[0x07] 27461 1 T1 22 T2 3 T3 59
valid_sources[0x08] 27576 1 T1 8 T2 4 T3 45
valid_sources[0x09] 27904 1 T1 15 T2 5 T3 46
valid_sources[0x0a] 27611 1 T1 63 T3 27 T7 12
valid_sources[0x0b] 26693 1 T1 26 T2 4 T3 52
valid_sources[0x0c] 27323 1 T1 5 T2 2 T3 31
valid_sources[0x0d] 27654 1 T1 23 T2 2 T3 32
valid_sources[0x0e] 28426 1 T1 21 T2 2 T3 45
valid_sources[0x0f] 27694 1 T1 42 T2 2 T3 26
valid_sources[0x10] 27432 1 T1 28 T2 5 T3 52
valid_sources[0x11] 28023 1 T1 27 T2 1 T3 45
valid_sources[0x12] 26781 1 T1 6 T2 1 T3 44
valid_sources[0x13] 27216 1 T1 22 T2 6 T3 42
valid_sources[0x14] 27502 1 T1 71 T2 7 T3 53
valid_sources[0x15] 27087 1 T1 47 T2 5 T3 38
valid_sources[0x16] 26915 1 T1 41 T2 2 T3 61
valid_sources[0x17] 28516 1 T1 36 T3 43 T7 14
valid_sources[0x18] 28619 1 T1 26 T2 1 T3 53
valid_sources[0x19] 27713 1 T1 34 T2 3 T3 58
valid_sources[0x1a] 27170 1 T1 39 T2 5 T3 27
valid_sources[0x1b] 26978 1 T1 23 T2 1 T3 55
valid_sources[0x1c] 27183 1 T1 13 T2 1 T3 50
valid_sources[0x1d] 26707 1 T1 29 T3 28 T7 13
valid_sources[0x1e] 27786 1 T1 33 T3 46 T7 8
valid_sources[0x1f] 27802 1 T1 33 T3 49 T7 9
valid_sources[0x20] 27213 1 T1 42 T3 31 T7 10


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25835 1 T1 21 T2 1 T3 36
values[0x0] all_enables biggest_size 195113 1 T1 217 T2 17 T3 357
values[0x1] all_enables biggest_size 25677 1 T1 19 T2 1 T3 38


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1508668 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 239996 1 T1 266 T2 29 T3 367


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 593762 1 T1 612 T2 70 T3 963
values[0x0] 561770 1 T1 641 T2 63 T3 876
values[0x1] 593132 1 T1 632 T2 56 T3 888


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1166703 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 581961 1 T1 605 T2 69 T3 918


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26583 1 T1 38 T2 3 T3 54
valid_sources[0x01] 26189 1 T1 21 T3 41 T7 20
valid_sources[0x02] 26967 1 T1 25 T2 6 T3 42
valid_sources[0x03] 27731 1 T1 24 T2 2 T3 42
valid_sources[0x04] 27151 1 T1 37 T2 3 T3 40
valid_sources[0x05] 27646 1 T1 29 T2 3 T3 44
valid_sources[0x06] 26785 1 T1 24 T2 3 T3 36
valid_sources[0x07] 26530 1 T1 27 T2 2 T3 39
valid_sources[0x08] 26967 1 T1 30 T2 3 T3 46
valid_sources[0x09] 26989 1 T1 30 T2 3 T3 42
valid_sources[0x0a] 27084 1 T1 25 T2 1 T3 41
valid_sources[0x0b] 27406 1 T1 26 T2 4 T3 38
valid_sources[0x0c] 27354 1 T1 33 T2 3 T3 38
valid_sources[0x0d] 28201 1 T1 24 T2 1 T3 44
valid_sources[0x0e] 28072 1 T1 27 T2 3 T3 48
valid_sources[0x0f] 27863 1 T1 29 T2 1 T3 45
valid_sources[0x10] 27651 1 T1 33 T2 2 T3 35
valid_sources[0x11] 27910 1 T1 25 T2 2 T3 40
valid_sources[0x12] 26692 1 T1 47 T2 4 T3 57
valid_sources[0x13] 26524 1 T1 18 T2 3 T3 49
valid_sources[0x14] 27558 1 T1 25 T2 6 T3 50
valid_sources[0x15] 26452 1 T1 26 T2 4 T3 36
valid_sources[0x16] 26607 1 T1 30 T2 1 T3 35
valid_sources[0x17] 27256 1 T1 25 T2 2 T3 39
valid_sources[0x18] 27253 1 T1 26 T3 31 T7 30
valid_sources[0x19] 26747 1 T1 31 T2 4 T3 51
valid_sources[0x1a] 27261 1 T1 27 T2 4 T3 33
valid_sources[0x1b] 27102 1 T1 25 T2 4 T3 33
valid_sources[0x1c] 27635 1 T1 28 T2 1 T3 49
valid_sources[0x1d] 27477 1 T1 26 T2 2 T3 36
valid_sources[0x1e] 27408 1 T1 30 T3 38 T7 14
valid_sources[0x1f] 27114 1 T1 33 T2 3 T3 42
valid_sources[0x20] 27489 1 T1 33 T2 2 T3 35


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25238 1 T1 21 T2 5 T3 35
values[0x0] all_enables biggest_size 189604 1 T1 224 T2 23 T3 295
values[0x1] all_enables biggest_size 25154 1 T1 21 T2 1 T3 37

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%