Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7689748	0	0
GntImpliesValid_A	2147483647	7689748	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7689748	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	427365662	0	0
ReadyAndValidImplyGrant_A	2147483647	7689748	0	0
ReqAndReadyImplyGrant_A	2147483647	7689748	0	0
ReqImpliesValid_A	2147483647	33523483	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	41153	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7689748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6283416	6283272	0	0
T2	11040696	11039688	0	0
T3	8700936	8700816	0	0
T7	3245376	3245280	0	0
T8	1116432	1074696	0	0
T9	45888	45576	0	0
T10	1221624	1218312	0	0
T11	980400	980184	0	0
T12	208176	207048	0	0
T13	11281536	11280024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6283416	6283272	0	0
T2	11040696	11039688	0	0
T3	8700936	8700816	0	0
T7	3245376	3245280	0	0
T8	1116432	1074696	0	0
T9	45888	45576	0	0
T10	1221624	1218312	0	0
T11	980400	980184	0	0
T12	208176	207048	0	0
T13	11281536	11280024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6283416	6283272	0	0
T2	11040696	11039688	0	0
T3	8700936	8700816	0	0
T7	3245376	3245280	0	0
T8	1116432	1074696	0	0
T9	45888	45576	0	0
T10	1221624	1218312	0	0
T11	980400	980184	0	0
T12	208176	207048	0	0
T13	11281536	11280024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	427365662	0	0
T1	6283416	1955838	0	0
T2	11040696	577574	0	0
T3	8700936	2942419	0	0
T7	3245376	134512	0	0
T8	1116432	69077	0	0
T9	45888	1207	0	0
T10	1221624	27067	0	0
T11	980400	51114	0	0
T12	208176	4433	0	0
T13	11281536	394437	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33523483	0	0
T1	6283416	331896	0	0
T2	11040696	27461	0	0
T3	8700936	547629	0	0
T7	3245376	7217	0	0
T8	1116432	11635	0	0
T9	45888	1397	0	0
T10	1221624	25105	0	0
T11	980400	5822	0	0
T12	208176	3977	0	0
T13	11281536	959	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41153	0	21600
T4	31974	27	0	2
T5	0	23	0	0
T8	93036	2	0	2
T9	3824	4	0	2
T10	101802	323	0	2
T11	81700	0	0	2
T12	17348	6	0	2
T13	940128	0	0	2
T14	1152818	6	0	2
T15	70086	4	0	2
T16	0	1	0	0
T17	0	48	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	4046	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6283416	6283272	0	0
T2	11040696	11039688	0	0
T3	8700936	8700816	0	0
T7	3245376	3245280	0	0
T8	1116432	1074696	0	0
T9	45888	45576	0	0
T10	1221624	1218312	0	0
T11	980400	980184	0	0
T12	208176	207048	0	0
T13	11281536	11280024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7689748	0	0
T1	6283416	5992	0	0
T2	11040696	397	0	0
T3	8700936	8412	0	0
T7	3245376	4106	0	0
T8	1116432	5002	0	0
T9	45888	1227	0	0
T10	1221624	15001	0	0
T11	980400	2735	0	0
T12	208176	3524	0	0
T13	11281536	471	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	853969	0	0
GntImpliesValid_A	391277102	853969	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	853969	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	11599602	0	0
ReadyAndValidImplyGrant_A	391277102	853969	0	0
ReqAndReadyImplyGrant_A	391277102	853969	0	0
ReqImpliesValid_A	391277102	2369281	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	853969	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	11599602	0	0
T1	261809	198303	0	0
T2	460029	17138	0	0
T3	362539	318001	0	0
T7	135224	1723	0	0
T8	46518	4287	0	0
T9	1912	116	0	0
T10	50901	1193	0	0
T11	40850	1911	0	0
T12	8674	299	0	0
T13	470064	196	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2369281	0	0
T1	261809	20124	0	0
T2	460029	1661	0	0
T3	362539	32435	0	0
T7	135224	560	0	0
T8	46518	1209	0	0
T9	1912	181	0	0
T10	50901	1445	0	0
T11	40850	355	0	0
T12	8674	418	0	0
T13	470064	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	853969	0	0
T1	261809	647	0	0
T2	460029	43	0	0
T3	362539	955	0	0
T7	135224	419	0	0
T8	46518	672	0	0
T9	1912	148	0	0
T10	50901	1318	0	0
T11	40850	251	0	0
T12	8674	358	0	0
T13	470064	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	861498	0	0
GntImpliesValid_A	391277102	861498	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	861498	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	11678014	0	0
ReadyAndValidImplyGrant_A	391277102	861498	0	0
ReqAndReadyImplyGrant_A	391277102	861498	0	0
ReqImpliesValid_A	391277102	2438760	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	861498	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	11678014	0	0
T1	261809	194675	0	0
T2	460029	13329	0	0
T3	362539	280511	0	0
T7	135224	2057	0	0
T8	46518	4347	0	0
T9	1912	110	0	0
T10	50901	1380	0	0
T11	40850	2092	0	0
T12	8674	339	0	0
T13	470064	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2438760	0	0
T1	261809	22470	0	0
T2	460029	204	0	0
T3	362539	29549	0	0
T7	135224	702	0	0
T8	46518	823	0	0
T9	1912	205	0	0
T10	50901	2732	0	0
T11	40850	430	0	0
T12	8674	476	0	0
T13	470064	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	861498	0	0
T1	261809	643	0	0
T2	460029	38	0	0
T3	362539	902	0	0
T7	135224	511	0	0
T8	46518	549	0	0
T9	1912	157	0	0
T10	50901	2055	0	0
T11	40850	288	0	0
T12	8674	407	0	0
T13	470064	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	199221	0	0
GntImpliesValid_A	391277102	199221	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	199221	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2782031	0	0
ReadyAndValidImplyGrant_A	391277102	199221	0	0
ReqAndReadyImplyGrant_A	391277102	199221	0	0
ReqImpliesValid_A	391277102	519611	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	199221	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2782031	0	0
T1	261809	57880	0	0
T2	460029	3491	0	0
T3	362539	60091	0	0
T7	135224	500	0	0
T8	46518	1821	0	0
T9	1912	30	0	0
T10	50901	294	0	0
T11	40850	604	0	0
T12	8674	102	0	0
T13	470064	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	519611	0	0
T1	261809	4251	0	0
T2	460029	16	0	0
T3	362539	2132	0	0
T7	135224	133	0	0
T8	46518	938	0	0
T9	1912	39	0	0
T10	50901	298	0	0
T11	40850	114	0	0
T12	8674	107	0	0
T13	470064	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	199221	0	0
T1	261809	191	0	0
T2	460029	16	0	0
T3	362539	191	0	0
T7	135224	119	0	0
T8	46518	298	0	0
T9	1912	34	0	0
T10	50901	295	0	0
T11	40850	77	0	0
T12	8674	104	0	0
T13	470064	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	207523	0	0
GntImpliesValid_A	391277102	207523	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	207523	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2836723	0	0
ReadyAndValidImplyGrant_A	391277102	207523	0	0
ReqAndReadyImplyGrant_A	391277102	207523	0	0
ReqImpliesValid_A	391277102	531618	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	207523	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2836723	0	0
T1	261809	44858	0	0
T2	460029	4852	0	0
T3	362539	71822	0	0
T7	135224	523	0	0
T8	46518	646	0	0
T9	1912	31	0	0
T10	50901	261	0	0
T11	40850	535	0	0
T12	8674	104	0	0
T13	470064	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	531618	0	0
T1	261809	2771	0	0
T2	460029	2164	0	0
T3	362539	6737	0	0
T7	135224	160	0	0
T8	46518	86	0	0
T9	1912	30	0	0
T10	50901	267	0	0
T11	40850	108	0	0
T12	8674	115	0	0
T13	470064	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207523	0	0
T1	261809	150	0	0
T2	460029	19	0	0
T3	362539	222	0	0
T7	135224	125	0	0
T8	46518	85	0	0
T9	1912	30	0	0
T10	50901	263	0	0
T11	40850	77	0	0
T12	8674	109	0	0
T13	470064	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	221524	0	0
GntImpliesValid_A	391277102	221524	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	221524	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	4714284	0	0
ReadyAndValidImplyGrant_A	391277102	221524	0	0
ReqAndReadyImplyGrant_A	391277102	221524	0	0
ReqImpliesValid_A	391277102	1363127	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	221524	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	4714284	0	0
T1	261809	68407	0	0
T2	460029	14159	0	0
T3	362539	92167	0	0
T7	135224	1129	0	0
T8	46518	1179	0	0
T9	1912	90	0	0
T10	50901	4087	0	0
T11	40850	580	0	0
T12	8674	529	0	0
T13	470064	101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	1363127	0	0
T1	261809	3548	0	0
T2	460029	1920	0	0
T3	362539	5842	0	0
T7	135224	157	0	0
T8	46518	161	0	0
T9	1912	36	0	0
T10	50901	2929	0	0
T11	40850	114	0	0
T12	8674	144	0	0
T13	470064	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221524	0	0
T1	261809	192	0	0
T2	460029	9	0	0
T3	362539	229	0	0
T7	135224	102	0	0
T8	46518	95	0	0
T9	1912	28	0	0
T10	50901	797	0	0
T11	40850	83	0	0
T12	8674	84	0	0
T13	470064	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	202590	0	0
GntImpliesValid_A	391277102	202590	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	202590	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	4931972	0	0
ReadyAndValidImplyGrant_A	391277102	202590	0	0
ReqAndReadyImplyGrant_A	391277102	202590	0	0
ReqImpliesValid_A	391277102	913723	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	202590	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	4931972	0	0
T1	261809	71839	0	0
T2	460029	2517	0	0
T3	362539	85573	0	0
T7	135224	3824	0	0
T8	46518	1305	0	0
T9	1912	196	0	0
T10	50901	3182	0	0
T11	40850	333	0	0
T12	8674	396	0	0
T13	470064	194	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	913723	0	0
T1	261809	5614	0	0
T2	460029	10	0	0
T3	362539	5698	0	0
T7	135224	324	0	0
T8	46518	146	0	0
T9	1912	53	0	0
T10	50901	392	0	0
T11	40850	83	0	0
T12	8674	138	0	0
T13	470064	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	202590	0	0
T1	261809	179	0	0
T2	460029	10	0	0
T3	362539	243	0	0
T7	135224	105	0	0
T8	46518	100	0	0
T9	1912	37	0	0
T10	50901	271	0	0
T11	40850	74	0	0
T12	8674	77	0	0
T13	470064	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	214899	0	0
GntImpliesValid_A	391277102	214899	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	214899	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	5083270	0	0
ReadyAndValidImplyGrant_A	391277102	214899	0	0
ReqAndReadyImplyGrant_A	391277102	214899	0	0
ReqImpliesValid_A	391277102	1228167	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	214899	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	5083270	0	0
T1	261809	49846	0	0
T2	460029	11977	0	0
T3	362539	223384	0	0
T7	135224	1032	0	0
T8	46518	1724	0	0
T9	1912	91	0	0
T10	50901	1843	0	0
T11	40850	332	0	0
T12	8674	567	0	0
T13	470064	928	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	1228167	0	0
T1	261809	3527	0	0
T2	460029	9	0	0
T3	362539	21562	0	0
T7	135224	186	0	0
T8	46518	140	0	0
T9	1912	30	0	0
T10	50901	318	0	0
T11	40850	81	0	0
T12	8674	122	0	0
T13	470064	153	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	214899	0	0
T1	261809	151	0	0
T2	460029	9	0	0
T3	362539	243	0	0
T7	135224	111	0	0
T8	46518	107	0	0
T9	1912	27	0	0
T10	50901	277	0	0
T11	40850	76	0	0
T12	8674	90	0	0
T13	470064	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	206904	0	0
GntImpliesValid_A	391277102	206904	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	206904	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	4367464	0	0
ReadyAndValidImplyGrant_A	391277102	206904	0	0
ReqAndReadyImplyGrant_A	391277102	206904	0	0
ReqImpliesValid_A	391277102	1081575	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	206904	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	4367464	0	0
T1	261809	44277	0	0
T2	460029	2305	0	0
T3	362539	110477	0	0
T7	135224	3085	0	0
T8	46518	887	0	0
T9	1912	88	0	0
T10	50901	10604	0	0
T11	40850	405	0	0
T12	8674	801	0	0
T13	470064	530	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	1081575	0	0
T1	261809	2683	0	0
T2	460029	260	0	0
T3	362539	8888	0	0
T7	135224	455	0	0
T8	46518	87	0	0
T9	1912	58	0	0
T10	50901	7332	0	0
T11	40850	99	0	0
T12	8674	216	0	0
T13	470064	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	206904	0	0
T1	261809	155	0	0
T2	460029	8	0	0
T3	362539	242	0	0
T7	135224	107	0	0
T8	46518	80	0	0
T9	1912	28	0	0
T10	50901	810	0	0
T11	40850	84	0	0
T12	8674	117	0	0
T13	470064	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	211454	0	0
GntImpliesValid_A	391277102	211454	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	211454	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2894489	0	0
ReadyAndValidImplyGrant_A	391277102	211454	0	0
ReqAndReadyImplyGrant_A	391277102	211454	0	0
ReqImpliesValid_A	391277102	543922	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	211454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2894489	0	0
T1	261809	55045	0	0
T2	460029	4109	0	0
T3	362539	80669	0	0
T7	135224	493	0	0
T8	46518	2422	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	459	0	0
T12	8674	87	0	0
T13	470064	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	543922	0	0
T1	261809	2673	0	0
T2	460029	115	0	0
T3	362539	3381	0	0
T7	135224	148	0	0
T8	46518	1158	0	0
T9	1912	44	0	0
T10	50901	252	0	0
T11	40850	91	0	0
T12	8674	94	0	0
T13	470064	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211454	0	0
T1	261809	175	0	0
T2	460029	10	0	0
T3	362539	265	0	0
T7	135224	111	0	0
T8	46518	486	0	0
T9	1912	43	0	0
T10	50901	250	0	0
T11	40850	67	0	0
T12	8674	90	0	0
T13	470064	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	207748	0	0
GntImpliesValid_A	391277102	207748	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	207748	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2801762	0	0
ReadyAndValidImplyGrant_A	391277102	207748	0	0
ReqAndReadyImplyGrant_A	391277102	207748	0	0
ReqImpliesValid_A	391277102	510921	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	207748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2801762	0	0
T1	261809	48511	0	0
T2	460029	5651	0	0
T3	362539	74421	0	0
T7	135224	447	0	0
T8	46518	720	0	0
T9	1912	23	0	0
T10	50901	297	0	0
T11	40850	659	0	0
T12	8674	95	0	0
T13	470064	82	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	510921	0	0
T1	261809	1603	0	0
T2	460029	15	0	0
T3	362539	5887	0	0
T7	135224	150	0	0
T8	46518	116	0	0
T9	1912	26	0	0
T10	50901	309	0	0
T11	40850	135	0	0
T12	8674	100	0	0
T13	470064	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207748	0	0
T1	261809	157	0	0
T2	460029	15	0	0
T3	362539	240	0	0
T7	135224	103	0	0
T8	46518	102	0	0
T9	1912	24	0	0
T10	50901	302	0	0
T11	40850	89	0	0
T12	8674	97	0	0
T13	470064	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	209951	0	0
GntImpliesValid_A	391277102	209951	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	209951	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2941291	0	0
ReadyAndValidImplyGrant_A	391277102	209951	0	0
ReqAndReadyImplyGrant_A	391277102	209951	0	0
ReqImpliesValid_A	391277102	552994	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	209951	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2941291	0	0
T1	261809	52787	0	0
T2	460029	3063	0	0
T3	362539	79652	0	0
T7	135224	370	0	0
T8	46518	715	0	0
T9	1912	27	0	0
T10	50901	484	0	0
T11	40850	528	0	0
T12	8674	78	0	0
T13	470064	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	552994	0	0
T1	261809	3198	0	0
T2	460029	1041	0	0
T3	362539	4582	0	0
T7	135224	109	0	0
T8	46518	88	0	0
T9	1912	30	0	0
T10	50901	958	0	0
T11	40850	92	0	0
T12	8674	87	0	0
T13	470064	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	209951	0	0
T1	261809	163	0	0
T2	460029	16	0	0
T3	362539	236	0	0
T7	135224	88	0	0
T8	46518	88	0	0
T9	1912	28	0	0
T10	50901	720	0	0
T11	40850	72	0	0
T12	8674	82	0	0
T13	470064	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	211751	0	0
GntImpliesValid_A	391277102	211751	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	211751	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2844978	0	0
ReadyAndValidImplyGrant_A	391277102	211751	0	0
ReqAndReadyImplyGrant_A	391277102	211751	0	0
ReqImpliesValid_A	391277102	573462	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	211751	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2844978	0	0
T1	261809	52898	0	0
T2	460029	4172	0	0
T3	362539	85626	0	0
T7	135224	402	0	0
T8	46518	868	0	0
T9	1912	41	0	0
T10	50901	259	0	0
T11	40850	620	0	0
T12	8674	92	0	0
T13	470064	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	573462	0	0
T1	261809	3648	0	0
T2	460029	10	0	0
T3	362539	5459	0	0
T7	135224	124	0	0
T8	46518	122	0	0
T9	1912	48	0	0
T10	50901	257	0	0
T11	40850	94	0	0
T12	8674	105	0	0
T13	470064	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	211751	0	0
T1	261809	176	0	0
T2	460029	10	0	0
T3	362539	259	0	0
T7	135224	105	0	0
T8	46518	105	0	0
T9	1912	44	0	0
T10	50901	257	0	0
T11	40850	90	0	0
T12	8674	98	0	0
T13	470064	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	216330	0	0
GntImpliesValid_A	391277102	216330	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	216330	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2852619	0	0
ReadyAndValidImplyGrant_A	391277102	216330	0	0
ReqAndReadyImplyGrant_A	391277102	216330	0	0
ReqImpliesValid_A	391277102	574634	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	216330	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2852619	0	0
T1	261809	65209	0	0
T2	460029	3157	0	0
T3	362539	77570	0	0
T7	135224	500	0	0
T8	46518	769	0	0
T9	1912	41	0	0
T10	50901	236	0	0
T11	40850	631	0	0
T12	8674	81	0	0
T13	470064	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	574634	0	0
T1	261809	3766	0	0
T2	460029	306	0	0
T3	362539	2426	0	0
T7	135224	150	0	0
T8	46518	98	0	0
T9	1912	44	0	0
T10	50901	238	0	0
T11	40850	117	0	0
T12	8674	90	0	0
T13	470064	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216330	0	0
T1	261809	192	0	0
T2	460029	10	0	0
T3	362539	227	0	0
T7	135224	117	0	0
T8	46518	94	0	0
T9	1912	42	0	0
T10	50901	236	0	0
T11	40850	81	0	0
T12	8674	85	0	0
T13	470064	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	213949	0	0
GntImpliesValid_A	391277102	213949	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	213949	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2871446	0	0
ReadyAndValidImplyGrant_A	391277102	213949	0	0
ReqAndReadyImplyGrant_A	391277102	213949	0	0
ReqImpliesValid_A	391277102	587600	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	213949	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2871446	0	0
T1	261809	48820	0	0
T2	460029	4816	0	0
T3	362539	78722	0	0
T7	135224	461	0	0
T8	46518	695	0	0
T9	1912	27	0	0
T10	50901	263	0	0
T11	40850	495	0	0
T12	8674	91	0	0
T13	470064	97	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	587600	0	0
T1	261809	3285	0	0
T2	460029	2239	0	0
T3	362539	6509	0	0
T7	135224	128	0	0
T8	46518	109	0	0
T9	1912	26	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	94	0	0
T13	470064	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213949	0	0
T1	261809	167	0	0
T2	460029	15	0	0
T3	362539	235	0	0
T7	135224	110	0	0
T8	46518	93	0	0
T9	1912	26	0	0
T10	50901	264	0	0
T11	40850	68	0	0
T12	8674	92	0	0
T13	470064	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	213345	0	0
GntImpliesValid_A	391277102	213345	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	213345	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2863186	0	0
ReadyAndValidImplyGrant_A	391277102	213345	0	0
ReqAndReadyImplyGrant_A	391277102	213345	0	0
ReqImpliesValid_A	391277102	611501	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	213345	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2863186	0	0
T1	261809	54444	0	0
T2	460029	3574	0	0
T3	362539	71852	0	0
T7	135224	466	0	0
T8	46518	1208	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	454	0	0
T12	8674	108	0	0
T13	470064	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	611501	0	0
T1	261809	977	0	0
T2	460029	238	0	0
T3	362539	2572	0	0
T7	135224	152	0	0
T8	46518	582	0	0
T9	1912	19	0	0
T10	50901	262	0	0
T11	40850	89	0	0
T12	8674	117	0	0
T13	470064	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	213345	0	0
T1	261809	164	0	0
T2	460029	11	0	0
T3	362539	211	0	0
T7	135224	120	0	0
T8	46518	194	0	0
T9	1912	18	0	0
T10	50901	260	0	0
T11	40850	63	0	0
T12	8674	112	0	0
T13	470064	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	216224	0	0
GntImpliesValid_A	391277102	216224	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	216224	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2869252	0	0
ReadyAndValidImplyGrant_A	391277102	216224	0	0
ReqAndReadyImplyGrant_A	391277102	216224	0	0
ReqImpliesValid_A	391277102	566573	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	216224	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2869252	0	0
T1	261809	57842	0	0
T2	460029	6393	0	0
T3	362539	71805	0	0
T7	135224	454	0	0
T8	46518	1133	0	0
T9	1912	40	0	0
T10	50901	274	0	0
T11	40850	593	0	0
T12	8674	92	0	0
T13	470064	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	566573	0	0
T1	261809	3769	0	0
T2	460029	335	0	0
T3	362539	6346	0	0
T7	135224	115	0	0
T8	46518	302	0	0
T9	1912	47	0	0
T10	50901	274	0	0
T11	40850	123	0	0
T12	8674	91	0	0
T13	470064	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	216224	0	0
T1	261809	162	0	0
T2	460029	19	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	167	0	0
T9	1912	43	0	0
T10	50901	273	0	0
T11	40850	80	0	0
T12	8674	91	0	0
T13	470064	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	231231	0	0
GntImpliesValid_A	391277102	231231	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	231231	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2917211	0	0
ReadyAndValidImplyGrant_A	391277102	231231	0	0
ReqAndReadyImplyGrant_A	391277102	231231	0	0
ReqImpliesValid_A	391277102	587286	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	231231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2917211	0	0
T1	261809	55331	0	0
T2	460029	1747	0	0
T3	362539	72188	0	0
T7	135224	461	0	0
T8	46518	1157	0	0
T9	1912	29	0	0
T10	50901	282	0	0
T11	40850	1095	0	0
T12	8674	139	0	0
T13	470064	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	587286	0	0
T1	261809	6021	0	0
T2	460029	321	0	0
T3	362539	3839	0	0
T7	135224	132	0	0
T8	46518	217	0	0
T9	1912	30	0	0
T10	50901	288	0	0
T11	40850	232	0	0
T12	8674	168	0	0
T13	470064	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	231231	0	0
T1	261809	167	0	0
T2	460029	7	0	0
T3	362539	213	0	0
T7	135224	105	0	0
T8	46518	164	0	0
T9	1912	29	0	0
T10	50901	284	0	0
T11	40850	152	0	0
T12	8674	153	0	0
T13	470064	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	217333	0	0
GntImpliesValid_A	391277102	217333	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	217333	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2890994	0	0
ReadyAndValidImplyGrant_A	391277102	217333	0	0
ReqAndReadyImplyGrant_A	391277102	217333	0	0
ReqImpliesValid_A	391277102	537480	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	217333	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2890994	0	0
T1	261809	50657	0	0
T2	460029	5264	0	0
T3	362539	65177	0	0
T7	135224	450	0	0
T8	46518	1228	0	0
T9	1912	34	0	0
T10	50901	262	0	0
T11	40850	507	0	0
T12	8674	87	0	0
T13	470064	86	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	537480	0	0
T1	261809	2023	0	0
T2	460029	44	0	0
T3	362539	5404	0	0
T7	135224	153	0	0
T8	46518	225	0	0
T9	1912	33	0	0
T10	50901	264	0	0
T11	40850	73	0	0
T12	8674	96	0	0
T13	470064	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	217333	0	0
T1	261809	166	0	0
T2	460029	13	0	0
T3	362539	210	0	0
T7	135224	122	0	0
T8	46518	166	0	0
T9	1912	33	0	0
T10	50901	262	0	0
T11	40850	70	0	0
T12	8674	91	0	0
T13	470064	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	207767	0	0
GntImpliesValid_A	391277102	207767	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	207767	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2883239	0	0
ReadyAndValidImplyGrant_A	391277102	207767	0	0
ReqAndReadyImplyGrant_A	391277102	207767	0	0
ReqImpliesValid_A	391277102	534064	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	207767	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2883239	0	0
T1	261809	60309	0	0
T2	460029	3277	0	0
T3	362539	73386	0	0
T7	135224	486	0	0
T8	46518	786	0	0
T9	1912	33	0	0
T10	50901	283	0	0
T11	40850	549	0	0
T12	8674	70	0	0
T13	470064	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	534064	0	0
T1	261809	1809	0	0
T2	460029	14	0	0
T3	362539	4190	0	0
T7	135224	122	0	0
T8	46518	117	0	0
T9	1912	32	0	0
T10	50901	285	0	0
T11	40850	110	0	0
T12	8674	75	0	0
T13	470064	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207767	0	0
T1	261809	186	0	0
T2	460029	14	0	0
T3	362539	236	0	0
T7	135224	107	0	0
T8	46518	93	0	0
T9	1912	32	0	0
T10	50901	283	0	0
T11	40850	76	0	0
T12	8674	72	0	0
T13	470064	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	207789	0	0
GntImpliesValid_A	391277102	207789	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	207789	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2858040	0	0
ReadyAndValidImplyGrant_A	391277102	207789	0	0
ReqAndReadyImplyGrant_A	391277102	207789	0	0
ReqImpliesValid_A	391277102	577178	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	207789	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2858040	0	0
T1	261809	60584	0	0
T2	460029	2576	0	0
T3	362539	78654	0	0
T7	135224	510	0	0
T8	46518	751	0	0
T9	1912	33	0	0
T10	50901	278	0	0
T11	40850	555	0	0
T12	8674	78	0	0
T13	470064	39	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	577178	0	0
T1	261809	1765	0	0
T2	460029	10	0	0
T3	362539	5265	0	0
T7	135224	150	0	0
T8	46518	107	0	0
T9	1912	40	0	0
T10	50901	280	0	0
T11	40850	89	0	0
T12	8674	79	0	0
T13	470064	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	207789	0	0
T1	261809	168	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	121	0	0
T8	46518	89	0	0
T9	1912	36	0	0
T10	50901	278	0	0
T11	40850	79	0	0
T12	8674	78	0	0
T13	470064	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	221141	0	0
GntImpliesValid_A	391277102	221141	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	221141	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2863851	0	0
ReadyAndValidImplyGrant_A	391277102	221141	0	0
ReqAndReadyImplyGrant_A	391277102	221141	0	0
ReqImpliesValid_A	391277102	618988	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	221141	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2863851	0	0
T1	261809	55336	0	0
T2	460029	3893	0	0
T3	362539	66549	0	0
T7	135224	428	0	0
T8	46518	689	0	0
T9	1912	30	0	0
T10	50901	266	0	0
T11	40850	512	0	0
T12	8674	115	0	0
T13	470064	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	618988	0	0
T1	261809	1834	0	0
T2	460029	10	0	0
T3	362539	5681	0	0
T7	135224	121	0	0
T8	46518	102	0	0
T9	1912	33	0	0
T10	50901	270	0	0
T11	40850	68	0	0
T12	8674	118	0	0
T13	470064	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	221141	0	0
T1	261809	158	0	0
T2	460029	10	0	0
T3	362539	220	0	0
T7	135224	107	0	0
T8	46518	95	0	0
T9	1912	31	0	0
T10	50901	267	0	0
T11	40850	68	0	0
T12	8674	116	0	0
T13	470064	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	219922	0	0
GntImpliesValid_A	391277102	219922	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	219922	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	2899805	0	0
ReadyAndValidImplyGrant_A	391277102	219922	0	0
ReqAndReadyImplyGrant_A	391277102	219922	0	0
ReqImpliesValid_A	391277102	622023	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	0	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	219922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2899805	0	0
T1	261809	53100	0	0
T2	460029	3939	0	0
T3	362539	78908	0	0
T7	135224	526	0	0
T8	46518	849	0	0
T9	1912	34	0	0
T10	50901	526	0	0
T11	40850	585	0	0
T12	8674	81	0	0
T13	470064	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	622023	0	0
T1	261809	2524	0	0
T2	460029	10	0	0
T3	362539	3352	0	0
T7	135224	137	0	0
T8	46518	111	0	0
T9	1912	41	0	0
T10	50901	942	0	0
T11	40850	145	0	0
T12	8674	92	0	0
T13	470064	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	219922	0	0
T1	261809	159	0	0
T2	460029	10	0	0
T3	362539	244	0	0
T7	135224	119	0	0
T8	46518	102	0	0
T9	1912	37	0	0
T10	50901	733	0	0
T11	40850	77	0	0
T12	8674	86	0	0
T13	470064	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	878497	0	0
GntImpliesValid_A	391277102	878497	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	878497	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	10816249	0	0
ReadyAndValidImplyGrant_A	391277102	878497	0	0
ReqAndReadyImplyGrant_A	391277102	878497	0	0
ReqImpliesValid_A	391277102	2350782	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	17622	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	878497	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	10816249	0	0
T1	261809	224590	0	0
T2	460029	8508	0	0
T3	362539	316234	0	0
T7	135224	1661	0	0
T8	46518	3133	0	0
T9	1912	1	0	0
T10	50901	2	0	0
T11	40850	2053	0	0
T12	8674	1	0	0
T13	470064	175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	2350782	0	0
T1	261809	27116	0	0
T2	460029	1086	0	0
T3	362539	40710	0	0
T7	135224	635	0	0
T8	46518	715	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	438	0	0
T12	8674	405	0	0
T13	470064	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	17622	0	900
T4	15987	9	0	1
T5	0	11	0	0
T8	46518	1	0	1
T9	1912	1	0	1
T10	50901	309	0	1
T11	40850	0	0	1
T12	8674	3	0	1
T13	470064	0	0	1
T14	576409	1	0	1
T15	35043	4	0	1
T16	0	1	0	0
T17	0	31	0	0
T20	2023	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	878497	0	0
T1	261809	691	0	0
T2	460029	32	0	0
T3	362539	970	0	0
T7	135224	499	0	0
T8	46518	496	0	0
T9	1912	148	0	0
T10	50901	2918	0	0
T11	40850	300	0	0
T12	8674	405	0	0
T13	470064	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391277102	391160957	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	391277102	837188	0	0
GntImpliesValid_A	391277102	837188	0	0
GrantKnown_A	391277102	391160957	0	0
IdxKnown_A	391277102	391160957	0	0
IndexIsCorrect_A	391277102	837188	0	0
LockArbDecision_A	391277102	0	0	0
NoReadyValidNoGrant_A	391277102	328303890	0	0
ReadyAndValidImplyGrant_A	391277102	837188	0	0
ReqAndReadyImplyGrant_A	391277102	837188	0	0
ReqImpliesValid_A	391277102	12728213	0	0
ReqStaysHighUntilGranted0_M	391277102	0	0	0
RoundRobin_A	391277102	23531	0	900
ValidKnown_A	391277102	391160957	0	0
gen_data_port_assertion.DataFlow_A	391277102	837188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	328303890	0	0
T1	261809	230290	0	0
T2	460029	443667	0	0
T3	362539	328980	0	0
T7	135224	112524	0	0
T8	46518	35758	0	0
T9	1912	1	0	0
T10	50901	1	0	0
T11	40850	34027	0	0
T12	8674	1	0	0
T13	470064	391105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	12728213	0	0
T1	261809	200897	0	0
T2	460029	15423	0	0
T3	362539	329183	0	0
T7	135224	2014	0	0
T8	46518	3876	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	2474	0	0
T12	8674	430	0	0
T13	470064	256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	23531	0	900
T4	15987	18	0	1
T5	0	12	0	0
T8	46518	1	0	1
T9	1912	3	0	1
T10	50901	14	0	1
T11	40850	0	0	1
T12	8674	3	0	1
T13	470064	0	0	1
T14	576409	5	0	1
T15	35043	0	0	1
T17	0	17	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	2023	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	391160957	0	0
T1	261809	261803	0	0
T2	460029	459987	0	0
T3	362539	362534	0	0
T7	135224	135220	0	0
T8	46518	44779	0	0
T9	1912	1899	0	0
T10	50901	50763	0	0
T11	40850	40841	0	0
T12	8674	8627	0	0
T13	470064	470001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391277102	837188	0	0
T1	261809	633	0	0
T2	460029	43	0	0
T3	362539	939	0	0
T7	135224	466	0	0
T8	46518	482	0	0
T9	1912	124	0	0
T10	50901	1328	0	0
T11	40850	293	0	0
T12	8674	430	0	0
T13	470064	54	0	0