Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1486268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236499

1

T1

18

T2

345

T3

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	584306	1			T1	40		T2	856		T3	270
values[0x0]	553441	1			T1	45		T2	844		T3	47
values[0x1]	585020	1			T1	61		T2	900		T3	237

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1149636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

573131

1

T1

47

T2

844

T3

213

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26806	1			T1	3		T2	49		T3	9
valid_sources[0x01]	26400	1			T2	38		T3	8		T4	113
valid_sources[0x02]	26563	1			T1	9		T2	32		T3	10
valid_sources[0x03]	27427	1			T1	1		T2	41		T3	10
valid_sources[0x04]	27230	1			T2	20		T3	10		T8	16
valid_sources[0x05]	26705	1			T1	4		T2	39		T3	11
valid_sources[0x06]	27705	1			T2	40		T3	7		T8	5
valid_sources[0x07]	26569	1			T2	39		T3	8		T9	1
valid_sources[0x08]	26084	1			T2	59		T3	2		T8	3
valid_sources[0x09]	26153	1			T2	56		T3	5		T8	2
valid_sources[0x0a]	27852	1			T1	1		T2	40		T3	13
valid_sources[0x0b]	27879	1			T1	2		T2	39		T3	9
valid_sources[0x0c]	26547	1			T2	38		T3	9		T8	13
valid_sources[0x0d]	26890	1			T1	1		T2	25		T3	5
valid_sources[0x0e]	27859	1			T2	41		T3	8		T8	18
valid_sources[0x0f]	27257	1			T1	3		T2	39		T3	2
valid_sources[0x10]	27184	1			T1	2		T2	48		T3	14
valid_sources[0x11]	27063	1			T2	49		T3	8		T7	1
valid_sources[0x12]	26467	1			T2	48		T3	16		T4	111
valid_sources[0x13]	26981	1			T1	3		T2	32		T3	15
valid_sources[0x14]	27754	1			T1	44		T2	26		T3	8
valid_sources[0x15]	27614	1			T2	40		T3	11		T9	2
valid_sources[0x16]	26441	1			T2	36		T3	4		T8	3
valid_sources[0x17]	27566	1			T1	1		T2	39		T3	6
valid_sources[0x18]	26386	1			T2	53		T3	10		T8	22
valid_sources[0x19]	28104	1			T2	41		T3	8		T4	158
valid_sources[0x1a]	27551	1			T1	2		T2	58		T3	8
valid_sources[0x1b]	26660	1			T1	6		T2	48		T3	8
valid_sources[0x1c]	26174	1			T2	35		T3	10		T7	1
valid_sources[0x1d]	26971	1			T1	11		T2	48		T3	7
valid_sources[0x1e]	26794	1			T1	1		T2	36		T3	7
valid_sources[0x1f]	26575	1			T1	1		T2	37		T3	12
valid_sources[0x20]	27839	1			T2	23		T3	6		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24977

1

T2

30

T3

25

T7

3

values[0x0]

all_enables

biggest_size

186750

1

T1

17

T2

276

T3

20

values[0x1]

all_enables

biggest_size

24772

1

T1

1

T2

39

T3

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1496755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243320

1

T1

29

T2

423

T3

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596449	1			T1	71		T2	947		T3	261
values[0x0]	548247	1			T1	73		T2	888		T3	55
values[0x1]	595379	1			T1	70		T2	914		T3	260

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1148826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591249

1

T1

65

T2

959

T3

204

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27019	1			T2	40		T3	10		T7	1
valid_sources[0x01]	27333	1			T2	43		T3	9		T8	8
valid_sources[0x02]	27370	1			T1	2		T2	45		T3	14
valid_sources[0x03]	27264	1			T1	7		T2	52		T3	15
valid_sources[0x04]	26892	1			T1	4		T2	40		T3	10
valid_sources[0x05]	27700	1			T2	32		T3	12		T8	5
valid_sources[0x06]	26788	1			T1	2		T2	47		T3	8
valid_sources[0x07]	27933	1			T1	3		T2	43		T3	8
valid_sources[0x08]	26215	1			T1	3		T2	47		T3	6
valid_sources[0x09]	27486	1			T1	3		T2	59		T3	11
valid_sources[0x0a]	27770	1			T1	3		T2	43		T3	12
valid_sources[0x0b]	27604	1			T1	3		T2	48		T3	11
valid_sources[0x0c]	26377	1			T1	2		T2	60		T3	4
valid_sources[0x0d]	26219	1			T2	57		T3	11		T9	6
valid_sources[0x0e]	26677	1			T1	4		T2	47		T3	9
valid_sources[0x0f]	27351	1			T1	2		T2	37		T3	8
valid_sources[0x10]	27424	1			T1	2		T2	26		T3	10
valid_sources[0x11]	27047	1			T1	1		T2	52		T3	9
valid_sources[0x12]	27343	1			T2	41		T3	5		T8	15
valid_sources[0x13]	27304	1			T1	3		T2	39		T3	11
valid_sources[0x14]	26806	1			T1	37		T2	28		T3	11
valid_sources[0x15]	27620	1			T1	3		T2	33		T3	9
valid_sources[0x16]	27281	1			T1	7		T2	38		T3	3
valid_sources[0x17]	26842	1			T1	1		T2	34		T3	7
valid_sources[0x18]	28034	1			T1	3		T2	59		T3	7
valid_sources[0x19]	27372	1			T1	5		T2	40		T3	7
valid_sources[0x1a]	27806	1			T1	5		T2	43		T3	10
valid_sources[0x1b]	26971	1			T1	7		T2	40		T3	9
valid_sources[0x1c]	27020	1			T1	4		T2	42		T3	15
valid_sources[0x1d]	27781	1			T2	40		T3	7		T9	5
valid_sources[0x1e]	27087	1			T1	4		T2	40		T3	9
valid_sources[0x1f]	28012	1			T1	3		T2	41		T3	8
valid_sources[0x20]	27441	1			T1	8		T2	39		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25697

1

T1

2

T2

42

T3

16

values[0x0]

all_enables

biggest_size

191830

1

T1

23

T2

339

T3

23

values[0x1]

all_enables

biggest_size

25793

1

T1

4

T2

42

T3

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1498918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238742

1

T1

36

T2

401

T3

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	590101	1			T1	89		T2	869		T3	244
values[0x0]	557956	1			T1	93		T2	883		T3	50
values[0x1]	589603	1			T1	102		T2	926		T3	278

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1158226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

579434

1

T1

99

T2

932

T3

217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26825	1			T1	1		T2	50		T3	6
valid_sources[0x01]	27046	1			T2	55		T3	7		T8	13
valid_sources[0x02]	27224	1			T1	2		T2	44		T3	11
valid_sources[0x03]	27767	1			T1	4		T2	39		T3	9
valid_sources[0x04]	27377	1			T1	6		T2	40		T3	11
valid_sources[0x05]	27462	1			T1	1		T2	51		T3	8
valid_sources[0x06]	27593	1			T2	50		T3	3		T8	20
valid_sources[0x07]	26947	1			T2	60		T3	9		T8	18
valid_sources[0x08]	26894	1			T1	2		T2	39		T3	6
valid_sources[0x09]	27551	1			T1	6		T2	46		T3	7
valid_sources[0x0a]	27877	1			T1	1		T2	44		T3	11
valid_sources[0x0b]	27053	1			T1	2		T2	42		T3	10
valid_sources[0x0c]	26508	1			T1	2		T2	46		T3	8
valid_sources[0x0d]	26603	1			T1	2		T2	46		T3	12
valid_sources[0x0e]	27191	1			T1	8		T2	33		T3	8
valid_sources[0x0f]	27184	1			T1	3		T2	35		T3	7
valid_sources[0x10]	27004	1			T2	50		T3	13		T7	1
valid_sources[0x11]	26725	1			T1	6		T2	40		T3	8
valid_sources[0x12]	27499	1			T1	4		T2	43		T3	5
valid_sources[0x13]	26432	1			T1	1		T2	54		T3	8
valid_sources[0x14]	26862	1			T1	46		T2	41		T3	7
valid_sources[0x15]	27525	1			T1	1		T2	48		T3	7
valid_sources[0x16]	27218	1			T1	4		T2	41		T3	2
valid_sources[0x17]	27264	1			T1	8		T2	40		T3	4
valid_sources[0x18]	27335	1			T1	8		T2	42		T3	13
valid_sources[0x19]	28159	1			T1	2		T2	38		T3	11
valid_sources[0x1a]	27621	1			T1	5		T2	26		T3	8
valid_sources[0x1b]	27061	1			T1	8		T2	34		T3	5
valid_sources[0x1c]	26380	1			T1	1		T2	38		T3	21
valid_sources[0x1d]	27047	1			T1	17		T2	41		T3	3
valid_sources[0x1e]	27425	1			T1	3		T2	33		T3	5
valid_sources[0x1f]	27242	1			T1	2		T2	43		T3	9
valid_sources[0x20]	27720	1			T1	5		T2	28		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25273

1

T2

36

T3

16

T7

1

values[0x0]

all_enables

biggest_size

188458

1

T1

32

T2

316

T3

22

values[0x1]

all_enables

biggest_size

25011

1

T1

4

T2

49

T3

19