Unified Coverage Report :: Group :: tl_agent_pkg::tl_d_chan_cov_cg

Group : tl_agent_pkg::tl_d_chan_cov_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

24 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131579

1

T1

1

T2

116

T3

615

auto[1]

74657

1

T1

3

T2

82

T3

656

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

51343

1

T1

1

T2

72

T3

148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60732

1

T2

63

T3

312

T7

8

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15741

1

T2

21

T3

40

T7

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140474

1

T1

9

T2

80

T3

435

auto[1]

79028

1

T2

133

T3

871

T7

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54693

1

T1

6

T2

65

T3

169

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65005

1

T1

2

T2

69

T3

331

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17029

1

T1

2

T2

27

T3

44

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141566

1

T1

5

T2

200

T3

359

auto[1]

73535

1

T1

1

T2

32

T3

414

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53881

1

T1

2

T2

72

T3

96

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63814

1

T1

4

T2

94

T3

188

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16696

1

T1

2

T2

32

T3

29

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138006

1

T1

2

T2

143

T3

761

auto[1]

79285

1

T1

2

T2

59

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54616

1

T1

2

T2

65

T3

96

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64427

1

T1

1

T2

69

T3

201

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16893

1

T2

21

T3

18

T7

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134229

1

T1

1

T2

146

T3

398

auto[1]

75640

1

T1

6

T2

62

T3

429

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52266

1

T2

66

T3

86

T7

5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148144	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

61725

1

T1

3

T2

68

T3

214

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16081

1

T2

21

T3

20

T7

2

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135246

1

T1

5

T2

75

T3

971

auto[1]

76473

1

T1

1

T2

131

T3

346

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53153

1

T1

4

T2

60

T3

174

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62562

1

T1

3

T2

69

T3

316

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16577

1

T1

1

T2

21

T3

47

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559960

1

T1

42

T2

450

T3

2311

auto[1]

305987

1

T1

10

T2

441

T3

1496

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

218092

1

T1

17

T2

308

T3

488

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	603907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

262040

1

T1

20

T2

293

T3

915

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

69086

1

T1

8

T2

84

T3

114

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141622

1

T1

4

T2

102

T3

401

auto[1]

72535

1

T1

3

T2

85

T3

403

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53358

1

T1

1

T2

62

T3

98

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63053

1

T1

2

T2

64

T3

205

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16552

1

T2

21

T3

23

T7

2

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141704

1

T1

3

T2

110

T3

404

auto[1]

81271

1

T1

1

T2

109

T3

432

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56517

1

T1

1

T2

67

T3

101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155369	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67606

1

T1

1

T2

79

T3

197

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17875

1

T2

22

T3

26

T7

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130699

1

T1

4

T2

159

T3

526

auto[1]

71538

1

T1

5

T2

54

T3

307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

49710

1

T1

5

T2

74

T3

99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59231

1

T1

1

T2

64

T3

203

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

15270

1

T2

26

T3

25

T8

5

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143748

1

T1

141

T2

126

T3

342

auto[1]

73703

1

T1

33

T2

107

T3

472

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54805

1

T1

45

T2

77

T3

112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66164

1

T1

60

T2

73

T3

222

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17486

1

T1

14

T2

24

T3

24

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141821

1

T2

68

T3

555

T7

18

auto[1]

78041

1

T1

2

T2

164

T3

223

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56072

1

T1

1

T2

81

T3

81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152683	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67179

1

T1

1

T2

75

T3

207

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17781

1

T2

30

T3

21

T7

3

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139695

1

T1

36

T2

142

T3

543

auto[1]

73646

1

T1

60

T2

87

T3

215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53867

1

T1

22

T2

74

T3

104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64845

1

T1

31

T2

74

T3

186

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17127

1

T1

4

T2

23

T3

33

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141006

1

T1

7

T2

176

T3

932

auto[1]

71434

1

T1

2

T2

13

T3

776

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53625

1

T1

2

T2

60

T3

211

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62598

1

T1

4

T2

55

T3

430

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16576

1

T2

23

T3

49

T7

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

582012

1

T1

59

T2

615

T3

3340

auto[1]

300190

1

T1

5

T2

364

T3

366

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

222749

1

T1

22

T2

340

T3

448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	615542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

266660

1

T1

17

T2

354

T3

935

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

70311

1

T1

5

T2

108

T3

106

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139793

1

T1

3

T2

165

T3

793

auto[1]

75937

1

T1

4

T2

40

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54253

1

T1

2

T2

67

T3

89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63838

1

T1

1

T2

80

T3

221

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16856

1

T2

24

T3

27

T8

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

552752

1

T1

28

T2

721

T3

1335

auto[1]

303288

1

T1

27

T2

188

T3

2494

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

217648

1

T1

21

T2

297

T3

457

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	596827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

259213

1

T1

16

T2

310

T3

935

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

68871

1

T1

8

T2

102

T3

124

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150190

1

T1

1

T2

155

T3

806

auto[1]

73124

1

T1

3

T2

52

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56044

1

T1

1

T2

65

T3

97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66536

1

T1

2

T2

71

T3

227

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17687

1

T2

18

T3

25

T7

2

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150727

1

T1

3

T2

95

T3

921

auto[1]

80391

1

T1

4

T2

147

T3

551

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

57777

1

T1

2

T2

90

T3

176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69894

1

T1

3

T2

76

T3

393

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18152

1

T2

29

T3

54

T7

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139739

1

T1

4

T2

190

T3

535

auto[1]

73037

1

T1

4

T2

33

T3

304

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53463

1

T1

2

T2

80

T3

112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63263

1

T1

3

T2

73

T3

207

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16759

1

T1

1

T2

25

T3

31

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137237

1

T1

6

T2

72

T3

1717

auto[1]

75561

1

T2

133

T7

11

T8

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52853

1

T1

3

T2

76

T3

206

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62932

1

T1

4

T2

67

T3

422

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16256

1

T1

1

T2

22

T3

46

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

552307

1

T1

18

T2

852

T3

2451

auto[1]

293927

1

T1

34

T2

46

T3

1377

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

212596

1

T1

14

T2

292

T3

509

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

256222

1

T1

15

T2

318

T3

933

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

67381

1

T1

3

T2

108

T3

116

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144323

1

T1

3

T2

201

T3

424

auto[1]

77164

1

T1

1

T2

25

T3

859

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54400

1

T1

1

T2

71

T3

163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65103

1

T2

70

T3

303

T7

4

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16810

1

T2

20

T3

48

T7

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139499

1

T1

2

T2

212

T3

810

auto[1]

75251

1

T1

1

T2

63

T3

411

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52578

1

T2

90

T3

127

T7

4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64081

1

T1

1

T2

103

T3

306

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16495

1

T2

37

T3

30

T7

2