Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7767171	0	0
GntImpliesValid_A	2147483647	7767171	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7767171	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	470702790	0	0
ReadyAndValidImplyGrant_A	2147483647	7767171	0	0
ReqAndReadyImplyGrant_A	2147483647	7767171	0	0
ReqImpliesValid_A	2147483647	34676556	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45017	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7767171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	144360	140736	0	0
T2	6185376	6185328	0	0
T3	9189648	9186888	0	0
T4	1103208	1099104	0	0
T7	421584	407544	0	0
T8	454536	453744	0	0
T9	9691440	9690864	0	0
T10	208056	207912	0	0
T11	37200	36840	0	0
T12	3037104	3036216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	144360	140736	0	0
T2	6185376	6185328	0	0
T3	9189648	9186888	0	0
T4	1103208	1099104	0	0
T7	421584	407544	0	0
T8	454536	453744	0	0
T9	9691440	9690864	0	0
T10	208056	207912	0	0
T11	37200	36840	0	0
T12	3037104	3036216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	144360	140736	0	0
T2	6185376	6185328	0	0
T3	9189648	9186888	0	0
T4	1103208	1099104	0	0
T7	421584	407544	0	0
T8	454536	453744	0	0
T9	9691440	9690864	0	0
T10	208056	207912	0	0
T11	37200	36840	0	0
T12	3037104	3036216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	470702790	0	0
T1	144360	8663	0	0
T2	6185376	243449	0	0
T3	9189648	569753	0	0
T4	1103208	34511	0	0
T7	421584	27044	0	0
T8	454536	30872	0	0
T9	9691440	506107	0	0
T10	208056	9902	0	0
T11	37200	407	0	0
T12	3037104	164934	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34676556	0	0
T1	144360	1616	0	0
T2	6185376	12968	0	0
T3	9189648	101435	0	0
T4	1103208	27258	0	0
T7	421584	4233	0	0
T8	454536	4727	0	0
T9	9691440	25826	0	0
T10	208056	800	0	0
T11	37200	429	0	0
T12	3037104	12285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45017	0	21600
T3	765804	6	0	2
T4	91934	95	0	2
T7	35132	3	0	2
T8	37878	0	0	2
T9	807620	0	0	2
T10	17338	0	0	2
T11	3100	0	0	2
T12	253092	0	0	2
T13	482712	16	0	2
T14	90132	1	0	2
T15	0	14	0	0
T16	0	1	0	0
T17	0	25	0	0
T18	0	16	0	0
T19	0	1	0	0
T20	0	24	0	0
T21	0	64	0	0
T22	0	23	0	0
T23	0	436	0	0
T24	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	144360	140736	0	0
T2	6185376	6185328	0	0
T3	9189648	9186888	0	0
T4	1103208	1099104	0	0
T7	421584	407544	0	0
T8	454536	453744	0	0
T9	9691440	9690864	0	0
T10	208056	207912	0	0
T11	37200	36840	0	0
T12	3037104	3036216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7767171	0	0
T1	144360	602	0	0
T2	6185376	8021	0	0
T3	9189648	36181	0	0
T4	1103208	23779	0	0
T7	421584	1785	0	0
T8	454536	2008	0	0
T9	9691440	449	0	0
T10	208056	377	0	0
T11	37200	389	0	0
T12	3037104	6564	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	856193	0	0
GntImpliesValid_A	436653732	856193	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	856193	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	12240262	0	0
ReadyAndValidImplyGrant_A	436653732	856193	0	0
ReqAndReadyImplyGrant_A	436653732	856193	0	0
ReqImpliesValid_A	436653732	2432949	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	856193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	12240262	0	0
T1	6015	336	0	0
T2	257724	3689	0	0
T3	382902	28064	0	0
T4	45967	2083	0	0
T7	17566	1105	0	0
T8	18939	1580	0	0
T9	403810	18990	0	0
T10	8669	296	0	0
T11	1550	32	0	0
T12	126546	5376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	2432949	0	0
T1	6015	72	0	0
T2	257724	1255	0	0
T3	382902	6538	0	0
T4	45967	3134	0	0
T7	17566	251	0	0
T8	18939	362	0	0
T9	403810	1539	0	0
T10	8669	75	0	0
T11	1550	51	0	0
T12	126546	855	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	856193	0	0
T1	6015	55	0	0
T2	257724	909	0	0
T3	382902	3829	0	0
T4	45967	2607	0	0
T7	17566	157	0	0
T8	18939	220	0	0
T9	403810	60	0	0
T10	8669	41	0	0
T11	1550	41	0	0
T12	126546	719	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	866171	0	0
GntImpliesValid_A	436653732	866171	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	866171	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	12316567	0	0
ReadyAndValidImplyGrant_A	436653732	866171	0	0
ReqAndReadyImplyGrant_A	436653732	866171	0	0
ReqImpliesValid_A	436653732	2498508	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	866171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	12316567	0	0
T1	6015	389	0	0
T2	257724	3675	0	0
T3	382902	26132	0	0
T4	45967	2169	0	0
T7	17566	1415	0	0
T8	18939	1403	0	0
T9	403810	11209	0	0
T10	8669	298	0	0
T11	1550	36	0	0
T12	126546	5700	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	2498508	0	0
T1	6015	81	0	0
T2	257724	1179	0	0
T3	382902	6318	0	0
T4	45967	3176	0	0
T7	17566	306	0	0
T8	18939	313	0	0
T9	403810	788	0	0
T10	8669	59	0	0
T11	1550	47	0	0
T12	126546	809	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	866171	0	0
T1	6015	52	0	0
T2	257724	891	0	0
T3	382902	3807	0	0
T4	45967	2671	0	0
T7	17566	183	0	0
T8	18939	212	0	0
T9	403810	38	0	0
T10	8669	45	0	0
T11	1550	41	0	0
T12	126546	727	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	212500	0	0
GntImpliesValid_A	436653732	212500	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	212500	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3086831	0	0
ReadyAndValidImplyGrant_A	436653732	212500	0	0
ReqAndReadyImplyGrant_A	436653732	212500	0	0
ReqImpliesValid_A	436653732	590691	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	212500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3086831	0	0
T1	6015	75	0	0
T2	257724	776	0	0
T3	382902	10394	0	0
T4	45967	662	0	0
T7	17566	269	0	0
T8	18939	429	0	0
T9	403810	5057	0	0
T10	8669	73	0	0
T11	1550	16	0	0
T12	126546	1302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	590691	0	0
T1	6015	9	0	0
T2	257724	209	0	0
T3	382902	6197	0	0
T4	45967	715	0	0
T7	17566	38	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	20	0	0
T11	1550	15	0	0
T12	126546	174	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212500	0	0
T1	6015	9	0	0
T2	257724	189	0	0
T3	382902	1708	0	0
T4	45967	687	0	0
T7	17566	34	0	0
T8	18939	57	0	0
T9	403810	17	0	0
T10	8669	8	0	0
T11	1550	15	0	0
T12	126546	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	223355	0	0
GntImpliesValid_A	436653732	223355	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	223355	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3086672	0	0
ReadyAndValidImplyGrant_A	436653732	223355	0	0
ReqAndReadyImplyGrant_A	436653732	223355	0	0
ReqImpliesValid_A	436653732	610663	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	223355	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3086672	0	0
T1	6015	40	0	0
T2	257724	840	0	0
T3	382902	6098	0	0
T4	45967	659	0	0
T7	17566	324	0	0
T8	18939	500	0	0
T9	403810	4483	0	0
T10	8669	52	0	0
T11	1550	8	0	0
T12	126546	1369	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	610663	0	0
T1	6015	4	0	0
T2	257724	251	0	0
T3	382902	1021	0	0
T4	45967	714	0	0
T7	17566	45	0	0
T8	18939	72	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223355	0	0
T1	6015	4	0	0
T2	257724	207	0	0
T3	382902	831	0	0
T4	45967	685	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	8	0	0
T11	1550	7	0	0
T12	126546	178	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	213406	0	0
GntImpliesValid_A	436653732	213406	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	213406	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	5207241	0	0
ReadyAndValidImplyGrant_A	436653732	213406	0	0
ReqAndReadyImplyGrant_A	436653732	213406	0	0
ReqImpliesValid_A	436653732	1192794	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	213406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	5207241	0	0
T1	6015	1260	0	0
T2	257724	1111	0	0
T3	382902	13273	0	0
T4	45967	3190	0	0
T7	17566	533	0	0
T8	18939	1441	0	0
T9	403810	1105	0	0
T10	8669	62	0	0
T11	1550	30	0	0
T12	126546	8379	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	1192794	0	0
T1	6015	254	0	0
T2	257724	278	0	0
T3	382902	1287	0	0
T4	45967	808	0	0
T7	17566	63	0	0
T8	18939	206	0	0
T9	403810	10	0	0
T10	8669	23	0	0
T11	1550	8	0	0
T12	126546	405	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	213406	0	0
T1	6015	97	0	0
T2	257724	229	0	0
T3	382902	758	0	0
T4	45967	607	0	0
T7	17566	29	0	0
T8	18939	72	0	0
T9	403810	10	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	212856	0	0
GntImpliesValid_A	436653732	212856	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	212856	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	4722109	0	0
ReadyAndValidImplyGrant_A	436653732	212856	0	0
ReqAndReadyImplyGrant_A	436653732	212856	0	0
ReqImpliesValid_A	436653732	1211154	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	212856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	4722109	0	0
T1	6015	64	0	0
T2	257724	1020	0	0
T3	382902	9185	0	0
T4	45967	7898	0	0
T7	17566	852	0	0
T8	18939	1037	0	0
T9	403810	5408	0	0
T10	8669	108	0	0
T11	1550	45	0	0
T12	126546	2176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	1211154	0	0
T1	6015	8	0	0
T2	257724	286	0	0
T3	382902	1022	0	0
T4	45967	1615	0	0
T7	17566	360	0	0
T8	18939	209	0	0
T9	403810	13	0	0
T10	8669	31	0	0
T11	1550	10	0	0
T12	126546	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212856	0	0
T1	6015	8	0	0
T2	257724	223	0	0
T3	382902	839	0	0
T4	45967	691	0	0
T7	17566	113	0	0
T8	18939	62	0	0
T9	403810	13	0	0
T10	8669	19	0	0
T11	1550	10	0	0
T12	126546	183	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	212852	0	0
GntImpliesValid_A	436653732	212852	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	212852	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	4841945	0	0
ReadyAndValidImplyGrant_A	436653732	212852	0	0
ReqAndReadyImplyGrant_A	436653732	212852	0	0
ReqImpliesValid_A	436653732	1120093	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	212852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	4841945	0	0
T1	6015	46	0	0
T2	257724	841	0	0
T3	382902	14686	0	0
T4	45967	3797	0	0
T7	17566	1147	0	0
T8	18939	844	0	0
T9	403810	1547	0	0
T10	8669	35	0	0
T11	1550	36	0	0
T12	126546	1634	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	1120093	0	0
T1	6015	11	0	0
T2	257724	253	0	0
T3	382902	10746	0	0
T4	45967	1095	0	0
T7	17566	45	0	0
T8	18939	170	0	0
T9	403810	14	0	0
T10	8669	13	0	0
T11	1550	18	0	0
T12	126546	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	212852	0	0
T1	6015	6	0	0
T2	257724	205	0	0
T3	382902	1717	0	0
T4	45967	700	0	0
T7	17566	29	0	0
T8	18939	63	0	0
T9	403810	14	0	0
T10	8669	10	0	0
T11	1550	10	0	0
T12	126546	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	214856	0	0
GntImpliesValid_A	436653732	214856	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	214856	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	4911737	0	0
ReadyAndValidImplyGrant_A	436653732	214856	0	0
ReqAndReadyImplyGrant_A	436653732	214856	0	0
ReqImpliesValid_A	436653732	1222227	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	214856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	4911737	0	0
T1	6015	35	0	0
T2	257724	1251	0	0
T3	382902	16893	0	0
T4	45967	5165	0	0
T7	17566	615	0	0
T8	18939	606	0	0
T9	403810	1325	0	0
T10	8669	27	0	0
T11	1550	33	0	0
T12	126546	3772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	1222227	0	0
T1	6015	3	0	0
T2	257724	353	0	0
T3	382902	5550	0	0
T4	45967	1177	0	0
T7	17566	63	0	0
T8	18939	119	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	20	0	0
T12	126546	206	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214856	0	0
T1	6015	3	0	0
T2	257724	275	0	0
T3	382902	1221	0	0
T4	45967	641	0	0
T7	17566	37	0	0
T8	18939	52	0	0
T9	403810	10	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	164	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	211787	0	0
GntImpliesValid_A	436653732	211787	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	211787	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3007983	0	0
ReadyAndValidImplyGrant_A	436653732	211787	0	0
ReqAndReadyImplyGrant_A	436653732	211787	0	0
ReqImpliesValid_A	436653732	559300	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	211787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3007983	0	0
T1	6015	45	0	0
T2	257724	891	0	0
T3	382902	8916	0	0
T4	45967	602	0	0
T7	17566	342	0	0
T8	18939	488	0	0
T9	403810	5594	0	0
T10	8669	56	0	0
T11	1550	11	0	0
T12	126546	1244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	559300	0	0
T1	6015	6	0	0
T2	257724	260	0	0
T3	382902	3797	0	0
T4	45967	645	0	0
T7	17566	39	0	0
T8	18939	108	0	0
T9	403810	321	0	0
T10	8669	11	0	0
T11	1550	14	0	0
T12	126546	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	211787	0	0
T1	6015	6	0	0
T2	257724	206	0	0
T3	382902	1317	0	0
T4	45967	622	0	0
T7	17566	36	0	0
T8	18939	68	0	0
T9	403810	17	0	0
T10	8669	11	0	0
T11	1550	12	0	0
T12	126546	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	214267	0	0
GntImpliesValid_A	436653732	214267	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	214267	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3005353	0	0
ReadyAndValidImplyGrant_A	436653732	214267	0	0
ReqAndReadyImplyGrant_A	436653732	214267	0	0
ReqImpliesValid_A	436653732	598587	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	214267	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3005353	0	0
T1	6015	54	0	0
T2	257724	795	0	0
T3	382902	6208	0	0
T4	45967	629	0	0
T7	17566	1023	0	0
T8	18939	462	0	0
T9	403810	4454	0	0
T10	8669	90	0	0
T11	1550	11	0	0
T12	126546	1521	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	598587	0	0
T1	6015	7	0	0
T2	257724	199	0	0
T3	382902	959	0	0
T4	45967	666	0	0
T7	17566	259	0	0
T8	18939	105	0	0
T9	403810	586	0	0
T10	8669	13	0	0
T11	1550	12	0	0
T12	126546	196	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	214267	0	0
T1	6015	7	0	0
T2	257724	187	0	0
T3	382902	804	0	0
T4	45967	646	0	0
T7	17566	139	0	0
T8	18939	60	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	206282	0	0
GntImpliesValid_A	436653732	206282	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	206282	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3009606	0	0
ReadyAndValidImplyGrant_A	436653732	206282	0	0
ReqAndReadyImplyGrant_A	436653732	206282	0	0
ReqImpliesValid_A	436653732	522319	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	206282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3009606	0	0
T1	6015	19	0	0
T2	257724	854	0	0
T3	382902	8302	0	0
T4	45967	634	0	0
T7	17566	273	0	0
T8	18939	432	0	0
T9	403810	4388	0	0
T10	8669	56	0	0
T11	1550	13	0	0
T12	126546	1443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	522319	0	0
T1	6015	4	0	0
T2	257724	248	0	0
T3	382902	3707	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	77	0	0
T9	403810	100	0	0
T10	8669	7	0	0
T11	1550	14	0	0
T12	126546	211	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	206282	0	0
T1	6015	4	0	0
T2	257724	198	0	0
T3	382902	1271	0	0
T4	45967	651	0	0
T7	17566	32	0	0
T8	18939	53	0	0
T9	403810	14	0	0
T10	8669	7	0	0
T11	1550	13	0	0
T12	126546	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	209936	0	0
GntImpliesValid_A	436653732	209936	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	209936	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3005016	0	0
ReadyAndValidImplyGrant_A	436653732	209936	0	0
ReqAndReadyImplyGrant_A	436653732	209936	0	0
ReqImpliesValid_A	436653732	581508	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	209936	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3005016	0	0
T1	6015	55	0	0
T2	257724	881	0	0
T3	382902	6130	0	0
T4	45967	629	0	0
T7	17566	285	0	0
T8	18939	489	0	0
T9	403810	7911	0	0
T10	8669	52	0	0
T11	1550	11	0	0
T12	126546	1425	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	581508	0	0
T1	6015	7	0	0
T2	257724	233	0	0
T3	382902	989	0	0
T4	45967	672	0	0
T7	17566	34	0	0
T8	18939	75	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	14	0	0
T12	126546	185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	209936	0	0
T1	6015	7	0	0
T2	257724	208	0	0
T3	382902	827	0	0
T4	45967	649	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	17	0	0
T10	8669	7	0	0
T11	1550	12	0	0
T12	126546	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	219540	0	0
GntImpliesValid_A	436653732	219540	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	219540	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	2957846	0	0
ReadyAndValidImplyGrant_A	436653732	219540	0	0
ReqAndReadyImplyGrant_A	436653732	219540	0	0
ReqImpliesValid_A	436653732	584290	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	219540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	2957846	0	0
T1	6015	74	0	0
T2	257724	932	0	0
T3	382902	8174	0	0
T4	45967	692	0	0
T7	17566	185	0	0
T8	18939	337	0	0
T9	403810	4523	0	0
T10	8669	92	0	0
T11	1550	11	0	0
T12	126546	1215	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	584290	0	0
T1	6015	10	0	0
T2	257724	236	0	0
T3	382902	2392	0	0
T4	45967	727	0	0
T7	17566	26	0	0
T8	18939	58	0	0
T9	403810	12	0	0
T10	8669	16	0	0
T11	1550	10	0	0
T12	126546	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219540	0	0
T1	6015	10	0	0
T2	257724	213	0	0
T3	382902	1306	0	0
T4	45967	708	0	0
T7	17566	26	0	0
T8	18939	49	0	0
T9	403810	12	0	0
T10	8669	13	0	0
T11	1550	10	0	0
T12	126546	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	215128	0	0
GntImpliesValid_A	436653732	215128	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	215128	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3127381	0	0
ReadyAndValidImplyGrant_A	436653732	215128	0	0
ReqAndReadyImplyGrant_A	436653732	215128	0	0
ReqImpliesValid_A	436653732	558193	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	215128	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3127381	0	0
T1	6015	44	0	0
T2	257724	1011	0	0
T3	382902	5766	0	0
T4	45967	620	0	0
T7	17566	261	0	0
T8	18939	426	0	0
T9	403810	3811	0	0
T10	8669	53	0	0
T11	1550	9	0	0
T12	126546	1183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	558193	0	0
T1	6015	6	0	0
T2	257724	289	0	0
T3	382902	979	0	0
T4	45967	683	0	0
T7	17566	39	0	0
T8	18939	61	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	171	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215128	0	0
T1	6015	6	0	0
T2	257724	232	0	0
T3	382902	773	0	0
T4	45967	650	0	0
T7	17566	35	0	0
T8	18939	55	0	0
T9	403810	14	0	0
T10	8669	9	0	0
T11	1550	8	0	0
T12	126546	164	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	217364	0	0
GntImpliesValid_A	436653732	217364	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	217364	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3067512	0	0
ReadyAndValidImplyGrant_A	436653732	217364	0	0
ReqAndReadyImplyGrant_A	436653732	217364	0	0
ReqImpliesValid_A	436653732	582821	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	217364	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3067512	0	0
T1	6015	40	0	0
T2	257724	827	0	0
T3	382902	6113	0	0
T4	45967	611	0	0
T7	17566	223	0	0
T8	18939	400	0	0
T9	403810	3458	0	0
T10	8669	81	0	0
T11	1550	14	0	0
T12	126546	1600	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	582821	0	0
T1	6015	4	0	0
T2	257724	244	0	0
T3	382902	979	0	0
T4	45967	666	0	0
T7	17566	33	0	0
T8	18939	102	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217364	0	0
T1	6015	4	0	0
T2	257724	202	0	0
T3	382902	806	0	0
T4	45967	637	0	0
T7	17566	25	0	0
T8	18939	62	0	0
T9	403810	11	0	0
T10	8669	9	0	0
T11	1550	13	0	0
T12	126546	189	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	223027	0	0
GntImpliesValid_A	436653732	223027	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	223027	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3030685	0	0
ReadyAndValidImplyGrant_A	436653732	223027	0	0
ReqAndReadyImplyGrant_A	436653732	223027	0	0
ReqImpliesValid_A	436653732	622119	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	223027	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3030685	0	0
T1	6015	30	0	0
T2	257724	833	0	0
T3	382902	6213	0	0
T4	45967	610	0	0
T7	17566	217	0	0
T8	18939	467	0	0
T9	403810	3525	0	0
T10	8669	69	0	0
T11	1550	11	0	0
T12	126546	1403	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	622119	0	0
T1	6015	4	0	0
T2	257724	284	0	0
T3	382902	1100	0	0
T4	45967	653	0	0
T7	17566	30	0	0
T8	18939	82	0	0
T9	403810	8	0	0
T10	8669	24	0	0
T11	1550	10	0	0
T12	126546	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	223027	0	0
T1	6015	4	0	0
T2	257724	219	0	0
T3	382902	836	0	0
T4	45967	630	0	0
T7	17566	30	0	0
T8	18939	60	0	0
T9	403810	8	0	0
T10	8669	11	0	0
T11	1550	10	0	0
T12	126546	176	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	231216	0	0
GntImpliesValid_A	436653732	231216	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	231216	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3120901	0	0
ReadyAndValidImplyGrant_A	436653732	231216	0	0
ReqAndReadyImplyGrant_A	436653732	231216	0	0
ReqImpliesValid_A	436653732	577767	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	231216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3120901	0	0
T1	6015	71	0	0
T2	257724	969	0	0
T3	382902	10178	0	0
T4	45967	694	0	0
T7	17566	1471	0	0
T8	18939	340	0	0
T9	403810	5666	0	0
T10	8669	45	0	0
T11	1550	18	0	0
T12	126546	1651	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	577767	0	0
T1	6015	7	0	0
T2	257724	327	0	0
T3	382902	4146	0	0
T4	45967	755	0	0
T7	17566	636	0	0
T8	18939	48	0	0
T9	403810	86	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	231216	0	0
T1	6015	7	0	0
T2	257724	242	0	0
T3	382902	1472	0	0
T4	45967	723	0	0
T7	17566	217	0	0
T8	18939	48	0	0
T9	403810	13	0	0
T10	8669	8	0	0
T11	1550	17	0	0
T12	126546	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	219896	0	0
GntImpliesValid_A	436653732	219896	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	219896	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3062814	0	0
ReadyAndValidImplyGrant_A	436653732	219896	0	0
ReqAndReadyImplyGrant_A	436653732	219896	0	0
ReqImpliesValid_A	436653732	587859	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	219896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3062814	0	0
T1	6015	21	0	0
T2	257724	972	0	0
T3	382902	5794	0	0
T4	45967	642	0	0
T7	17566	222	0	0
T8	18939	392	0	0
T9	403810	3215	0	0
T10	8669	117	0	0
T11	1550	9	0	0
T12	126546	1457	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	587859	0	0
T1	6015	2	0	0
T2	257724	282	0	0
T3	382902	998	0	0
T4	45967	703	0	0
T7	17566	46	0	0
T8	18939	83	0	0
T9	403810	353	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	219896	0	0
T1	6015	2	0	0
T2	257724	232	0	0
T3	382902	778	0	0
T4	45967	671	0	0
T7	17566	32	0	0
T8	18939	51	0	0
T9	403810	10	0	0
T10	8669	11	0	0
T11	1550	8	0	0
T12	126546	182	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	202414	0	0
GntImpliesValid_A	436653732	202414	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	202414	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	2968280	0	0
ReadyAndValidImplyGrant_A	436653732	202414	0	0
ReqAndReadyImplyGrant_A	436653732	202414	0	0
ReqImpliesValid_A	436653732	525305	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	202414	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	2968280	0	0
T1	6015	54	0	0
T2	257724	829	0	0
T3	382902	6211	0	0
T4	45967	625	0	0
T7	17566	223	0	0
T8	18939	490	0	0
T9	403810	1830	0	0
T10	8669	113	0	0
T11	1550	11	0	0
T12	126546	1687	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	525305	0	0
T1	6015	9	0	0
T2	257724	262	0	0
T3	382902	1036	0	0
T4	45967	662	0	0
T7	17566	29	0	0
T8	18939	91	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	202414	0	0
T1	6015	9	0	0
T2	257724	213	0	0
T3	382902	833	0	0
T4	45967	642	0	0
T7	17566	29	0	0
T8	18939	64	0	0
T9	403810	8	0	0
T10	8669	12	0	0
T11	1550	10	0	0
T12	126546	198	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	217671	0	0
GntImpliesValid_A	436653732	217671	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	217671	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3028102	0	0
ReadyAndValidImplyGrant_A	436653732	217671	0	0
ReqAndReadyImplyGrant_A	436653732	217671	0	0
ReqImpliesValid_A	436653732	562590	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	217671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3028102	0	0
T1	6015	641	0	0
T2	257724	1042	0	0
T3	382902	6252	0	0
T4	45967	636	0	0
T7	17566	262	0	0
T8	18939	362	0	0
T9	403810	3916	0	0
T10	8669	101	0	0
T11	1550	16	0	0
T12	126546	1483	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	562590	0	0
T1	6015	588	0	0
T2	257724	258	0	0
T3	382902	963	0	0
T4	45967	679	0	0
T7	17566	30	0	0
T8	18939	56	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	217671	0	0
T1	6015	175	0	0
T2	257724	233	0	0
T3	382902	814	0	0
T4	45967	656	0	0
T7	17566	30	0	0
T8	18939	50	0	0
T9	403810	15	0	0
T10	8669	9	0	0
T11	1550	15	0	0
T12	126546	200	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	221546	0	0
GntImpliesValid_A	436653732	221546	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	221546	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3111832	0	0
ReadyAndValidImplyGrant_A	436653732	221546	0	0
ReqAndReadyImplyGrant_A	436653732	221546	0	0
ReqImpliesValid_A	436653732	613781	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	221546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3111832	0	0
T1	6015	38	0	0
T2	257724	932	0	0
T3	382902	8728	0	0
T4	45967	646	0	0
T7	17566	165	0	0
T8	18939	460	0	0
T9	403810	799	0	0
T10	8669	110	0	0
T11	1550	16	0	0
T12	126546	1423	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	613781	0	0
T1	6015	4	0	0
T2	257724	303	0	0
T3	382902	3439	0	0
T4	45967	685	0	0
T7	17566	22	0	0
T8	18939	142	0	0
T9	403810	7	0	0
T10	8669	23	0	0
T11	1550	15	0	0
T12	126546	192	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	221546	0	0
T1	6015	4	0	0
T2	257724	226	0	0
T3	382902	1283	0	0
T4	45967	664	0	0
T7	17566	22	0	0
T8	18939	66	0	0
T9	403810	7	0	0
T10	8669	12	0	0
T11	1550	15	0	0
T12	126546	190	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	215773	0	0
GntImpliesValid_A	436653732	215773	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	215773	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	3032893	0	0
ReadyAndValidImplyGrant_A	436653732	215773	0	0
ReqAndReadyImplyGrant_A	436653732	215773	0	0
ReqImpliesValid_A	436653732	602382	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	0	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	215773	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	3032893	0	0
T1	6015	45	0	0
T2	257724	841	0	0
T3	382902	6149	0	0
T4	45967	614	0	0
T7	17566	302	0	0
T8	18939	405	0	0
T9	403810	3012	0	0
T10	8669	69	0	0
T11	1550	8	0	0
T12	126546	1622	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	602382	0	0
T1	6015	7	0	0
T2	257724	238	0	0
T3	382902	1007	0	0
T4	45967	643	0	0
T7	17566	41	0	0
T8	18939	64	0	0
T9	403810	519	0	0
T10	8669	13	0	0
T11	1550	11	0	0
T12	126546	247	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	215773	0	0
T1	6015	7	0	0
T2	257724	205	0	0
T3	382902	817	0	0
T4	45967	627	0	0
T7	17566	34	0	0
T8	18939	52	0	0
T9	403810	11	0	0
T10	8669	13	0	0
T11	1550	9	0	0
T12	126546	211	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	882689	0	0
GntImpliesValid_A	436653732	882689	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	882689	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	11381065	0	0
ReadyAndValidImplyGrant_A	436653732	882689	0	0
ReqAndReadyImplyGrant_A	436653732	882689	0	0
ReqImpliesValid_A	436653732	2368019	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	20540	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	882689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	11381065	0	0
T1	6015	459	0	0
T2	257724	3187	0	0
T3	382902	24576	0	0
T4	45967	3	0	0
T7	17566	1482	0	0
T8	18939	1426	0	0
T9	403810	15863	0	0
T10	8669	252	0	0
T11	1550	1	0	0
T12	126546	4901	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	2368019	0	0
T1	6015	72	0	0
T2	257724	1251	0	0
T3	382902	5972	0	0
T4	45967	2686	0	0
T7	17566	620	0	0
T8	18939	365	0	0
T9	403810	3338	0	0
T10	8669	61	0	0
T11	1550	47	0	0
T12	126546	795	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	20540	0	900
T3	382902	2	0	1
T4	45967	47	0	1
T7	17566	3	0	1
T8	18939	0	0	1
T9	403810	0	0	1
T10	8669	0	0	1
T11	1550	0	0	1
T12	126546	0	0	1
T13	241356	0	0	1
T14	45066	0	0	1
T15	0	6	0	0
T18	0	16	0	0
T20	0	11	0	0
T21	0	42	0	0
T22	0	23	0	0
T23	0	436	0	0
T24	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	882689	0	0
T1	6015	64	0	0
T2	257724	979	0	0
T3	382902	3706	0	0
T4	45967	2686	0	0
T7	17566	292	0	0
T8	18939	211	0	0
T9	403810	57	0	0
T10	8669	41	0	0
T11	1550	47	0	0
T12	126546	726	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436653732	436530875	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436653732	846446	0	0
GntImpliesValid_A	436653732	846446	0	0
GrantKnown_A	436653732	436530875	0	0
IdxKnown_A	436653732	436530875	0	0
IndexIsCorrect_A	436653732	846446	0	0
LockArbDecision_A	436653732	0	0	0
NoReadyValidNoGrant_A	436653732	366372157	0	0
ReadyAndValidImplyGrant_A	436653732	846446	0	0
ReqAndReadyImplyGrant_A	436653732	846446	0	0
ReqImpliesValid_A	436653732	13350637	0	0
ReqStaysHighUntilGranted0_M	436653732	0	0	0
RoundRobin_A	436653732	24477	0	900
ValidKnown_A	436653732	436530875	0	0
gen_data_port_assertion.DataFlow_A	436653732	846446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	366372157	0	0
T1	6015	4728	0	0
T2	257724	214450	0	0
T3	382902	321318	0	0
T4	45967	1	0	0
T7	17566	13848	0	0
T8	18939	15656	0	0
T9	403810	385018	0	0
T10	8669	7595	0	0
T11	1550	1	0	0
T12	126546	109968	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	13350637	0	0
T1	6015	437	0	0
T2	257724	3990	0	0
T3	382902	30293	0	0
T4	45967	2628	0	0
T7	17566	1146	0	0
T8	18939	1702	0	0
T9	403810	18026	0	0
T10	8669	331	0	0
T11	1550	35	0	0
T12	126546	5775	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	24477	0	900
T3	382902	4	0	1
T4	45967	48	0	1
T7	17566	0	0	1
T8	18939	0	0	1
T9	403810	0	0	1
T10	8669	0	0	1
T11	1550	0	0	1
T12	126546	0	0	1
T13	241356	16	0	1
T14	45066	1	0	1
T15	0	8	0	0
T16	0	1	0	0
T17	0	25	0	0
T19	0	1	0	0
T20	0	13	0	0
T21	0	22	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	436530875	0	0
T1	6015	5864	0	0
T2	257724	257722	0	0
T3	382902	382787	0	0
T4	45967	45796	0	0
T7	17566	16981	0	0
T8	18939	18906	0	0
T9	403810	403786	0	0
T10	8669	8663	0	0
T11	1550	1535	0	0
T12	126546	126509	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436653732	846446	0	0
T1	6015	52	0	0
T2	257724	898	0	0
T3	382902	3828	0	0
T4	45967	2628	0	0
T7	17566	151	0	0
T8	18939	208	0	0
T9	403810	48	0	0
T10	8669	44	0	0
T11	1550	35	0	0
T12	126546	715	0	0