Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1470940 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 234299 1 T1 164 T2 112 T3 26


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 579580 1 T1 435 T2 228 T3 71
values[0x0] 548140 1 T1 395 T2 242 T3 66
values[0x1] 577519 1 T1 407 T2 245 T3 58


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1136907 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 568332 1 T1 400 T2 244 T3 67


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26566 1 T2 11 T3 2 T7 38
valid_sources[0x01] 26393 1 T1 36 T2 12 T3 6
valid_sources[0x02] 27472 1 T1 74 T2 13 T3 12
valid_sources[0x03] 26550 1 T2 15 T3 5 T7 24
valid_sources[0x04] 27105 1 T2 11 T3 4 T7 31
valid_sources[0x05] 27420 1 T1 45 T2 10 T7 29
valid_sources[0x06] 26545 1 T2 16 T3 10 T7 20
valid_sources[0x07] 25887 1 T1 49 T2 7 T7 18
valid_sources[0x08] 26385 1 T1 18 T2 17 T3 4
valid_sources[0x09] 26494 1 T1 65 T2 7 T7 27
valid_sources[0x0a] 26751 1 T1 15 T2 20 T3 5
valid_sources[0x0b] 26648 1 T2 16 T3 1 T7 42
valid_sources[0x0c] 25703 1 T2 11 T3 3 T7 26
valid_sources[0x0d] 26221 1 T1 19 T2 10 T3 3
valid_sources[0x0e] 27388 1 T2 15 T3 7 T7 28
valid_sources[0x0f] 26599 1 T1 6 T2 4 T7 45
valid_sources[0x10] 26215 1 T2 14 T3 2 T7 38
valid_sources[0x11] 26187 1 T2 10 T7 20 T9 5
valid_sources[0x12] 26783 1 T1 59 T2 8 T3 1
valid_sources[0x13] 26903 1 T2 12 T7 28 T8 20
valid_sources[0x14] 26283 1 T1 9 T2 10 T3 1
valid_sources[0x15] 26438 1 T2 8 T7 36 T8 25
valid_sources[0x16] 27180 1 T1 42 T2 15 T7 26
valid_sources[0x17] 26295 1 T2 12 T7 33 T8 22
valid_sources[0x18] 26611 1 T1 57 T2 14 T3 6
valid_sources[0x19] 26309 1 T1 14 T2 11 T7 35
valid_sources[0x1a] 26784 1 T2 12 T3 17 T7 46
valid_sources[0x1b] 26849 1 T2 9 T3 1 T7 34
valid_sources[0x1c] 25913 1 T2 11 T7 44 T9 4
valid_sources[0x1d] 26922 1 T1 29 T2 14 T3 1
valid_sources[0x1e] 26767 1 T1 5 T2 9 T3 10
valid_sources[0x1f] 27100 1 T1 32 T2 6 T3 7
valid_sources[0x20] 27220 1 T2 18 T3 16 T7 31


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24339 1 T1 30 T2 5 T3 6
values[0x0] all_enables biggest_size 185293 1 T1 114 T2 99 T3 19
values[0x1] all_enables biggest_size 24667 1 T1 20 T2 8 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1484534 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 242593 1 T1 199 T2 87 T3 22


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 591384 1 T1 457 T2 241 T3 37
values[0x0] 545763 1 T1 419 T2 195 T3 36
values[0x1] 589980 1 T1 457 T2 224 T3 45


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1139178 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 587949 1 T1 487 T2 226 T3 49


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26389 1 T1 6 T2 8 T3 6
valid_sources[0x01] 26846 1 T1 80 T2 14 T7 33
valid_sources[0x02] 26698 1 T1 25 T2 11 T3 2
valid_sources[0x03] 26494 1 T1 17 T2 2 T7 35
valid_sources[0x04] 26379 1 T2 15 T7 23 T9 2
valid_sources[0x05] 26771 1 T1 14 T2 10 T3 1
valid_sources[0x06] 26910 1 T2 8 T3 2 T7 37
valid_sources[0x07] 26073 1 T2 8 T3 5 T7 36
valid_sources[0x08] 26862 1 T2 11 T3 5 T7 33
valid_sources[0x09] 27174 1 T2 8 T3 3 T7 28
valid_sources[0x0a] 26932 1 T1 46 T2 14 T7 52
valid_sources[0x0b] 27146 1 T2 7 T3 1 T7 45
valid_sources[0x0c] 26843 1 T1 27 T2 10 T3 6
valid_sources[0x0d] 26976 1 T1 13 T2 9 T3 1
valid_sources[0x0e] 27035 1 T1 14 T2 11 T3 2
valid_sources[0x0f] 26394 1 T2 4 T3 2 T7 45
valid_sources[0x10] 27115 1 T1 80 T2 6 T3 1
valid_sources[0x11] 26829 1 T1 7 T2 8 T3 1
valid_sources[0x12] 27472 1 T1 12 T2 8 T3 4
valid_sources[0x13] 26922 1 T1 48 T2 13 T7 17
valid_sources[0x14] 27096 1 T1 41 T2 1 T3 1
valid_sources[0x15] 27649 1 T1 3 T2 6 T7 34
valid_sources[0x16] 27035 1 T1 28 T2 20 T3 1
valid_sources[0x17] 26720 1 T1 11 T2 8 T7 41
valid_sources[0x18] 26358 1 T2 6 T3 1 T7 26
valid_sources[0x19] 27174 1 T1 2 T2 13 T3 1
valid_sources[0x1a] 27208 1 T1 1 T2 3 T3 2
valid_sources[0x1b] 27509 1 T1 41 T2 13 T3 1
valid_sources[0x1c] 26838 1 T1 10 T2 15 T7 33
valid_sources[0x1d] 26908 1 T1 9 T2 26 T3 2
valid_sources[0x1e] 26706 1 T1 42 T2 16 T3 1
valid_sources[0x1f] 27015 1 T1 9 T2 11 T3 4
valid_sources[0x20] 27734 1 T1 29 T2 12 T3 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25398 1 T1 18 T2 7 T3 3
values[0x0] all_enables biggest_size 191934 1 T1 162 T2 67 T3 15
values[0x1] all_enables biggest_size 25261 1 T1 19 T2 13 T3 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1486346 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 236131 1 T1 184 T2 89 T3 23


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 584495 1 T1 453 T2 251 T3 58
values[0x0] 554512 1 T1 435 T2 210 T3 48
values[0x1] 583470 1 T1 410 T2 241 T3 75


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1149569 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 572908 1 T1 431 T2 246 T3 66


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27050 1 T2 15 T3 2 T7 26
valid_sources[0x01] 26631 1 T1 21 T2 10 T3 6
valid_sources[0x02] 26674 1 T1 1 T2 12 T3 5
valid_sources[0x03] 27132 1 T1 58 T2 11 T3 4
valid_sources[0x04] 26663 1 T1 32 T2 10 T3 6
valid_sources[0x05] 26915 1 T2 6 T3 2 T7 26
valid_sources[0x06] 26920 1 T2 10 T3 2 T7 37
valid_sources[0x07] 27228 1 T2 8 T3 2 T7 32
valid_sources[0x08] 26740 1 T1 63 T2 7 T3 4
valid_sources[0x09] 26798 1 T2 8 T3 2 T7 25
valid_sources[0x0a] 26754 1 T1 69 T2 8 T3 2
valid_sources[0x0b] 27193 1 T1 2 T2 12 T3 2
valid_sources[0x0c] 27146 1 T1 31 T2 28 T3 1
valid_sources[0x0d] 26600 1 T2 10 T3 1 T7 29
valid_sources[0x0e] 26916 1 T1 1 T2 16 T3 3
valid_sources[0x0f] 26625 1 T2 7 T3 3 T7 43
valid_sources[0x10] 26375 1 T1 59 T2 15 T3 2
valid_sources[0x11] 26992 1 T1 6 T2 5 T3 3
valid_sources[0x12] 26771 1 T1 13 T2 20 T3 1
valid_sources[0x13] 27662 1 T2 19 T3 4 T7 28
valid_sources[0x14] 27302 1 T1 120 T2 10 T3 2
valid_sources[0x15] 26542 1 T2 11 T3 1 T7 35
valid_sources[0x16] 27282 1 T2 5 T3 3 T7 33
valid_sources[0x17] 27191 1 T2 18 T3 3 T7 21
valid_sources[0x18] 26997 1 T2 3 T3 6 T7 14
valid_sources[0x19] 27115 1 T2 11 T3 5 T7 26
valid_sources[0x1a] 27492 1 T2 9 T3 2 T7 32
valid_sources[0x1b] 26553 1 T1 27 T2 6 T3 1
valid_sources[0x1c] 26687 1 T2 5 T7 33 T10 269
valid_sources[0x1d] 26334 1 T2 11 T3 3 T7 31
valid_sources[0x1e] 26611 1 T2 9 T3 1 T7 43
valid_sources[0x1f] 26826 1 T2 7 T3 3 T7 23
valid_sources[0x20] 27095 1 T2 7 T3 4 T7 35


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24585 1 T1 15 T2 8 T3 2
values[0x0] all_enables biggest_size 186493 1 T1 152 T2 68 T3 18
values[0x1] all_enables biggest_size 25053 1 T1 17 T2 13 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%