Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7323445	0	0
GntImpliesValid_A	2147483647	7323445	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7323445	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	471130458	0	0
ReadyAndValidImplyGrant_A	2147483647	7323445	0	0
ReqAndReadyImplyGrant_A	2147483647	7323445	0	0
ReqImpliesValid_A	2147483647	34120326	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40695	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7323445	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	124008	123048	0	0
T2	507624	507288	0	0
T3	11712696	11711808	0	0
T7	1507152	1505112	0	0
T8	221328	220272	0	0
T9	55488	54576	0	0
T10	12462024	12458376	0	0
T11	18153552	18131784	0	0
T12	153912	153624	0	0
T13	281256	280968	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	124008	123048	0	0
T2	507624	507288	0	0
T3	11712696	11711808	0	0
T7	1507152	1505112	0	0
T8	221328	220272	0	0
T9	55488	54576	0	0
T10	12462024	12458376	0	0
T11	18153552	18131784	0	0
T12	153912	153624	0	0
T13	281256	280968	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	124008	123048	0	0
T2	507624	507288	0	0
T3	11712696	11711808	0	0
T7	1507152	1505112	0	0
T8	221328	220272	0	0
T9	55488	54576	0	0
T10	12462024	12458376	0	0
T11	18153552	18131784	0	0
T12	153912	153624	0	0
T13	281256	280968	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	471130458	0	0
T1	124008	2356	0	0
T2	507624	31792	0	0
T3	11712696	617762	0	0
T7	1507152	100858	0	0
T8	221328	5236	0	0
T9	55488	699	0	0
T10	12462024	697621	0	0
T11	18153552	1077002	0	0
T12	153912	4031	0	0
T13	281256	13226	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34120326	0	0
T1	124008	2237	0	0
T2	507624	4518	0	0
T3	11712696	17462	0	0
T7	1507152	14438	0	0
T8	221328	2620	0	0
T9	55488	566	0	0
T10	12462024	116422	0	0
T11	18153552	261445	0	0
T12	153912	4873	0	0
T13	281256	1148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40695	0	21600
T1	10334	3	0	2
T2	42302	0	0	2
T3	976058	0	0	2
T7	125596	0	0	2
T8	18444	7	0	2
T9	4624	0	0	2
T10	1038502	25	0	2
T11	1512796	53	0	2
T12	12826	17	0	2
T13	23438	0	0	2
T14	0	195	0	0
T15	0	1	0	0
T16	0	9	0	0
T17	0	11	0	0
T18	0	27	0	0
T19	0	2	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	124008	123048	0	0
T2	507624	507288	0	0
T3	11712696	11711808	0	0
T7	1507152	1505112	0	0
T8	221328	220272	0	0
T9	55488	54576	0	0
T10	12462024	12458376	0	0
T11	18153552	18131784	0	0
T12	153912	153624	0	0
T13	281256	280968	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7323445	0	0
T1	124008	1993	0	0
T2	507624	2076	0	0
T3	11712696	494	0	0
T7	1507152	5986	0	0
T8	221328	2468	0	0
T9	55488	484	0	0
T10	12462024	42117	0	0
T11	18153552	76422	0	0
T12	153912	4271	0	0
T13	281256	490	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	811743	0	0
GntImpliesValid_A	436370503	811743	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	811743	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	11996165	0	0
ReadyAndValidImplyGrant_A	436370503	811743	0	0
ReqAndReadyImplyGrant_A	436370503	811743	0	0
ReqImpliesValid_A	436370503	2377895	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	811743	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	11996165	0	0
T1	5167	185	0	0
T2	21151	1868	0	0
T3	488029	16426	0	0
T7	62798	5022	0	0
T8	9222	266	0	0
T9	2312	45	0	0
T10	519251	27660	0	0
T11	756398	62244	0	0
T12	6413	342	0	0
T13	11719	413	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2377895	0	0
T1	5167	264	0	0
T2	21151	448	0	0
T3	488029	634	0	0
T7	62798	1249	0	0
T8	9222	291	0	0
T9	2312	68	0	0
T10	519251	5611	0	0
T11	756398	25120	0	0
T12	6413	613	0	0
T13	11719	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	811743	0	0
T1	5167	224	0	0
T2	21151	236	0	0
T3	488029	45	0	0
T7	62798	690	0	0
T8	9222	278	0	0
T9	2312	56	0	0
T10	519251	3902	0	0
T11	756398	10783	0	0
T12	6413	477	0	0
T13	11719	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	826579	0	0
GntImpliesValid_A	436370503	826579	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	826579	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	12035347	0	0
ReadyAndValidImplyGrant_A	436370503	826579	0	0
ReqAndReadyImplyGrant_A	436370503	826579	0	0
ReqImpliesValid_A	436370503	2453191	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	826579	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	12035347	0	0
T1	5167	177	0	0
T2	21151	1653	0	0
T3	488029	17566	0	0
T7	62798	5438	0	0
T8	9222	245	0	0
T9	2312	35	0	0
T10	519251	34176	0	0
T11	756398	53415	0	0
T12	6413	329	0	0
T13	11719	504	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2453191	0	0
T1	5167	250	0	0
T2	21151	340	0	0
T3	488029	2128	0	0
T7	62798	1277	0	0
T8	9222	258	0	0
T9	2312	48	0	0
T10	519251	10440	0	0
T11	756398	18347	0	0
T12	6413	630	0	0
T13	11719	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	826579	0	0
T1	5167	213	0	0
T2	21151	208	0	0
T3	488029	50	0	0
T7	62798	712	0	0
T8	9222	251	0	0
T9	2312	41	0	0
T10	519251	5559	0	0
T11	756398	7788	0	0
T12	6413	479	0	0
T13	11719	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	196195	0	0
GntImpliesValid_A	436370503	196195	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	196195	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2986306	0	0
ReadyAndValidImplyGrant_A	436370503	196195	0	0
ReqAndReadyImplyGrant_A	436370503	196195	0	0
ReqImpliesValid_A	436370503	574034	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	196195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2986306	0	0
T1	5167	58	0	0
T2	21151	465	0	0
T3	488029	5943	0	0
T7	62798	1162	0	0
T8	9222	50	0	0
T9	2312	19	0	0
T10	519251	5736	0	0
T11	756398	9752	0	0
T12	6413	101	0	0
T13	11719	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	574034	0	0
T1	5167	61	0	0
T2	21151	88	0	0
T3	488029	23	0	0
T7	62798	283	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	893	0	0
T11	756398	1487	0	0
T12	6413	110	0	0
T13	11719	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196195	0	0
T1	5167	59	0	0
T2	21151	68	0	0
T3	488029	17	0	0
T7	62798	168	0	0
T8	9222	49	0	0
T9	2312	18	0	0
T10	519251	783	0	0
T11	756398	1274	0	0
T12	6413	105	0	0
T13	11719	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	201272	0	0
GntImpliesValid_A	436370503	201272	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	201272	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2998512	0	0
ReadyAndValidImplyGrant_A	436370503	201272	0	0
ReqAndReadyImplyGrant_A	436370503	201272	0	0
ReqImpliesValid_A	436370503	591306	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	201272	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2998512	0	0
T1	5167	39	0	0
T2	21151	445	0	0
T3	488029	5980	0	0
T7	62798	1238	0	0
T8	9222	59	0	0
T9	2312	16	0	0
T10	519251	5440	0	0
T11	756398	11342	0	0
T12	6413	125	0	0
T13	11719	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	591306	0	0
T1	5167	42	0	0
T2	21151	71	0	0
T3	488029	18	0	0
T7	62798	237	0	0
T8	9222	58	0	0
T9	2312	23	0	0
T10	519251	878	0	0
T11	756398	3376	0	0
T12	6413	146	0	0
T13	11719	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	201272	0	0
T1	5167	40	0	0
T2	21151	60	0	0
T3	488029	18	0	0
T7	62798	180	0	0
T8	9222	58	0	0
T9	2312	19	0	0
T10	519251	723	0	0
T11	756398	1595	0	0
T12	6413	135	0	0
T13	11719	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	196739	0	0
GntImpliesValid_A	436370503	196739	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	196739	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	5101937	0	0
ReadyAndValidImplyGrant_A	436370503	196739	0	0
ReqAndReadyImplyGrant_A	436370503	196739	0	0
ReqImpliesValid_A	436370503	1078686	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	196739	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	5101937	0	0
T1	5167	370	0	0
T2	21151	382	0	0
T3	488029	4059	0	0
T7	62798	5357	0	0
T8	9222	482	0	0
T9	2312	169	0	0
T10	519251	10055	0	0
T11	756398	14365	0	0
T12	6413	334	0	0
T13	11719	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	1078686	0	0
T1	5167	118	0	0
T2	21151	70	0	0
T3	488029	54	0	0
T7	62798	688	0	0
T8	9222	95	0	0
T9	2312	46	0	0
T10	519251	1112	0	0
T11	756398	7919	0	0
T12	6413	133	0	0
T13	11719	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	196739	0	0
T1	5167	66	0	0
T2	21151	64	0	0
T3	488029	12	0	0
T7	62798	165	0	0
T8	9222	72	0	0
T9	2312	20	0	0
T10	519251	808	0	0
T11	756398	2212	0	0
T12	6413	104	0	0
T13	11719	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	206700	0	0
GntImpliesValid_A	436370503	206700	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	206700	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	5230520	0	0
ReadyAndValidImplyGrant_A	436370503	206700	0	0
ReqAndReadyImplyGrant_A	436370503	206700	0	0
ReqImpliesValid_A	436370503	1207932	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	206700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	5230520	0	0
T1	5167	244	0	0
T2	21151	329	0	0
T3	488029	1570	0	0
T7	62798	1677	0	0
T8	9222	1488	0	0
T9	2312	53	0	0
T10	519251	14746	0	0
T11	756398	41285	0	0
T12	6413	470	0	0
T13	11719	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	1207932	0	0
T1	5167	62	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	207	0	0
T8	9222	96	0	0
T9	2312	15	0	0
T10	519251	1308	0	0
T11	756398	3056	0	0
T12	6413	220	0	0
T13	11719	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206700	0	0
T1	5167	44	0	0
T2	21151	48	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	747	0	0
T11	756398	1135	0	0
T12	6413	135	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	199913	0	0
GntImpliesValid_A	436370503	199913	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	199913	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	5182720	0	0
ReadyAndValidImplyGrant_A	436370503	199913	0	0
ReqAndReadyImplyGrant_A	436370503	199913	0	0
ReqImpliesValid_A	436370503	1166486	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	199913	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	5182720	0	0
T1	5167	280	0	0
T2	21151	467	0	0
T3	488029	2018	0	0
T7	62798	4224	0	0
T8	9222	1081	0	0
T9	2312	68	0	0
T10	519251	10777	0	0
T11	756398	18891	0	0
T12	6413	384	0	0
T13	11719	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	1166486	0	0
T1	5167	86	0	0
T2	21151	77	0	0
T3	488029	11	0	0
T7	62798	513	0	0
T8	9222	130	0	0
T9	2312	18	0	0
T10	519251	2824	0	0
T11	756398	19901	0	0
T12	6413	151	0	0
T13	11719	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199913	0	0
T1	5167	51	0	0
T2	21151	53	0	0
T3	488029	11	0	0
T7	62798	177	0	0
T8	9222	65	0	0
T9	2312	15	0	0
T10	519251	1311	0	0
T11	756398	3184	0	0
T12	6413	113	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	206555	0	0
GntImpliesValid_A	436370503	206555	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	206555	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	5109123	0	0
ReadyAndValidImplyGrant_A	436370503	206555	0	0
ReqAndReadyImplyGrant_A	436370503	206555	0	0
ReqImpliesValid_A	436370503	1241503	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	206555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	5109123	0	0
T1	5167	234	0	0
T2	21151	877	0	0
T3	488029	2398	0	0
T7	62798	3337	0	0
T8	9222	587	0	0
T9	2312	105	0	0
T10	519251	10999	0	0
T11	756398	13931	0	0
T12	6413	362	0	0
T13	11719	215	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	1241503	0	0
T1	5167	71	0	0
T2	21151	92	0	0
T3	488029	11	0	0
T7	62798	447	0	0
T8	9222	92	0	0
T9	2312	31	0	0
T10	519251	1144	0	0
T11	756398	3192	0	0
T12	6413	162	0	0
T13	11719	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	206555	0	0
T1	5167	49	0	0
T2	21151	56	0	0
T3	488029	11	0	0
T7	62798	155	0	0
T8	9222	81	0	0
T9	2312	19	0	0
T10	519251	826	0	0
T11	756398	1688	0	0
T12	6413	117	0	0
T13	11719	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	195031	0	0
GntImpliesValid_A	436370503	195031	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	195031	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	3001419	0	0
ReadyAndValidImplyGrant_A	436370503	195031	0	0
ReqAndReadyImplyGrant_A	436370503	195031	0	0
ReqImpliesValid_A	436370503	546152	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	195031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	3001419	0	0
T1	5167	55	0	0
T2	21151	422	0	0
T3	488029	5239	0	0
T7	62798	1269	0	0
T8	9222	76	0	0
T9	2312	16	0	0
T10	519251	5678	0	0
T11	756398	12584	0	0
T12	6413	102	0	0
T13	11719	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	546152	0	0
T1	5167	56	0	0
T2	21151	62	0	0
T3	488029	306	0	0
T7	62798	225	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	944	0	0
T11	756398	9216	0	0
T12	6413	125	0	0
T13	11719	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	195031	0	0
T1	5167	55	0	0
T2	21151	52	0	0
T3	488029	19	0	0
T7	62798	164	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	768	0	0
T11	756398	2254	0	0
T12	6413	113	0	0
T13	11719	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	197574	0	0
GntImpliesValid_A	436370503	197574	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	197574	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2977567	0	0
ReadyAndValidImplyGrant_A	436370503	197574	0	0
ReqAndReadyImplyGrant_A	436370503	197574	0	0
ReqImpliesValid_A	436370503	580031	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	197574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2977567	0	0
T1	5167	56	0	0
T2	21151	478	0	0
T3	488029	6157	0	0
T7	62798	1132	0	0
T8	9222	57	0	0
T9	2312	11	0	0
T10	519251	9292	0	0
T11	756398	17278	0	0
T12	6413	122	0	0
T13	11719	107	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	580031	0	0
T1	5167	63	0	0
T2	21151	89	0	0
T3	488029	69	0	0
T7	62798	236	0	0
T8	9222	56	0	0
T9	2312	12	0	0
T10	519251	2715	0	0
T11	756398	7510	0	0
T12	6413	139	0	0
T13	11719	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197574	0	0
T1	5167	59	0	0
T2	21151	65	0	0
T3	488029	18	0	0
T7	62798	156	0	0
T8	9222	56	0	0
T9	2312	11	0	0
T10	519251	1290	0	0
T11	756398	3269	0	0
T12	6413	130	0	0
T13	11719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	210351	0	0
GntImpliesValid_A	436370503	210351	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	210351	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2997045	0	0
ReadyAndValidImplyGrant_A	436370503	210351	0	0
ReqAndReadyImplyGrant_A	436370503	210351	0	0
ReqImpliesValid_A	436370503	565568	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	210351	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2997045	0	0
T1	5167	56	0	0
T2	21151	462	0	0
T3	488029	4754	0	0
T7	62798	980	0	0
T8	9222	70	0	0
T9	2312	15	0	0
T10	519251	5863	0	0
T11	756398	9192	0	0
T12	6413	106	0	0
T13	11719	163	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	565568	0	0
T1	5167	61	0	0
T2	21151	88	0	0
T3	488029	16	0	0
T7	62798	236	0	0
T8	9222	71	0	0
T9	2312	14	0	0
T10	519251	954	0	0
T11	756398	1411	0	0
T12	6413	117	0	0
T13	11719	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	210351	0	0
T1	5167	58	0	0
T2	21151	70	0	0
T3	488029	16	0	0
T7	62798	133	0	0
T8	9222	70	0	0
T9	2312	14	0	0
T10	519251	800	0	0
T11	756398	1210	0	0
T12	6413	111	0	0
T13	11719	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	204962	0	0
GntImpliesValid_A	436370503	204962	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	204962	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	3016900	0	0
ReadyAndValidImplyGrant_A	436370503	204962	0	0
ReqAndReadyImplyGrant_A	436370503	204962	0	0
ReqImpliesValid_A	436370503	599960	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	204962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	3016900	0	0
T1	5167	46	0	0
T2	21151	472	0	0
T3	488029	6567	0	0
T7	62798	1291	0	0
T8	9222	67	0	0
T9	2312	12	0	0
T10	519251	8332	0	0
T11	756398	20662	0	0
T12	6413	108	0	0
T13	11719	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	599960	0	0
T1	5167	47	0	0
T2	21151	88	0	0
T3	488029	23	0	0
T7	62798	263	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	3174	0	0
T11	756398	12602	0	0
T12	6413	115	0	0
T13	11719	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	204962	0	0
T1	5167	46	0	0
T2	21151	69	0	0
T3	488029	23	0	0
T7	62798	179	0	0
T8	9222	66	0	0
T9	2312	11	0	0
T10	519251	1235	0	0
T11	756398	3398	0	0
T12	6413	111	0	0
T13	11719	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	197034	0	0
GntImpliesValid_A	436370503	197034	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	197034	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2978763	0	0
ReadyAndValidImplyGrant_A	436370503	197034	0	0
ReqAndReadyImplyGrant_A	436370503	197034	0	0
ReqImpliesValid_A	436370503	541254	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	197034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2978763	0	0
T1	5167	63	0	0
T2	21151	437	0	0
T3	488029	1779	0	0
T7	62798	1292	0	0
T8	9222	54	0	0
T9	2312	19	0	0
T10	519251	8510	0	0
T11	756398	9718	0	0
T12	6413	120	0	0
T13	11719	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	541254	0	0
T1	5167	68	0	0
T2	21151	57	0	0
T3	488029	7	0	0
T7	62798	256	0	0
T8	9222	53	0	0
T9	2312	20	0	0
T10	519251	2057	0	0
T11	756398	1535	0	0
T12	6413	141	0	0
T13	11719	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	197034	0	0
T1	5167	65	0	0
T2	21151	52	0	0
T3	488029	7	0	0
T7	62798	173	0	0
T8	9222	53	0	0
T9	2312	19	0	0
T10	519251	1277	0	0
T11	756398	1275	0	0
T12	6413	130	0	0
T13	11719	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	205257	0	0
GntImpliesValid_A	436370503	205257	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	205257	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2965883	0	0
ReadyAndValidImplyGrant_A	436370503	205257	0	0
ReqAndReadyImplyGrant_A	436370503	205257	0	0
ReqImpliesValid_A	436370503	577419	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	205257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2965883	0	0
T1	5167	55	0	0
T2	21151	397	0	0
T3	488029	2276	0	0
T7	62798	1110	0	0
T8	9222	64	0	0
T9	2312	9	0	0
T10	519251	9134	0	0
T11	756398	9025	0	0
T12	6413	104	0	0
T13	11719	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	577419	0	0
T1	5167	56	0	0
T2	21151	79	0	0
T3	488029	10	0	0
T7	62798	207	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1950	0	0
T11	756398	6684	0	0
T12	6413	125	0	0
T13	11719	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	205257	0	0
T1	5167	55	0	0
T2	21151	56	0	0
T3	488029	10	0	0
T7	62798	145	0	0
T8	9222	63	0	0
T9	2312	8	0	0
T10	519251	1232	0	0
T11	756398	1647	0	0
T12	6413	114	0	0
T13	11719	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	193968	0	0
GntImpliesValid_A	436370503	193968	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	193968	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2985854	0	0
ReadyAndValidImplyGrant_A	436370503	193968	0	0
ReqAndReadyImplyGrant_A	436370503	193968	0	0
ReqImpliesValid_A	436370503	524014	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	193968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2985854	0	0
T1	5167	47	0	0
T2	21151	372	0	0
T3	488029	5284	0	0
T7	62798	1238	0	0
T8	9222	74	0	0
T9	2312	11	0	0
T10	519251	8144	0	0
T11	756398	12166	0	0
T12	6413	122	0	0
T13	11719	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	524014	0	0
T1	5167	48	0	0
T2	21151	95	0	0
T3	488029	492	0	0
T7	62798	240	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1906	0	0
T11	756398	9462	0	0
T12	6413	129	0	0
T13	11719	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	193968	0	0
T1	5167	47	0	0
T2	21151	56	0	0
T3	488029	14	0	0
T7	62798	170	0	0
T8	9222	73	0	0
T9	2312	10	0	0
T10	519251	1245	0	0
T11	756398	2255	0	0
T12	6413	125	0	0
T13	11719	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	199993	0	0
GntImpliesValid_A	436370503	199993	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	199993	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2943315	0	0
ReadyAndValidImplyGrant_A	436370503	199993	0	0
ReqAndReadyImplyGrant_A	436370503	199993	0	0
ReqImpliesValid_A	436370503	579708	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	199993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2943315	0	0
T1	5167	47	0	0
T2	21151	442	0	0
T3	488029	9907	0	0
T7	62798	1175	0	0
T8	9222	76	0	0
T9	2312	14	0	0
T10	519251	6296	0	0
T11	756398	11862	0	0
T12	6413	108	0	0
T13	11719	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	579708	0	0
T1	5167	50	0	0
T2	21151	85	0	0
T3	488029	748	0	0
T7	62798	210	0	0
T8	9222	75	0	0
T9	2312	17	0	0
T10	519251	957	0	0
T11	756398	2877	0	0
T12	6413	117	0	0
T13	11719	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199993	0	0
T1	5167	48	0	0
T2	21151	59	0	0
T3	488029	23	0	0
T7	62798	158	0	0
T8	9222	75	0	0
T9	2312	15	0	0
T10	519251	847	0	0
T11	756398	1632	0	0
T12	6413	112	0	0
T13	11719	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	226884	0	0
GntImpliesValid_A	436370503	226884	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	226884	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	3060972	0	0
ReadyAndValidImplyGrant_A	436370503	226884	0	0
ReqAndReadyImplyGrant_A	436370503	226884	0	0
ReqImpliesValid_A	436370503	609531	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	226884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	3060972	0	0
T1	5167	93	0	0
T2	21151	364	0	0
T3	488029	7456	0	0
T7	62798	1341	0	0
T8	9222	76	0	0
T9	2312	15	0	0
T10	519251	11576	0	0
T11	756398	11425	0	0
T12	6413	108	0	0
T13	11719	91	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	609531	0	0
T1	5167	104	0	0
T2	21151	63	0	0
T3	488029	103	0	0
T7	62798	236	0	0
T8	9222	77	0	0
T9	2312	20	0	0
T10	519251	3456	0	0
T11	756398	5999	0	0
T12	6413	121	0	0
T13	11719	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	226884	0	0
T1	5167	98	0	0
T2	21151	54	0	0
T3	488029	23	0	0
T7	62798	176	0	0
T8	9222	76	0	0
T9	2312	17	0	0
T10	519251	1877	0	0
T11	756398	1876	0	0
T12	6413	114	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	209620	0	0
GntImpliesValid_A	436370503	209620	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	209620	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2982462	0	0
ReadyAndValidImplyGrant_A	436370503	209620	0	0
ReqAndReadyImplyGrant_A	436370503	209620	0	0
ReqImpliesValid_A	436370503	588308	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	209620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2982462	0	0
T1	5167	47	0	0
T2	21151	422	0	0
T3	488029	4552	0	0
T7	62798	1083	0	0
T8	9222	64	0	0
T9	2312	17	0	0
T10	519251	7594	0	0
T11	756398	12905	0	0
T12	6413	119	0	0
T13	11719	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	588308	0	0
T1	5167	58	0	0
T2	21151	80	0	0
T3	488029	25	0	0
T7	62798	226	0	0
T8	9222	65	0	0
T9	2312	22	0	0
T10	519251	2430	0	0
T11	756398	4127	0	0
T12	6413	122	0	0
T13	11719	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	209620	0	0
T1	5167	52	0	0
T2	21151	60	0	0
T3	488029	16	0	0
T7	62798	163	0	0
T8	9222	64	0	0
T9	2312	19	0	0
T10	519251	1273	0	0
T11	756398	2098	0	0
T12	6413	120	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	200891	0	0
GntImpliesValid_A	436370503	200891	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	200891	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	3036154	0	0
ReadyAndValidImplyGrant_A	436370503	200891	0	0
ReqAndReadyImplyGrant_A	436370503	200891	0	0
ReqImpliesValid_A	436370503	558342	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	200891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	3036154	0	0
T1	5167	45	0	0
T2	21151	468	0	0
T3	488029	2415	0	0
T7	62798	1335	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	9004	0	0
T11	756398	11572	0	0
T12	6413	127	0	0
T13	11719	108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	558342	0	0
T1	5167	50	0	0
T2	21151	74	0	0
T3	488029	10	0	0
T7	62798	229	0	0
T8	9222	94	0	0
T9	2312	13	0	0
T10	519251	2180	0	0
T11	756398	8243	0	0
T12	6413	150	0	0
T13	11719	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	200891	0	0
T1	5167	47	0	0
T2	21151	63	0	0
T3	488029	10	0	0
T7	62798	181	0	0
T8	9222	93	0	0
T9	2312	12	0	0
T10	519251	1278	0	0
T11	756398	2041	0	0
T12	6413	138	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	212528	0	0
GntImpliesValid_A	436370503	212528	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	212528	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2983076	0	0
ReadyAndValidImplyGrant_A	436370503	212528	0	0
ReqAndReadyImplyGrant_A	436370503	212528	0	0
ReqImpliesValid_A	436370503	590379	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	212528	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2983076	0	0
T1	5167	56	0	0
T2	21151	474	0	0
T3	488029	7781	0	0
T7	62798	1245	0	0
T8	9222	72	0	0
T9	2312	9	0	0
T10	519251	5606	0	0
T11	756398	11808	0	0
T12	6413	109	0	0
T13	11719	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	590379	0	0
T1	5167	61	0	0
T2	21151	75	0	0
T3	488029	833	0	0
T7	62798	213	0	0
T8	9222	71	0	0
T9	2312	10	0	0
T10	519251	914	0	0
T11	756398	4578	0	0
T12	6413	116	0	0
T13	11719	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	212528	0	0
T1	5167	58	0	0
T2	21151	62	0	0
T3	488029	22	0	0
T7	62798	162	0	0
T8	9222	71	0	0
T9	2312	9	0	0
T10	519251	759	0	0
T11	756398	2144	0	0
T12	6413	112	0	0
T13	11719	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	199838	0	0
GntImpliesValid_A	436370503	199838	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	199838	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2932711	0	0
ReadyAndValidImplyGrant_A	436370503	199838	0	0
ReqAndReadyImplyGrant_A	436370503	199838	0	0
ReqImpliesValid_A	436370503	535361	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	199838	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2932711	0	0
T1	5167	50	0	0
T2	21151	521	0	0
T3	488029	5513	0	0
T7	62798	1156	0	0
T8	9222	68	0	0
T9	2312	17	0	0
T10	519251	9322	0	0
T11	756398	16761	0	0
T12	6413	115	0	0
T13	11719	103	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	535361	0	0
T1	5167	49	0	0
T2	21151	88	0	0
T3	488029	18	0	0
T7	62798	186	0	0
T8	9222	67	0	0
T9	2312	20	0	0
T10	519251	6972	0	0
T11	756398	8012	0	0
T12	6413	128	0	0
T13	11719	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	199838	0	0
T1	5167	49	0	0
T2	21151	69	0	0
T3	488029	18	0	0
T7	62798	161	0	0
T8	9222	67	0	0
T9	2312	18	0	0
T10	519251	1677	0	0
T11	756398	3243	0	0
T12	6413	121	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	203270	0	0
GntImpliesValid_A	436370503	203270	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	203270	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	2943298	0	0
ReadyAndValidImplyGrant_A	436370503	203270	0	0
ReqAndReadyImplyGrant_A	436370503	203270	0	0
ReqImpliesValid_A	436370503	566969	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	0	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	203270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2943298	0	0
T1	5167	51	0	0
T2	21151	453	0	0
T3	488029	6602	0	0
T7	62798	1114	0	0
T8	9222	65	0	0
T9	2312	10	0	0
T10	519251	9290	0	0
T11	756398	10005	0	0
T12	6413	112	0	0
T13	11719	81	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	566969	0	0
T1	5167	54	0	0
T2	21151	82	0	0
T3	488029	134	0	0
T7	62798	223	0	0
T8	9222	64	0	0
T9	2312	11	0	0
T10	519251	2970	0	0
T11	756398	6650	0	0
T12	6413	127	0	0
T13	11719	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	203270	0	0
T1	5167	52	0	0
T2	21151	53	0	0
T3	488029	14	0	0
T7	62798	160	0	0
T8	9222	64	0	0
T9	2312	10	0	0
T10	519251	1283	0	0
T11	756398	1740	0	0
T12	6413	119	0	0
T13	11719	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	808032	0	0
GntImpliesValid_A	436370503	808032	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	808032	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	11469562	0	0
ReadyAndValidImplyGrant_A	436370503	808032	0	0
ReqAndReadyImplyGrant_A	436370503	808032	0	0
ReqImpliesValid_A	436370503	2267352	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	14456	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	808032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	11469562	0	0
T1	5167	1	0	0
T2	21151	1522	0	0
T3	488029	13127	0	0
T7	62798	4318	0	0
T8	9222	1	0	0
T9	2312	1	0	0
T10	519251	30885	0	0
T11	756398	50080	0	0
T12	6413	1	0	0
T13	11719	376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	2267352	0	0
T1	5167	237	0	0
T2	21151	336	0	0
T3	488029	1157	0	0
T7	62798	1025	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	14956	0	0
T11	756398	19782	0	0
T12	6413	466	0	0
T13	11719	96	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	14456	0	900
T1	5167	2	0	1
T2	21151	0	0	1
T3	488029	0	0	1
T7	62798	0	0	1
T8	9222	3	0	1
T9	2312	0	0	1
T10	519251	17	0	1
T11	756398	16	0	1
T12	6413	13	0	1
T13	11719	0	0	1
T14	0	68	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	20	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	808032	0	0
T1	5167	237	0	0
T2	21151	222	0	0
T3	488029	54	0	0
T7	62798	648	0	0
T8	9222	284	0	0
T9	2312	49	0	0
T10	519251	5364	0	0
T11	756398	8319	0	0
T12	6413	466	0	0
T13	11719	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	436370503	436252659	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	436370503	812516	0	0
GntImpliesValid_A	436370503	812516	0	0
GrantKnown_A	436370503	436252659	0	0
IdxKnown_A	436370503	436252659	0	0
IndexIsCorrect_A	436370503	812516	0	0
LockArbDecision_A	436370503	0	0	0
NoReadyValidNoGrant_A	436370503	367214847	0	0
ReadyAndValidImplyGrant_A	436370503	812516	0	0
ReqAndReadyImplyGrant_A	436370503	812516	0	0
ReqImpliesValid_A	436370503	13198945	0	0
ReqStaysHighUntilGranted0_M	436370503	0	0	0
RoundRobin_A	436370503	26239	0	900
ValidKnown_A	436370503	436252659	0	0
gen_data_port_assertion.DataFlow_A	436370503	812516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	367214847	0	0
T1	5167	1	0	0
T2	21151	17600	0	0
T3	488029	472393	0	0
T7	62798	52324	0	0
T8	9222	1	0	0
T9	2312	1	0	0
T10	519251	433506	0	0
T11	756398	624734	0	0
T12	6413	1	0	0
T13	11719	10134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	13198945	0	0
T1	5167	221	0	0
T2	21151	1843	0	0
T3	488029	10622	0	0
T7	62798	5326	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	43677	0	0
T11	756398	70359	0	0
T12	6413	470	0	0
T13	11719	566	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	26239	0	900
T1	5167	1	0	1
T2	21151	0	0	1
T3	488029	0	0	1
T7	62798	0	0	1
T8	9222	4	0	1
T9	2312	0	0	1
T10	519251	8	0	1
T11	756398	37	0	1
T12	6413	4	0	1
T13	11719	0	0	1
T14	0	127	0	0
T16	0	8	0	0
T17	0	11	0	0
T18	0	7	0	0
T19	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	436252659	0	0
T1	5167	5127	0	0
T2	21151	21137	0	0
T3	488029	487992	0	0
T7	62798	62713	0	0
T8	9222	9178	0	0
T9	2312	2274	0	0
T10	519251	519099	0	0
T11	756398	755491	0	0
T12	6413	6401	0	0
T13	11719	11707	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436370503	812516	0	0
T1	5167	221	0	0
T2	21151	221	0	0
T3	488029	33	0	0
T7	62798	665	0	0
T8	9222	297	0	0
T9	2312	47	0	0
T10	519251	5253	0	0
T11	756398	8362	0	0
T12	6413	470	0	0
T13	11719	67	0	0