Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1565550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249043

1

T1

22

T2

258

T3

317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	615453	1			T1	28		T2	585		T3	746
values[0x0]	582424	1			T1	41		T2	611		T3	708
values[0x1]	616716	1			T1	32		T2	622		T3	763

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1209699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

604894

1

T1

36

T2

602

T3

751

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28153	1			T2	59		T3	37		T7	26
valid_sources[0x01]	27829	1			T1	1		T2	44		T3	34
valid_sources[0x02]	27443	1			T1	3		T2	11		T3	33
valid_sources[0x03]	28498	1			T2	13		T3	33		T6	1
valid_sources[0x04]	28382	1			T1	1		T2	31		T3	34
valid_sources[0x05]	28272	1			T1	1		T2	27		T3	42
valid_sources[0x06]	28744	1			T1	2		T2	40		T3	35
valid_sources[0x07]	28344	1			T1	4		T2	36		T3	36
valid_sources[0x08]	29932	1			T1	1		T2	28		T3	32
valid_sources[0x09]	28758	1			T2	39		T3	39		T6	1
valid_sources[0x0a]	27430	1			T1	5		T2	19		T3	40
valid_sources[0x0b]	28313	1			T2	14		T3	16		T6	2
valid_sources[0x0c]	28250	1			T1	1		T2	43		T3	44
valid_sources[0x0d]	27216	1			T1	1		T2	33		T3	51
valid_sources[0x0e]	29216	1			T1	5		T2	47		T3	22
valid_sources[0x0f]	28416	1			T1	2		T2	39		T3	24
valid_sources[0x10]	29743	1			T1	2		T2	62		T3	38
valid_sources[0x11]	28760	1			T1	1		T2	24		T3	39
valid_sources[0x12]	28879	1			T1	1		T2	18		T3	27
valid_sources[0x13]	28617	1			T2	49		T3	30		T7	26
valid_sources[0x14]	29020	1			T1	1		T2	29		T3	31
valid_sources[0x15]	28546	1			T1	1		T2	35		T3	37
valid_sources[0x16]	27848	1			T1	1		T2	26		T3	33
valid_sources[0x17]	27377	1			T1	3		T2	14		T3	43
valid_sources[0x18]	27791	1			T1	3		T2	26		T3	38
valid_sources[0x19]	28586	1			T1	1		T2	14		T3	32
valid_sources[0x1a]	26970	1			T1	3		T2	8		T3	27
valid_sources[0x1b]	28444	1			T2	33		T3	46		T7	12
valid_sources[0x1c]	28630	1			T2	16		T3	29		T6	2
valid_sources[0x1d]	27800	1			T1	2		T2	35		T3	24
valid_sources[0x1e]	28812	1			T1	1		T2	10		T3	31
valid_sources[0x1f]	28953	1			T1	2		T2	2		T3	26
valid_sources[0x20]	29178	1			T2	14		T3	30		T7	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26303

1

T1

2

T2

23

T3

33

values[0x0]

all_enables

biggest_size

196510

1

T1

18

T2

206

T3

256

values[0x1]

all_enables

biggest_size

26230

1

T1

2

T2

29

T3

28

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1577985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257332

1

T1

18

T2

219

T3

294

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627392	1			T1	37		T2	508		T3	727
values[0x0]	578261	1			T1	40		T2	534		T3	705
values[0x1]	629664	1			T1	44		T2	528		T3	750

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1211641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623676

1

T1

37

T2

510

T3

718

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29672	1			T2	32		T3	40		T6	1
valid_sources[0x01]	28596	1			T2	26		T3	30		T7	36
valid_sources[0x02]	28507	1			T2	13		T3	29		T6	2
valid_sources[0x03]	28819	1			T1	5		T2	36		T3	38
valid_sources[0x04]	28736	1			T1	7		T2	23		T3	51
valid_sources[0x05]	28976	1			T2	25		T3	26		T6	1
valid_sources[0x06]	28564	1			T2	32		T3	31		T6	3
valid_sources[0x07]	29066	1			T2	22		T3	41		T6	2
valid_sources[0x08]	28770	1			T2	24		T3	33		T6	1
valid_sources[0x09]	28708	1			T2	35		T3	54		T6	3
valid_sources[0x0a]	28123	1			T2	26		T3	31		T6	1
valid_sources[0x0b]	28260	1			T2	27		T3	30		T7	22
valid_sources[0x0c]	28910	1			T1	1		T2	47		T3	29
valid_sources[0x0d]	27753	1			T2	18		T3	18		T6	1
valid_sources[0x0e]	28859	1			T2	22		T3	31		T6	1
valid_sources[0x0f]	28687	1			T2	12		T3	30		T6	1
valid_sources[0x10]	29037	1			T1	7		T2	37		T3	38
valid_sources[0x11]	28473	1			T2	24		T3	28		T6	1
valid_sources[0x12]	29586	1			T1	10		T2	25		T3	46
valid_sources[0x13]	28512	1			T2	17		T3	24		T6	1
valid_sources[0x14]	29727	1			T2	14		T3	42		T7	20
valid_sources[0x15]	28833	1			T2	52		T3	27		T6	1
valid_sources[0x16]	28966	1			T2	17		T3	35		T6	1
valid_sources[0x17]	27819	1			T1	3		T2	25		T3	38
valid_sources[0x18]	28830	1			T1	5		T2	21		T3	37
valid_sources[0x19]	29578	1			T2	27		T3	52		T6	3
valid_sources[0x1a]	28000	1			T2	28		T3	37		T7	12
valid_sources[0x1b]	28277	1			T2	5		T3	28		T6	4
valid_sources[0x1c]	28930	1			T1	4		T2	37		T3	23
valid_sources[0x1d]	28629	1			T1	6		T2	12		T3	32
valid_sources[0x1e]	29314	1			T2	26		T3	33		T6	4
valid_sources[0x1f]	28615	1			T2	19		T3	25		T6	3
valid_sources[0x20]	28709	1			T2	32		T3	30		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26886

1

T2

19

T3

29

T6

2

values[0x0]

all_enables

biggest_size

203307

1

T1

15

T2

184

T3

244

values[0x1]

all_enables

biggest_size

27139

1

T1

3

T2

16

T3

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1576779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251142

1

T1

18

T2

223

T3

309

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	620151	1			T1	34		T2	519		T3	816
values[0x0]	587756	1			T1	45		T2	531		T3	788
values[0x1]	620014	1			T1	37		T2	552		T3	774

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1218615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

609306

1

T1

45

T2

521

T3

789

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28468	1			T1	2		T2	28		T3	44
valid_sources[0x01]	28374	1			T1	1		T2	22		T3	32
valid_sources[0x02]	28480	1			T2	29		T3	35		T7	31
valid_sources[0x03]	28624	1			T1	1		T2	14		T3	35
valid_sources[0x04]	28888	1			T1	1		T3	39		T6	6
valid_sources[0x05]	28682	1			T1	1		T2	18		T3	34
valid_sources[0x06]	29061	1			T1	2		T2	16		T3	45
valid_sources[0x07]	28580	1			T1	4		T2	12		T3	45
valid_sources[0x08]	29478	1			T1	3		T2	76		T3	29
valid_sources[0x09]	29242	1			T1	2		T3	28		T6	5
valid_sources[0x0a]	28097	1			T1	2		T2	31		T3	41
valid_sources[0x0b]	28367	1			T1	4		T2	26		T3	46
valid_sources[0x0c]	29062	1			T1	1		T2	16		T3	42
valid_sources[0x0d]	28199	1			T1	3		T2	51		T3	33
valid_sources[0x0e]	28918	1			T2	56		T3	51		T6	1
valid_sources[0x0f]	28471	1			T1	1		T2	30		T3	35
valid_sources[0x10]	28460	1			T2	7		T3	41		T6	10
valid_sources[0x11]	28132	1			T1	3		T2	11		T3	40
valid_sources[0x12]	27767	1			T1	1		T2	40		T3	37
valid_sources[0x13]	28299	1			T1	1		T2	7		T3	36
valid_sources[0x14]	28852	1			T1	1		T2	46		T3	40
valid_sources[0x15]	28240	1			T2	5		T3	41		T6	4
valid_sources[0x16]	28068	1			T1	1		T2	54		T3	34
valid_sources[0x17]	27818	1			T1	1		T2	23		T3	35
valid_sources[0x18]	29014	1			T1	2		T2	30		T3	36
valid_sources[0x19]	28773	1			T1	2		T2	30		T3	42
valid_sources[0x1a]	27961	1			T1	3		T2	27		T3	39
valid_sources[0x1b]	29495	1			T1	4		T2	24		T3	38
valid_sources[0x1c]	28368	1			T1	2		T2	25		T3	33
valid_sources[0x1d]	28598	1			T1	1		T2	34		T3	39
valid_sources[0x1e]	28422	1			T1	1		T2	36		T3	40
valid_sources[0x1f]	28723	1			T1	8		T2	27		T3	36
valid_sources[0x20]	28358	1			T1	3		T2	12		T3	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26482

1

T1

4

T2

16

T3

25

values[0x0]

all_enables

biggest_size

197995

1

T1

12

T2

179

T3

256

values[0x1]

all_enables

biggest_size

26665

1

T1

2

T2

28

T3

28