Unified Coverage Report :: Group :: tl_agent_pkg::tl_d_chan_cov_cg

Group : tl_agent_pkg::tl_d_chan_cov_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

24 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	1	0	1	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error	2	0	2	100.00	100	1	1	2
cp_opcode	1	0	1	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_d_chan_cov_cg_cc	1	0	1	100.00	100	1	1	0

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144177

1

T1

11

T2

69

T3

68

auto[1]

69845

1

T1

1

T2

82

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54270

1

T1

6

T2

58

T3

35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150816	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63206

1

T1

5

T2

48

T3

29

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16723

1

T1

4

T2

17

T3

11

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158224

1

T2

89

T3

53

T6

2

auto[1]

82257

1

T1

6

T2

68

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

60461

1

T1

1

T2

51

T3

27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	169543	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

70938

1

T1

1

T2

40

T3

24

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18623

1

T2

18

T3

2

T10

17

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139438

1

T1

8

T2

110

T3

64

auto[1]

81815

1

T1

1

T2

16

T3

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

57518

1

T1

1

T2

47

T3

44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154716	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66537

1

T2

43

T3

43

T6

7

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18324

1

T2

19

T3

16

T6

3

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148430

1

T1

11

T2

86

T3

59

auto[1]

74919

1

T2

70

T3

49

T8

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54853

1

T1

5

T2

51

T3

34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66028

1

T1

4

T2

50

T3

36

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17133

1

T1

3

T2

16

T3

9

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141129

1

T1

2

T2

51

T3

71

auto[1]

77081

1

T1

12

T2

113

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53883

1

T1

3

T2

46

T3

29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64013

1

T1

6

T2

57

T3

17

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16675

1

T1

1

T2

9

T3

4

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145505

1

T1

2

T2

81

T3

65

auto[1]

79453

1

T1

3

T2

67

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

55458

1

T1

2

T2

40

T3

32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66596

1

T2

52

T3

35

T6

6

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17353

1

T2

15

T3

12

T6

3

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

581098

1

T1

21

T2

225

T3

252

auto[1]

313982

1

T1

22

T2

314

T3

116

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

225914

1

T1

14

T2

182

T3

113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	624260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

270820

1

T1

14

T2

173

T3

113

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

71464

1

T1

3

T2

54

T3

30

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149461

1

T1

9

T2

98

T3

71

auto[1]

78923

1

T1

1

T2

46

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56994

1

T1

3

T2

43

T3

21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67920

1

T1

4

T2

41

T3

22

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17865

1

T1

2

T2

12

T3

5

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145660

1

T1

5

T2

73

T3

44

auto[1]

75951

1

T1

2

T2

59

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56891

1

T1

1

T2

37

T3

24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67184

1

T1

1

T2

38

T3

40

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18000

1

T2

12

T3

8

T6

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144844

1

T1

12

T2

142

T3

43

auto[1]

83665

1

T1

1

T3

53

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56870

1

T1

1

T2

55

T3

28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67726

1

T1

6

T2

52

T3

27

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17749

1

T1

1

T2

22

T3

9

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147337

1

T1

7

T2

47

T3

53

auto[1]

77467

1

T1

2

T2

98

T3

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

57158

1

T1

3

T2

40

T3

41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68290

1

T1

5

T2

47

T3

36

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18113

1

T2

15

T3

16

T6

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153143

1

T1

5

T2

68

T3

74

auto[1]

77226

1

T1

7

T2

76

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

57565

1

T1

5

T2

59

T3

30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69413

1

T1

5

T2

50

T3

28

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18212

1

T1

3

T2

20

T3

10

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138711

1

T1

7

T2

104

T3

62

auto[1]

76376

1

T2

21

T3

35

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

54318

1

T1

2

T2

44

T3

33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149836	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65251

1

T1

4

T2

38

T3

33

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17287

1

T1

1

T2

10

T3

9

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137968

1

T1

7

T2

136

T3

89

auto[1]

72857

1

T1

1

T2

11

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

52822

1

T1

4

T2

46

T3

27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62287

1

T1

3

T2

56

T3

28

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16603

1

T1

1

T2

21

T3

6

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603147

1

T1

20

T2

243

T3

241

auto[1]

283247

1

T1

18

T2

286

T3

124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

224317

1

T1

10

T2

179

T3

120

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	617686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

268708

1

T1

11

T2

161

T3

120

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

70778

1

T2

52

T3

38

T6

3

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147188

1

T1

7

T2

103

T3

100

auto[1]

74843

1

T1

2

T2

29

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

55230

1

T1

1

T2

33

T3

44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65865

1

T1

4

T2

37

T3

32

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17184

1

T2

12

T3

11

T8

52

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600106

1

T1

42

T2

265

T3

180

auto[1]

297871

1

T1

3

T2

281

T3

188

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

227242

1

T1

15

T2

188

T3

127

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	626137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

271840

1

T1

14

T2

180

T3

131

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

71879

1

T1

7

T2

61

T3

52

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141760

1

T1

2

T2

68

T3

42

auto[1]

86225

1

T1

5

T2

88

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

57281

1

T1

4

T2

50

T3

28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67497

1

T1

3

T2

57

T3

28

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17896

1

T1

3

T2

19

T3

7

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165011

1

T1

1

T2

119

T3

92

auto[1]

85086

1

T1

2

T2

6

T3

83

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

64467

1

T2

30

T3

63

T6

1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

76505

1

T1

1

T2

32

T3

49

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

20520

1

T2

7

T3

16

T8

126

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156528

1

T1

4

T2

138

T3

56

auto[1]

77715

1

T1

3

T2

3

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

59461

1

T1

1

T2

38

T3

26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69393

1

T1

4

T2

46

T3

29

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

18442

1

T2

11

T3

11

T6

2

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139762

1

T1

5

T2

149

T3

84

auto[1]

74848

1

T1

5

T2

7

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53949

1

T1

5

T2

50

T3

46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63686

1

T1

4

T2

57

T3

31

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

16719

1

T1

3

T2

15

T3

15

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577388

1

T1

19

T2

301

T3

197

auto[1]

308427

1

T1

16

T2

218

T3

169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

226686

1

T1

10

T2

162

T3

121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

269360

1

T1

13

T2

186

T3

120

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

71678

1

T1

3

T2

51

T3

47

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148881

1

T1

2

T2

121

T3

45

auto[1]

82212

1

T1

5

T2

11

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

56301

1

T1

1

T2

38

T3

28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

67886

1

T1

3

T2

47

T3

29

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17426

1

T2

7

T3

13

T6

1

Summary for Variable cp_error

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_error

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138107

1

T1

11

T2

96

T3

76

auto[1]

72966

1

T2

37

T3

5

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_opcode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

53556

1

T1

1

T2

45

T3

30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64004

1

T1

3

T2

45

T3

32

---

Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins

cp_opcode

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x1]

biggest_size

17097

1

T2

12

T3

9

T8

61