Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8061572	0	0
GntImpliesValid_A	2147483647	8061572	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8061572	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	494737060	0	0
ReadyAndValidImplyGrant_A	2147483647	8061572	0	0
ReqAndReadyImplyGrant_A	2147483647	8061572	0	0
ReqImpliesValid_A	2147483647	35756811	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45836	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8061572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9812736	9811200	0	0
T2	4287960	4287888	0	0
T3	202824	202272	0	0
T6	209664	208728	0	0
T7	1066224	1066104	0	0
T8	495528	494784	0	0
T9	57696	56304	0	0
T10	5905200	5904960	0	0
T11	223728	222720	0	0
T12	925440	924384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9812736	9811200	0	0
T2	4287960	4287888	0	0
T3	202824	202272	0	0
T6	209664	208728	0	0
T7	1066224	1066104	0	0
T8	495528	494784	0	0
T9	57696	56304	0	0
T10	5905200	5904960	0	0
T11	223728	222720	0	0
T12	925440	924384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9812736	9811200	0	0
T2	4287960	4287888	0	0
T3	202824	202272	0	0
T6	209664	208728	0	0
T7	1066224	1066104	0	0
T8	495528	494784	0	0
T9	57696	56304	0	0
T10	5905200	5904960	0	0
T11	223728	222720	0	0
T12	925440	924384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	494737060	0	0
T1	9812736	527642	0	0
T2	4287960	1604739	0	0
T3	202824	3811	0	0
T6	209664	9994	0	0
T7	1066224	50941	0	0
T8	495528	1571	0	0
T9	57696	679	0	0
T10	5905200	244925	0	0
T11	223728	4826	0	0
T12	925440	21926	0	0
T13	0	396	0	0
T14	0	117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35756811	0	0
T1	9812736	18485	0	0
T2	4287960	271250	0	0
T3	202824	3767	0	0
T6	209664	850	0	0
T7	1066224	31960	0	0
T8	495528	24070	0	0
T9	57696	516	0	0
T10	5905200	12604	0	0
T11	223728	3702	0	0
T12	925440	26444	0	0
T13	0	268	0	0
T14	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45836	0	21600
T2	178665	1	0	1
T3	16902	13	0	2
T6	17472	0	0	2
T7	88852	0	0	2
T8	41294	413	0	2
T9	4808	0	0	2
T10	492100	0	0	2
T11	18644	9	0	2
T12	77120	65	0	2
T13	557124	0	0	2
T14	196441	0	0	1
T15	0	11	0	0
T16	0	1	0	0
T17	0	13	0	0
T18	0	219	0	0
T19	0	8	0	0
T20	0	600	0	0
T21	0	7	0	0
T22	0	15	0	0
T23	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9812736	9811200	0	0
T2	4287960	4287888	0	0
T3	202824	202272	0	0
T6	209664	208728	0	0
T7	1066224	1066104	0	0
T8	495528	494784	0	0
T9	57696	56304	0	0
T10	5905200	5904960	0	0
T11	223728	222720	0	0
T12	925440	924384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8061572	0	0
T1	9812736	338	0	0
T2	4287960	4989	0	0
T3	202824	3444	0	0
T6	209664	327	0	0
T7	1066224	4559	0	0
T8	495528	11511	0	0
T9	57696	461	0	0
T10	5905200	7205	0	0
T11	223728	3324	0	0
T12	925440	21435	0	0
T13	0	204	0	0
T14	0	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	898163	0	0
GntImpliesValid_A	459196709	898163	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	898163	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	12435332	0	0
ReadyAndValidImplyGrant_A	459196709	898163	0	0
ReqAndReadyImplyGrant_A	459196709	898163	0	0
ReqImpliesValid_A	459196709	2557032	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	898163	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	12435332	0	0
T1	408864	17034	0	0
T2	178665	155740	0	0
T3	8451	309	0	0
T6	8736	221	0	0
T7	44426	3769	0	0
T8	20647	666	0	0
T9	2404	49	0	0
T10	246050	3245	0	0
T11	9322	305	0	0
T12	38560	1802	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	2557032	0	0
T1	408864	1675	0	0
T2	178665	20698	0	0
T3	8451	428	0	0
T6	8736	39	0	0
T7	44426	7958	0	0
T8	20647	1149	0	0
T9	2404	58	0	0
T10	246050	1061	0	0
T11	9322	420	0	0
T12	38560	2680	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	898163	0	0
T1	408864	45	0	0
T2	178665	546	0	0
T3	8451	368	0	0
T6	8736	30	0	0
T7	44426	1113	0	0
T8	20647	907	0	0
T9	2404	53	0	0
T10	246050	797	0	0
T11	9322	362	0	0
T12	38560	2239	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	895446	0	0
GntImpliesValid_A	459196709	895446	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	895446	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	12490386	0	0
ReadyAndValidImplyGrant_A	459196709	895446	0	0
ReqAndReadyImplyGrant_A	459196709	895446	0	0
ReqImpliesValid_A	459196709	2581469	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	895446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	12490386	0	0
T1	408864	12785	0	0
T2	178665	180234	0	0
T3	8451	323	0	0
T6	8736	209	0	0
T7	44426	2037	0	0
T8	20647	673	0	0
T9	2404	42	0	0
T10	246050	3048	0	0
T11	9322	276	0	0
T12	38560	1755	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	2581469	0	0
T1	408864	787	0	0
T2	178665	17538	0	0
T3	8451	414	0	0
T6	8736	40	0	0
T7	44426	495	0	0
T8	20647	1156	0	0
T9	2404	57	0	0
T10	246050	965	0	0
T11	9322	377	0	0
T12	38560	2553	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	895446	0	0
T1	408864	43	0	0
T2	178665	539	0	0
T3	8451	368	0	0
T6	8736	27	0	0
T7	44426	295	0	0
T8	20647	914	0	0
T9	2404	49	0	0
T10	246050	760	0	0
T11	9322	326	0	0
T12	38560	2152	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	210887	0	0
GntImpliesValid_A	459196709	210887	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	210887	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3023945	0	0
ReadyAndValidImplyGrant_A	459196709	210887	0	0
ReqAndReadyImplyGrant_A	459196709	210887	0	0
ReqImpliesValid_A	459196709	575135	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	210887	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3023945	0	0
T1	408864	1731	0	0
T2	178665	50565	0	0
T3	8451	91	0	0
T6	8736	40	0	0
T7	44426	1472	0	0
T8	20647	1	0	0
T9	2404	15	0	0
T10	246050	977	0	0
T11	9322	92	0	0
T12	38560	374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	575135	0	0
T1	408864	80	0	0
T2	178665	2603	0	0
T3	8451	94	0	0
T6	8736	6	0	0
T7	44426	4745	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	296	0	0
T11	9322	93	0	0
T12	38560	384	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	210887	0	0
T1	408864	8	0	0
T2	178665	147	0	0
T3	8451	92	0	0
T6	8736	6	0	0
T7	44426	538	0	0
T8	20647	0	0	0
T9	2404	14	0	0
T10	246050	217	0	0
T11	9322	92	0	0
T12	38560	377	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	228035	0	0
GntImpliesValid_A	459196709	228035	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	228035	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3118972	0	0
ReadyAndValidImplyGrant_A	459196709	228035	0	0
ReqAndReadyImplyGrant_A	459196709	228035	0	0
ReqImpliesValid_A	459196709	634582	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	228035	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3118972	0	0
T1	408864	1294	0	0
T2	178665	56582	0	0
T3	8451	96	0	0
T6	8736	91	0	0
T7	44426	877	0	0
T8	20647	3	0	0
T9	2404	17	0	0
T10	246050	857	0	0
T11	9322	92	0	0
T12	38560	385	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	634582	0	0
T1	408864	7	0	0
T2	178665	3030	0	0
T3	8451	101	0	0
T6	8736	18	0	0
T7	44426	4533	0	0
T8	20647	918	0	0
T9	2404	16	0	0
T10	246050	249	0	0
T11	9322	99	0	0
T12	38560	395	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228035	0	0
T1	408864	7	0	0
T2	178665	156	0	0
T3	8451	98	0	0
T6	8736	15	0	0
T7	44426	484	0	0
T8	20647	460	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	95	0	0
T12	38560	388	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	215188	0	0
GntImpliesValid_A	459196709	215188	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	215188	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	5952074	0	0
ReadyAndValidImplyGrant_A	459196709	215188	0	0
ReqAndReadyImplyGrant_A	459196709	215188	0	0
ReqImpliesValid_A	459196709	1299457	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	215188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	5952074	0	0
T1	408864	2947	0	0
T2	178665	21801	0	0
T3	8451	428	0	0
T6	8736	130	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	34	0	0
T10	246050	1777	0	0
T11	9322	1199	0	0
T12	38560	1372	0	0
T13	0	130	0	0
T14	0	40	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	1299457	0	0
T1	408864	7	0	0
T2	178665	408	0	0
T3	8451	150	0	0
T6	8736	17	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	340	0	0
T11	9322	189	0	0
T12	38560	472	0	0
T13	0	13	0	0
T14	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	215188	0	0
T1	408864	7	0	0
T2	178665	125	0	0
T3	8451	97	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	7	0	0
T10	246050	193	0	0
T11	9322	92	0	0
T12	38560	411	0	0
T13	0	13	0	0
T14	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	234351	0	0
GntImpliesValid_A	459196709	234351	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	234351	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	5537083	0	0
ReadyAndValidImplyGrant_A	459196709	234351	0	0
ReqAndReadyImplyGrant_A	459196709	234351	0	0
ReqImpliesValid_A	459196709	1378435	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	234351	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	5537083	0	0
T1	408864	2463	0	0
T2	178665	14792	0	0
T3	8451	366	0	0
T6	8736	163	0	0
T7	44426	0	0	0
T8	20647	21	0	0
T9	2404	174	0	0
T10	246050	3731	0	0
T11	9322	717	0	0
T12	38560	4570	0	0
T13	0	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	1378435	0	0
T1	408864	7	0	0
T2	178665	437	0	0
T3	8451	141	0	0
T6	8736	70	0	0
T7	44426	0	0	0
T8	20647	3301	0	0
T9	2404	24	0	0
T10	246050	492	0	0
T11	9322	122	0	0
T12	38560	2273	0	0
T13	0	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	234351	0	0
T1	408864	7	0	0
T2	178665	141	0	0
T3	8451	97	0	0
T6	8736	13	0	0
T7	44426	0	0	0
T8	20647	387	0	0
T9	2404	14	0	0
T10	246050	203	0	0
T11	9322	76	0	0
T12	38560	844	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	214700	0	0
GntImpliesValid_A	459196709	214700	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	214700	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	5593483	0	0
ReadyAndValidImplyGrant_A	459196709	214700	0	0
ReqAndReadyImplyGrant_A	459196709	214700	0	0
ReqImpliesValid_A	459196709	1192146	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	214700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	5593483	0	0
T1	408864	20429	0	0
T2	178665	107461	0	0
T3	8451	448	0	0
T6	8736	206	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	123	0	0
T10	246050	2175	0	0
T11	9322	383	0	0
T12	38560	1820	0	0
T13	0	103	0	0
T14	0	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	1192146	0	0
T1	408864	1985	0	0
T2	178665	7144	0	0
T3	8451	120	0	0
T6	8736	35	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	37	0	0
T10	246050	450	0	0
T11	9322	98	0	0
T12	38560	475	0	0
T13	0	19	0	0
T14	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214700	0	0
T1	408864	10	0	0
T2	178665	156	0	0
T3	8451	93	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	18	0	0
T10	246050	225	0	0
T11	9322	69	0	0
T12	38560	403	0	0
T13	0	10	0	0
T14	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	211168	0	0
GntImpliesValid_A	459196709	211168	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	211168	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	4989682	0	0
ReadyAndValidImplyGrant_A	459196709	211168	0	0
ReqAndReadyImplyGrant_A	459196709	211168	0	0
ReqImpliesValid_A	459196709	1062280	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	211168	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	4989682	0	0
T1	408864	12275	0	0
T2	178665	23172	0	0
T3	8451	363	0	0
T6	8736	142	0	0
T7	44426	0	0	0
T8	20647	5	0	0
T9	2404	46	0	0
T10	246050	9620	0	0
T11	9322	399	0	0
T12	38560	2155	0	0
T13	0	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	1062280	0	0
T1	408864	719	0	0
T2	178665	727	0	0
T3	8451	121	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	3441	0	0
T9	2404	20	0	0
T10	246050	945	0	0
T11	9322	101	0	0
T12	38560	1920	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	211168	0	0
T1	408864	11	0	0
T2	178665	133	0	0
T3	8451	81	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	489	0	0
T9	2404	10	0	0
T10	246050	212	0	0
T11	9322	81	0	0
T12	38560	906	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	225122	0	0
GntImpliesValid_A	459196709	225122	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	225122	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3121819	0	0
ReadyAndValidImplyGrant_A	459196709	225122	0	0
ReqAndReadyImplyGrant_A	459196709	225122	0	0
ReqImpliesValid_A	459196709	582870	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	225122	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3121819	0	0
T1	408864	2432	0	0
T2	178665	49198	0	0
T3	8451	100	0	0
T6	8736	73	0	0
T7	44426	1	0	0
T8	20647	2	0	0
T9	2404	12	0	0
T10	246050	881	0	0
T11	9322	93	0	0
T12	38560	396	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	582870	0	0
T1	408864	5	0	0
T2	178665	2982	0	0
T3	8451	105	0	0
T6	8736	19	0	0
T7	44426	0	0	0
T8	20647	1103	0	0
T9	2404	11	0	0
T10	246050	249	0	0
T11	9322	108	0	0
T12	38560	432	0	0
T13	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	225122	0	0
T1	408864	5	0	0
T2	178665	148	0	0
T3	8451	102	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	552	0	0
T9	2404	11	0	0
T10	246050	216	0	0
T11	9322	100	0	0
T12	38560	412	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	228431	0	0
GntImpliesValid_A	459196709	228431	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	228431	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3080190	0	0
ReadyAndValidImplyGrant_A	459196709	228431	0	0
ReqAndReadyImplyGrant_A	459196709	228431	0	0
ReqImpliesValid_A	459196709	608144	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	228431	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3080190	0	0
T1	408864	2913	0	0
T2	178665	52564	0	0
T3	8451	77	0	0
T6	8736	84	0	0
T7	44426	1	0	0
T8	20647	22	0	0
T9	2404	7	0	0
T10	246050	853	0	0
T11	9322	87	0	0
T12	38560	386	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	608144	0	0
T1	408864	10	0	0
T2	178665	1779	0	0
T3	8451	84	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	1877	0	0
T9	2404	6	0	0
T10	246050	229	0	0
T11	9322	96	0	0
T12	38560	404	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228431	0	0
T1	408864	10	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	949	0	0
T9	2404	6	0	0
T10	246050	200	0	0
T11	9322	91	0	0
T12	38560	393	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	214079	0	0
GntImpliesValid_A	459196709	214079	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	214079	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3105136	0	0
ReadyAndValidImplyGrant_A	459196709	214079	0	0
ReqAndReadyImplyGrant_A	459196709	214079	0	0
ReqImpliesValid_A	459196709	520885	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	214079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3105136	0	0
T1	408864	4524	0	0
T2	178665	51875	0	0
T3	8451	91	0	0
T6	8736	30	0	0
T7	44426	1	0	0
T8	20647	97	0	0
T9	2404	16	0	0
T10	246050	951	0	0
T11	9322	88	0	0
T12	38560	798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	520885	0	0
T1	408864	320	0	0
T2	178665	1558	0	0
T3	8451	94	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	1956	0	0
T9	2404	15	0	0
T10	246050	273	0	0
T11	9322	91	0	0
T12	38560	1212	0	0
T13	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	214079	0	0
T1	408864	12	0	0
T2	178665	151	0	0
T3	8451	92	0	0
T6	8736	5	0	0
T7	44426	0	0	0
T8	20647	1026	0	0
T9	2404	15	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	1003	0	0
T13	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	218309	0	0
GntImpliesValid_A	459196709	218309	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	218309	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3161894	0	0
ReadyAndValidImplyGrant_A	459196709	218309	0	0
ReqAndReadyImplyGrant_A	459196709	218309	0	0
ReqImpliesValid_A	459196709	592184	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	218309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3161894	0	0
T1	408864	5642	0	0
T2	178665	56849	0	0
T3	8451	88	0	0
T6	8736	65	0	0
T7	44426	1	0	0
T8	20647	1	0	0
T9	2404	13	0	0
T10	246050	794	0	0
T11	9322	100	0	0
T12	38560	397	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	592184	0	0
T1	408864	127	0	0
T2	178665	4660	0	0
T3	8451	91	0	0
T6	8736	21	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	215	0	0
T11	9322	109	0	0
T12	38560	405	0	0
T13	0	19	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	218309	0	0
T1	408864	14	0	0
T2	178665	164	0	0
T3	8451	89	0	0
T6	8736	9	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	12	0	0
T10	246050	179	0	0
T11	9322	104	0	0
T12	38560	399	0	0
T13	0	17	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	240586	0	0
GntImpliesValid_A	459196709	240586	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	240586	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3103098	0	0
ReadyAndValidImplyGrant_A	459196709	240586	0	0
ReqAndReadyImplyGrant_A	459196709	240586	0	0
ReqImpliesValid_A	459196709	669702	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	240586	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3103098	0	0
T1	408864	2370	0	0
T2	178665	51027	0	0
T3	8451	93	0	0
T6	8736	69	0	0
T7	44426	1	0	0
T8	20647	1	0	0
T9	2404	15	0	0
T10	246050	775	0	0
T11	9322	94	0	0
T12	38560	718	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	669702	0	0
T1	408864	25	0	0
T2	178665	5711	0	0
T3	8451	96	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	216	0	0
T11	9322	111	0	0
T12	38560	1002	0	0
T13	0	11	0	0
T14	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	240586	0	0
T1	408864	6	0	0
T2	178665	157	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	15	0	0
T10	246050	193	0	0
T11	9322	102	0	0
T12	38560	858	0	0
T13	0	11	0	0
T14	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	221306	0	0
GntImpliesValid_A	459196709	221306	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	221306	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3030708	0	0
ReadyAndValidImplyGrant_A	459196709	221306	0	0
ReqAndReadyImplyGrant_A	459196709	221306	0	0
ReqImpliesValid_A	459196709	577062	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	221306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3030708	0	0
T1	408864	2861	0	0
T2	178665	37485	0	0
T3	8451	112	0	0
T6	8736	111	0	0
T7	44426	1	0	0
T8	20647	2	0	0
T9	2404	11	0	0
T10	246050	876	0	0
T11	9322	90	0	0
T12	38560	413	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	577062	0	0
T1	408864	9	0	0
T2	178665	1559	0	0
T3	8451	121	0	0
T6	8736	39	0	0
T7	44426	0	0	0
T8	20647	1077	0	0
T9	2404	10	0	0
T10	246050	314	0	0
T11	9322	97	0	0
T12	38560	419	0	0
T13	0	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221306	0	0
T1	408864	9	0	0
T2	178665	126	0	0
T3	8451	116	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	539	0	0
T9	2404	10	0	0
T10	246050	229	0	0
T11	9322	93	0	0
T12	38560	414	0	0
T13	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	223406	0	0
GntImpliesValid_A	459196709	223406	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	223406	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3108118	0	0
ReadyAndValidImplyGrant_A	459196709	223406	0	0
ReqAndReadyImplyGrant_A	459196709	223406	0	0
ReqImpliesValid_A	459196709	583759	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	223406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3108118	0	0
T1	408864	5192	0	0
T2	178665	51088	0	0
T3	8451	106	0	0
T6	8736	59	0	0
T7	44426	1	0	0
T8	20647	26	0	0
T9	2404	7	0	0
T10	246050	821	0	0
T11	9322	95	0	0
T12	38560	398	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	583759	0	0
T1	408864	11	0	0
T2	178665	2312	0	0
T3	8451	111	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	1713	0	0
T9	2404	6	0	0
T10	246050	216	0	0
T11	9322	108	0	0
T12	38560	410	0	0
T13	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	223406	0	0
T1	408864	11	0	0
T2	178665	156	0	0
T3	8451	108	0	0
T6	8736	8	0	0
T7	44426	0	0	0
T8	20647	869	0	0
T9	2404	6	0	0
T10	246050	196	0	0
T11	9322	101	0	0
T12	38560	402	0	0
T13	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	221695	0	0
GntImpliesValid_A	459196709	221695	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	221695	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3113442	0	0
ReadyAndValidImplyGrant_A	459196709	221695	0	0
ReqAndReadyImplyGrant_A	459196709	221695	0	0
ReqImpliesValid_A	459196709	553530	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	221695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3113442	0	0
T1	408864	2580	0	0
T2	178665	44364	0	0
T3	8451	91	0	0
T6	8736	45	0	0
T7	44426	1	0	0
T8	20647	1	0	0
T9	2404	12	0	0
T10	246050	917	0	0
T11	9322	86	0	0
T12	38560	672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	553530	0	0
T1	408864	7	0	0
T2	178665	2820	0	0
T3	8451	98	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	248	0	0
T11	9322	93	0	0
T12	38560	1130	0	0
T13	0	10	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	221695	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	94	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	217	0	0
T11	9322	89	0	0
T12	38560	899	0	0
T13	0	10	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	250352	0	0
GntImpliesValid_A	459196709	250352	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	250352	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3153513	0	0
ReadyAndValidImplyGrant_A	459196709	250352	0	0
ReqAndReadyImplyGrant_A	459196709	250352	0	0
ReqImpliesValid_A	459196709	666378	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	250352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3153513	0	0
T1	408864	1316	0	0
T2	178665	41012	0	0
T3	8451	169	0	0
T6	8736	12	0	0
T7	44426	1	0	0
T8	20647	16	0	0
T9	2404	11	0	0
T10	246050	846	0	0
T11	9322	174	0	0
T12	38560	376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	666378	0	0
T1	408864	3	0	0
T2	178665	1368	0	0
T3	8451	182	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	2091	0	0
T9	2404	12	0	0
T10	246050	244	0	0
T11	9322	185	0	0
T12	38560	396	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	250352	0	0
T1	408864	3	0	0
T2	178665	125	0	0
T3	8451	175	0	0
T6	8736	3	0	0
T7	44426	0	0	0
T8	20647	1053	0	0
T9	2404	11	0	0
T10	246050	190	0	0
T11	9322	179	0	0
T12	38560	384	0	0
T13	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	230511	0	0
GntImpliesValid_A	459196709	230511	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	230511	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3062586	0	0
ReadyAndValidImplyGrant_A	459196709	230511	0	0
ReqAndReadyImplyGrant_A	459196709	230511	0	0
ReqImpliesValid_A	459196709	587493	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	230511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3062586	0	0
T1	408864	4131	0	0
T2	178665	47127	0	0
T3	8451	78	0	0
T6	8736	103	0	0
T7	44426	1	0	0
T8	20647	1	0	0
T9	2404	17	0	0
T10	246050	932	0	0
T11	9322	89	0	0
T12	38560	372	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	587493	0	0
T1	408864	371	0	0
T2	178665	3135	0	0
T3	8451	83	0	0
T6	8736	29	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	286	0	0
T11	9322	94	0	0
T12	38560	382	0	0
T13	0	9	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	230511	0	0
T1	408864	12	0	0
T2	178665	144	0	0
T3	8451	80	0	0
T6	8736	14	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	16	0	0
T10	246050	210	0	0
T11	9322	91	0	0
T12	38560	375	0	0
T13	0	9	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	228545	0	0
GntImpliesValid_A	459196709	228545	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	228545	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3200387	0	0
ReadyAndValidImplyGrant_A	459196709	228545	0	0
ReqAndReadyImplyGrant_A	459196709	228545	0	0
ReqImpliesValid_A	459196709	639282	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	228545	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3200387	0	0
T1	408864	4744	0	0
T2	178665	49142	0	0
T3	8451	94	0	0
T6	8736	36	0	0
T7	44426	1415	0	0
T8	20647	2	0	0
T9	2404	18	0	0
T10	246050	935	0	0
T11	9322	81	0	0
T12	38560	377	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	639282	0	0
T1	408864	384	0	0
T2	178665	4029	0	0
T3	8451	99	0	0
T6	8736	6	0	0
T7	44426	2437	0	0
T8	20647	923	0	0
T9	2404	19	0	0
T10	246050	268	0	0
T11	9322	84	0	0
T12	38560	387	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	228545	0	0
T1	408864	13	0	0
T2	178665	142	0	0
T3	8451	96	0	0
T6	8736	6	0	0
T7	44426	599	0	0
T8	20647	462	0	0
T9	2404	18	0	0
T10	246050	226	0	0
T11	9322	82	0	0
T12	38560	380	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	224922	0	0
GntImpliesValid_A	459196709	224922	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	224922	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3240276	0	0
ReadyAndValidImplyGrant_A	459196709	224922	0	0
ReqAndReadyImplyGrant_A	459196709	224922	0	0
ReqImpliesValid_A	459196709	628542	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	224922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3240276	0	0
T1	408864	3216	0	0
T2	178665	51659	0	0
T3	8451	95	0	0
T6	8736	64	0	0
T7	44426	1	0	0
T8	20647	1	0	0
T9	2404	12	0	0
T10	246050	808	0	0
T11	9322	91	0	0
T12	38560	1158	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	628542	0	0
T1	408864	9	0	0
T2	178665	1869	0	0
T3	8451	100	0	0
T6	8736	12	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	227	0	0
T11	9322	104	0	0
T12	38560	1870	0	0
T13	0	10	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	224922	0	0
T1	408864	9	0	0
T2	178665	145	0	0
T3	8451	97	0	0
T6	8736	10	0	0
T7	44426	0	0	0
T8	20647	0	0	0
T9	2404	11	0	0
T10	246050	183	0	0
T11	9322	97	0	0
T12	38560	1512	0	0
T13	0	10	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	231133	0	0
GntImpliesValid_A	459196709	231133	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	231133	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3056065	0	0
ReadyAndValidImplyGrant_A	459196709	231133	0	0
ReqAndReadyImplyGrant_A	459196709	231133	0	0
ReqImpliesValid_A	459196709	688614	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	231133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3056065	0	0
T1	408864	2915	0	0
T2	178665	43237	0	0
T3	8451	82	0	0
T6	8736	101	0	0
T7	44426	1977	0	0
T8	20647	1	0	0
T9	2404	9	0	0
T10	246050	883	0	0
T11	9322	108	0	0
T12	38560	659	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	688614	0	0
T1	408864	137	0	0
T2	178665	1432	0	0
T3	8451	87	0	0
T6	8736	15	0	0
T7	44426	8996	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	247	0	0
T11	9322	121	0	0
T12	38560	1129	0	0
T13	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	231133	0	0
T1	408864	7	0	0
T2	178665	132	0	0
T3	8451	84	0	0
T6	8736	14	0	0
T7	44426	953	0	0
T8	20647	0	0	0
T9	2404	8	0	0
T10	246050	215	0	0
T11	9322	114	0	0
T12	38560	892	0	0
T13	0	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	222088	0	0
GntImpliesValid_A	459196709	222088	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	222088	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	3121310	0	0
ReadyAndValidImplyGrant_A	459196709	222088	0	0
ReqAndReadyImplyGrant_A	459196709	222088	0	0
ReqImpliesValid_A	459196709	591630	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	0	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	222088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	3121310	0	0
T1	408864	2629	0	0
T2	178665	40744	0	0
T3	8451	109	0	0
T6	8736	44	0	0
T7	44426	1	0	0
T8	20647	27	0	0
T9	2404	17	0	0
T10	246050	761	0	0
T11	9322	85	0	0
T12	38560	568	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	591630	0	0
T1	408864	9	0	0
T2	178665	4011	0	0
T3	8451	116	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	948	0	0
T9	2404	16	0	0
T10	246050	214	0	0
T11	9322	90	0	0
T12	38560	1208	0	0
T13	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	222088	0	0
T1	408864	9	0	0
T2	178665	132	0	0
T3	8451	112	0	0
T6	8736	7	0	0
T7	44426	0	0	0
T8	20647	487	0	0
T9	2404	16	0	0
T10	246050	183	0	0
T11	9322	87	0	0
T12	38560	886	0	0
T13	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	887058	0	0
GntImpliesValid_A	459196709	887058	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	887058	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	11900492	0	0
ReadyAndValidImplyGrant_A	459196709	887058	0	0
ReqAndReadyImplyGrant_A	459196709	887058	0	0
ReqImpliesValid_A	459196709	2342922	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	18624	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	887058	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	11900492	0	0
T1	408864	11936	0	0
T2	178665	173102	0	0
T3	8451	1	0	0
T6	8736	306	0	0
T7	44426	1833	0	0
T8	20647	1	0	0
T9	2404	1	0	0
T10	246050	2705	0	0
T11	9322	1	0	0
T12	38560	4	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	2342922	0	0
T1	408864	1054	0	0
T2	178665	17974	0	0
T3	8451	365	0	0
T6	8736	41	0	0
T7	44426	478	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	988	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	18624	0	900
T3	8451	4	0	1
T6	8736	0	0	1
T7	44426	0	0	1
T8	20647	0	0	1
T9	2404	0	0	1
T10	246050	0	0	1
T11	9322	7	0	1
T12	38560	27	0	1
T13	278562	0	0	1
T14	196441	0	0	1
T17	0	6	0	0
T18	0	115	0	0
T19	0	3	0	0
T20	0	600	0	0
T21	0	7	0	0
T22	0	15	0	0
T23	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	887058	0	0
T1	408864	38	0	0
T2	178665	529	0	0
T3	8451	365	0	0
T6	8736	38	0	0
T7	44426	293	0	0
T8	20647	887	0	0
T9	2404	58	0	0
T10	246050	786	0	0
T11	9322	366	0	0
T12	38560	2320	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459196709	459064082	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	459196709	886091	0	0
GntImpliesValid_A	459196709	886091	0	0
GrantKnown_A	459196709	459064082	0	0
IdxKnown_A	459196709	459064082	0	0
IndexIsCorrect_A	459196709	886091	0	0
LockArbDecision_A	459196709	0	0	0
NoReadyValidNoGrant_A	459196709	386037069	0	0
ReadyAndValidImplyGrant_A	459196709	886091	0	0
ReqAndReadyImplyGrant_A	459196709	886091	0	0
ReqImpliesValid_A	459196709	13643278	0	0
ReqStaysHighUntilGranted0_M	459196709	0	0	0
RoundRobin_A	459196709	27212	0	900
ValidKnown_A	459196709	459064082	0	0
gen_data_port_assertion.DataFlow_A	459196709	886091	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	386037069	0	0
T1	408864	397283	0	0
T2	178665	153919	0	0
T3	8451	1	0	0
T6	8736	7590	0	0
T7	44426	37549	0	0
T8	20647	1	0	0
T9	2404	1	0	0
T10	246050	204757	0	0
T11	9322	1	0	0
T12	38560	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	13643278	0	0
T1	408864	10737	0	0
T2	178665	161466	0	0
T3	8451	366	0	0
T6	8736	382	0	0
T7	44426	2318	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	3372	0	0
T11	9322	346	0	0
T12	38560	2186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	27212	0	900
T2	178665	1	0	1
T3	8451	9	0	1
T6	8736	0	0	1
T7	44426	0	0	1
T8	20647	413	0	1
T9	2404	0	0	1
T10	246050	0	0	1
T11	9322	2	0	1
T12	38560	38	0	1
T13	278562	0	0	1
T15	0	11	0	0
T16	0	1	0	0
T17	0	7	0	0
T18	0	104	0	0
T19	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	459064082	0	0
T1	408864	408800	0	0
T2	178665	178662	0	0
T3	8451	8428	0	0
T6	8736	8697	0	0
T7	44426	44421	0	0
T8	20647	20616	0	0
T9	2404	2346	0	0
T10	246050	246040	0	0
T11	9322	9280	0	0
T12	38560	38516	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459196709	886091	0	0
T1	408864	35	0	0
T2	178665	519	0	0
T3	8451	366	0	0
T6	8736	47	0	0
T7	44426	284	0	0
T8	20647	1530	0	0
T9	2404	56	0	0
T10	246050	744	0	0
T11	9322	346	0	0
T12	38560	2186	0	0