Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1624278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259448

1

T1

89

T2

39

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	639054	1			T1	361		T2	44		T3	148
values[0x0]	605660	1			T1	60		T2	78		T3	32
values[0x1]	639012	1			T1	384		T2	41		T3	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

628155

1

T1

311

T2

67

T3

120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29192	1			T1	13		T2	2		T3	4
valid_sources[0x01]	29030	1			T1	13		T2	3		T3	4
valid_sources[0x02]	29812	1			T1	18		T3	5		T9	39
valid_sources[0x03]	29716	1			T1	26		T2	4		T3	8
valid_sources[0x04]	29113	1			T1	9		T2	2		T3	4
valid_sources[0x05]	29586	1			T1	8		T3	2		T9	54
valid_sources[0x06]	29390	1			T1	10		T2	5		T3	6
valid_sources[0x07]	29151	1			T1	7		T2	9		T3	4
valid_sources[0x08]	28639	1			T1	20		T2	4		T3	2
valid_sources[0x09]	29269	1			T1	14		T2	6		T3	4
valid_sources[0x0a]	28857	1			T1	16		T2	1		T3	5
valid_sources[0x0b]	30150	1			T1	13		T2	1		T3	4
valid_sources[0x0c]	28988	1			T1	13		T2	3		T3	3
valid_sources[0x0d]	29172	1			T1	7		T2	1		T3	8
valid_sources[0x0e]	29076	1			T1	11		T2	1		T3	10
valid_sources[0x0f]	29498	1			T1	12		T2	2		T3	3
valid_sources[0x10]	29984	1			T1	14		T2	4		T3	8
valid_sources[0x11]	29180	1			T1	10		T2	1		T3	1
valid_sources[0x12]	29000	1			T1	9		T2	4		T3	8
valid_sources[0x13]	30518	1			T1	11		T2	1		T3	10
valid_sources[0x14]	29092	1			T1	13		T3	2		T9	24
valid_sources[0x15]	30008	1			T1	14		T2	4		T3	5
valid_sources[0x16]	29807	1			T1	14		T2	5		T3	4
valid_sources[0x17]	30282	1			T1	12		T2	1		T3	3
valid_sources[0x18]	29342	1			T1	6		T2	4		T3	6
valid_sources[0x19]	30644	1			T1	12		T2	3		T3	7
valid_sources[0x1a]	30080	1			T1	17		T2	2		T3	5
valid_sources[0x1b]	28946	1			T1	10		T2	3		T3	13
valid_sources[0x1c]	30044	1			T1	23		T2	2		T3	6
valid_sources[0x1d]	29162	1			T1	12		T2	4		T3	3
valid_sources[0x1e]	29861	1			T1	10		T2	1		T3	1
valid_sources[0x1f]	29420	1			T1	8		T2	1		T3	2
valid_sources[0x20]	29163	1			T1	13		T2	3		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27198

1

T1

21

T2

3

T3

9

values[0x0]

all_enables

biggest_size

205283

1

T1

27

T2

35

T3

14

values[0x1]

all_enables

biggest_size

26967

1

T1

41

T2

1

T3

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1635492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266286

1

T1

80

T2

18

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650248	1			T1	390		T2	52		T3	154
values[0x0]	601015	1			T1	64		T2	42		T3	29
values[0x1]	650515	1			T1	349		T2	52		T3	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1256975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644803

1

T1

288

T2

54

T3

134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29363	1			T1	12		T2	1		T3	6
valid_sources[0x01]	29321	1			T1	13		T2	1		T3	3
valid_sources[0x02]	28945	1			T1	6		T3	6		T9	18
valid_sources[0x03]	29321	1			T1	9		T2	11		T3	7
valid_sources[0x04]	29557	1			T1	8		T2	9		T3	6
valid_sources[0x05]	29890	1			T1	18		T3	8		T9	27
valid_sources[0x06]	29740	1			T1	27		T3	7		T9	43
valid_sources[0x07]	29344	1			T1	11		T2	11		T3	7
valid_sources[0x08]	29233	1			T1	14		T3	5		T9	13
valid_sources[0x09]	29169	1			T1	14		T3	1		T9	14
valid_sources[0x0a]	29118	1			T1	12		T3	12		T9	19
valid_sources[0x0b]	30481	1			T1	16		T3	6		T9	35
valid_sources[0x0c]	30120	1			T1	10		T2	4		T9	36
valid_sources[0x0d]	29040	1			T1	7		T2	8		T3	6
valid_sources[0x0e]	29588	1			T1	26		T2	4		T3	3
valid_sources[0x0f]	30034	1			T1	18		T3	3		T9	36
valid_sources[0x10]	29559	1			T1	16		T3	4		T9	16
valid_sources[0x11]	29782	1			T1	11		T3	7		T9	27
valid_sources[0x12]	30561	1			T1	13		T3	6		T9	25
valid_sources[0x13]	30371	1			T1	12		T3	6		T9	43
valid_sources[0x14]	29372	1			T1	24		T3	5		T9	43
valid_sources[0x15]	30417	1			T1	5		T3	8		T9	43
valid_sources[0x16]	29754	1			T1	11		T3	6		T9	11
valid_sources[0x17]	29795	1			T1	13		T3	3		T9	38
valid_sources[0x18]	30521	1			T1	8		T3	8		T9	15
valid_sources[0x19]	29522	1			T1	4		T2	2		T3	5
valid_sources[0x1a]	29387	1			T1	14		T3	5		T9	33
valid_sources[0x1b]	29861	1			T1	15		T2	3		T3	4
valid_sources[0x1c]	29882	1			T1	19		T9	55		T10	1
valid_sources[0x1d]	30204	1			T1	10		T2	3		T3	3
valid_sources[0x1e]	29520	1			T1	9		T2	13		T3	3
valid_sources[0x1f]	29650	1			T1	17		T2	1		T3	5
valid_sources[0x20]	30388	1			T1	12		T3	2		T9	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27870

1

T1

28

T3

12

T9

25

values[0x0]

all_enables

biggest_size

210390

1

T1

25

T2

15

T3

12

values[0x1]

all_enables

biggest_size

28026

1

T1

27

T2

3

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1636342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260196

1

T1

83

T2

20

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	643632	1			T1	343		T2	52		T3	136
values[0x0]	609077	1			T1	58		T2	37		T3	16
values[0x1]	643829	1			T1	378		T2	48		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1265015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

631523

1

T1

315

T2

51

T3

96

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29507	1			T1	11		T2	2		T3	8
valid_sources[0x01]	29740	1			T1	15		T3	4		T9	42
valid_sources[0x02]	28967	1			T1	10		T2	1		T3	6
valid_sources[0x03]	29861	1			T1	14		T2	1		T3	4
valid_sources[0x04]	29468	1			T1	10		T2	3		T3	8
valid_sources[0x05]	30193	1			T1	15		T3	9		T9	24
valid_sources[0x06]	29224	1			T1	7		T3	7		T9	4
valid_sources[0x07]	28840	1			T1	14		T2	3		T3	3
valid_sources[0x08]	29012	1			T1	17		T2	5		T3	1
valid_sources[0x09]	28993	1			T1	18		T2	5		T3	6
valid_sources[0x0a]	28318	1			T1	14		T9	16		T11	17
valid_sources[0x0b]	30496	1			T1	23		T2	4		T3	7
valid_sources[0x0c]	29632	1			T1	9		T2	1		T3	4
valid_sources[0x0d]	29565	1			T1	11		T2	6		T3	5
valid_sources[0x0e]	29446	1			T1	7		T2	3		T3	5
valid_sources[0x0f]	29469	1			T1	26		T2	1		T3	5
valid_sources[0x10]	30344	1			T1	6		T3	4		T9	29
valid_sources[0x11]	29671	1			T1	12		T3	1		T9	12
valid_sources[0x12]	29891	1			T1	13		T2	11		T3	4
valid_sources[0x13]	29688	1			T1	14		T3	2		T9	6
valid_sources[0x14]	29806	1			T1	11		T2	4		T3	4
valid_sources[0x15]	29702	1			T1	17		T2	10		T3	4
valid_sources[0x16]	29698	1			T1	7		T2	3		T3	9
valid_sources[0x17]	30364	1			T1	17		T3	3		T9	58
valid_sources[0x18]	29773	1			T1	15		T2	2		T3	2
valid_sources[0x19]	29277	1			T1	10		T2	3		T3	4
valid_sources[0x1a]	29096	1			T1	15		T3	8		T9	6
valid_sources[0x1b]	29822	1			T1	24		T2	5		T3	3
valid_sources[0x1c]	28819	1			T1	13		T2	4		T3	8
valid_sources[0x1d]	29401	1			T1	10		T3	2		T9	43
valid_sources[0x1e]	29140	1			T1	16		T2	11		T3	4
valid_sources[0x1f]	29293	1			T1	9		T3	2		T9	38
valid_sources[0x20]	29842	1			T1	7		T2	6		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27309

1

T1

28

T2

2

T3

10

values[0x0]

all_enables

biggest_size

205720

1

T1

24

T2

17

T3

5

values[0x1]

all_enables

biggest_size

27167

1

T1

31

T2

1

T3

11