Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7982453	0	0
GntImpliesValid_A	2147483647	7982453	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7982453	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	479683732	0	0
ReadyAndValidImplyGrant_A	2147483647	7982453	0	0
ReqAndReadyImplyGrant_A	2147483647	7982453	0	0
ReqImpliesValid_A	2147483647	37035973	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38591	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7982453	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110800	2109936	0	0
T2	10091760	10091424	0	0
T3	890904	863952	0	0
T7	244680	243888	0	0
T8	2160216	2160024	0	0
T9	291864	289704	0	0
T10	47376	47256	0	0
T11	359232	358344	0	0
T12	44400	44160	0	0
T13	3075576	3074808	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110800	2109936	0	0
T2	10091760	10091424	0	0
T3	890904	863952	0	0
T7	244680	243888	0	0
T8	2160216	2160024	0	0
T9	291864	289704	0	0
T10	47376	47256	0	0
T11	359232	358344	0	0
T12	44400	44160	0	0
T13	3075576	3074808	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110800	2109936	0	0
T2	10091760	10091424	0	0
T3	890904	863952	0	0
T7	244680	243888	0	0
T8	2160216	2160024	0	0
T9	291864	289704	0	0
T10	47376	47256	0	0
T11	359232	358344	0	0
T12	44400	44160	0	0
T13	3075576	3074808	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	479683732	0	0
T1	2110800	38318	0	0
T2	10091760	521652	0	0
T3	890904	19526	0	0
T7	244680	12058	0	0
T8	2160216	96406	0	0
T9	291864	9056	0	0
T10	47376	580	0	0
T11	359232	6986	0	0
T12	44400	525	0	0
T13	3075576	145572	0	0
T14	0	21634	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37035973	0	0
T1	2110800	71371	0	0
T2	10091760	22208	0	0
T3	890904	22168	0	0
T7	244680	934	0	0
T8	2160216	65124	0	0
T9	291864	7007	0	0
T10	47376	600	0	0
T11	359232	5508	0	0
T12	44400	530	0	0
T13	3075576	74664	0	0
T14	0	57552	0	0
T15	0	576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38591	0	21600
T1	175900	1070	0	2
T2	840980	0	0	2
T3	74242	828	0	2
T7	20390	0	0	2
T8	180018	20	0	2
T9	24322	25	0	2
T10	3948	0	0	2
T11	29936	11	0	2
T12	3700	0	0	2
T13	256298	13	0	2
T14	0	3	0	0
T15	0	8	0	0
T16	0	2	0	0
T17	0	19	0	0
T18	0	2	0	0
T19	0	12	0	0
T20	0	1	0	0
T21	0	42	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2110800	2109936	0	0
T2	10091760	10091424	0	0
T3	890904	863952	0	0
T7	244680	243888	0	0
T8	2160216	2160024	0	0
T9	291864	289704	0	0
T10	47376	47256	0	0
T11	359232	358344	0	0
T12	44400	44160	0	0
T13	3075576	3074808	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7982453	0	0
T1	2110800	50650	0	0
T2	10091760	446	0	0
T3	890904	19950	0	0
T7	244680	401	0	0
T8	2160216	10281	0	0
T9	291864	5746	0	0
T10	47376	522	0	0
T11	359232	5388	0	0
T12	44400	464	0	0
T13	3075576	12714	0	0
T14	0	9804	0	0
T15	0	552	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	893446	0	0
GntImpliesValid_A	437340096	893446	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	893446	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	12701779	0	0
ReadyAndValidImplyGrant_A	437340096	893446	0	0
ReqAndReadyImplyGrant_A	437340096	893446	0	0
ReqImpliesValid_A	437340096	2601521	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	893446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	12701779	0	0
T1	87950	3720	0	0
T2	420490	16270	0	0
T3	37121	1622	0	0
T7	10195	379	0	0
T8	90009	5580	0	0
T9	12161	458	0	0
T10	1974	48	0	0
T11	14968	599	0	0
T12	1850	39	0	0
T13	128149	9626	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	2601521	0	0
T1	87950	10403	0	0
T2	420490	295	0	0
T3	37121	2365	0	0
T7	10195	73	0	0
T8	90009	1220	0	0
T9	12161	761	0	0
T10	1974	91	0	0
T11	14968	634	0	0
T12	1850	64	0	0
T13	128149	6945	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	893446	0	0
T1	87950	7060	0	0
T2	420490	53	0	0
T3	37121	1986	0	0
T7	10195	48	0	0
T8	90009	800	0	0
T9	12161	609	0	0
T10	1974	69	0	0
T11	14968	616	0	0
T12	1850	51	0	0
T13	128149	2381	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	901554	0	0
GntImpliesValid_A	437340096	901554	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	901554	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	12748460	0	0
ReadyAndValidImplyGrant_A	437340096	901554	0	0
ReqAndReadyImplyGrant_A	437340096	901554	0	0
ReqImpliesValid_A	437340096	2680382	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	901554	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	12748460	0	0
T1	87950	3914	0	0
T2	420490	15082	0	0
T3	37121	1580	0	0
T7	10195	389	0	0
T8	90009	5573	0	0
T9	12161	428	0	0
T10	1974	48	0	0
T11	14968	592	0	0
T12	1850	34	0	0
T13	128149	7197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	2680382	0	0
T1	87950	9059	0	0
T2	420490	800	0	0
T3	37121	2311	0	0
T7	10195	75	0	0
T8	90009	1338	0	0
T9	12161	725	0	0
T10	1974	65	0	0
T11	14968	631	0	0
T12	1850	43	0	0
T13	128149	8022	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	901554	0	0
T1	87950	6485	0	0
T2	420490	46	0	0
T3	37121	1938	0	0
T7	10195	50	0	0
T8	90009	772	0	0
T9	12161	576	0	0
T10	1974	56	0	0
T11	14968	611	0	0
T12	1850	38	0	0
T13	128149	1527	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	226385	0	0
GntImpliesValid_A	437340096	226385	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	226385	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3150592	0	0
ReadyAndValidImplyGrant_A	437340096	226385	0	0
ReqAndReadyImplyGrant_A	437340096	226385	0	0
ReqImpliesValid_A	437340096	646314	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	226385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3150592	0	0
T1	87950	1035	0	0
T2	420490	4905	0	0
T3	37121	403	0	0
T7	10195	23	0	0
T8	90009	1	0	0
T9	12161	160	0	0
T10	1974	14	0	0
T11	14968	131	0	0
T12	1850	15	0	0
T13	128149	918	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	646314	0	0
T1	87950	2316	0	0
T2	420490	14	0	0
T3	37121	406	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	13	0	0
T11	14968	134	0	0
T12	1850	14	0	0
T13	128149	4110	0	0
T14	0	793	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	226385	0	0
T1	87950	1674	0	0
T2	420490	14	0	0
T3	37121	397	0	0
T7	10195	2	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	13	0	0
T11	14968	132	0	0
T12	1850	14	0	0
T13	128149	458	0	0
T14	0	452	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	230219	0	0
GntImpliesValid_A	437340096	230219	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	230219	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3164140	0	0
ReadyAndValidImplyGrant_A	437340096	230219	0	0
ReqAndReadyImplyGrant_A	437340096	230219	0	0
ReqImpliesValid_A	437340096	698654	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	230219	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3164140	0	0
T1	87950	1663	0	0
T2	420490	2659	0	0
T3	37121	423	0	0
T7	10195	53	0	0
T8	90009	1	0	0
T9	12161	163	0	0
T10	1974	13	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	698654	0	0
T1	87950	3032	0	0
T2	420490	12	0	0
T3	37121	419	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	180	0	0
T10	1974	14	0	0
T11	14968	150	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	2212	0	0
T15	0	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	230219	0	0
T1	87950	2346	0	0
T2	420490	12	0	0
T3	37121	414	0	0
T7	10195	8	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	13	0	0
T11	14968	150	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	822	0	0
T15	0	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	221925	0	0
GntImpliesValid_A	437340096	221925	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	221925	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	6055617	0	0
ReadyAndValidImplyGrant_A	437340096	221925	0	0
ReqAndReadyImplyGrant_A	437340096	221925	0	0
ReqImpliesValid_A	437340096	1398201	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	221925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	6055617	0	0
T1	87950	2667	0	0
T2	420490	5688	0	0
T3	37121	2452	0	0
T7	10195	527	0	0
T8	90009	1336	0	0
T9	12161	916	0	0
T10	1974	73	0	0
T11	14968	854	0	0
T12	1850	53	0	0
T13	128149	0	0	0
T14	0	6936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	1398201	0	0
T1	87950	877	0	0
T2	420490	675	0	0
T3	37121	576	0	0
T7	10195	10	0	0
T8	90009	2034	0	0
T9	12161	281	0	0
T10	1974	37	0	0
T11	14968	155	0	0
T12	1850	34	0	0
T13	128149	0	0	0
T14	0	12597	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	221925	0	0
T1	87950	720	0	0
T2	420490	24	0	0
T3	37121	414	0	0
T7	10195	10	0	0
T8	90009	543	0	0
T9	12161	163	0	0
T10	1974	16	0	0
T11	14968	139	0	0
T12	1850	18	0	0
T13	128149	0	0	0
T14	0	762	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	220183	0	0
GntImpliesValid_A	437340096	220183	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	220183	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	5420375	0	0
ReadyAndValidImplyGrant_A	437340096	220183	0	0
ReqAndReadyImplyGrant_A	437340096	220183	0	0
ReqImpliesValid_A	437340096	1302828	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	220183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	5420375	0	0
T1	87950	3751	0	0
T2	420490	1495	0	0
T3	37121	1932	0	0
T7	10195	118	0	0
T8	90009	444	0	0
T9	12161	1400	0	0
T10	1974	74	0	0
T11	14968	773	0	0
T12	1850	52	0	0
T13	128149	0	0	0
T14	0	14698	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	1302828	0	0
T1	87950	2810	0	0
T2	420490	15	0	0
T3	37121	540	0	0
T7	10195	13	0	0
T8	90009	7610	0	0
T9	12161	363	0	0
T10	1974	20	0	0
T11	14968	154	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	15474	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220183	0	0
T1	87950	1259	0	0
T2	420490	15	0	0
T3	37121	400	0	0
T7	10195	13	0	0
T8	90009	521	0	0
T9	12161	174	0	0
T10	1974	20	0	0
T11	14968	151	0	0
T12	1850	12	0	0
T13	128149	0	0	0
T14	0	2207	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	227759	0	0
GntImpliesValid_A	437340096	227759	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	227759	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	6065641	0	0
ReadyAndValidImplyGrant_A	437340096	227759	0	0
ReqAndReadyImplyGrant_A	437340096	227759	0	0
ReqImpliesValid_A	437340096	1528378	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	227759	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	6065641	0	0
T1	87950	3583	0	0
T2	420490	2128	0	0
T3	37121	2301	0	0
T7	10195	109	0	0
T8	90009	1283	0	0
T9	12161	2001	0	0
T10	1974	71	0	0
T11	14968	900	0	0
T12	1850	50	0	0
T13	128149	1160	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	1528378	0	0
T1	87950	3126	0	0
T2	420490	14	0	0
T3	37121	555	0	0
T7	10195	46	0	0
T8	90009	1560	0	0
T9	12161	371	0	0
T10	1974	30	0	0
T11	14968	174	0	0
T12	1850	16	0	0
T13	128149	3649	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	227759	0	0
T1	87950	1272	0	0
T2	420490	14	0	0
T3	37121	413	0	0
T7	10195	13	0	0
T8	90009	512	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	145	0	0
T12	1850	11	0	0
T13	128149	501	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	209336	0	0
GntImpliesValid_A	437340096	209336	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	209336	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	5045585	0	0
ReadyAndValidImplyGrant_A	437340096	209336	0	0
ReqAndReadyImplyGrant_A	437340096	209336	0	0
ReqImpliesValid_A	437340096	1057753	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	209336	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	5045585	0	0
T1	87950	5957	0	0
T2	420490	2830	0	0
T3	37121	1865	0	0
T7	10195	115	0	0
T8	90009	916	0	0
T9	12161	1345	0	0
T10	1974	34	0	0
T11	14968	879	0	0
T12	1850	51	0	0
T13	128149	1303	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	1057753	0	0
T1	87950	6468	0	0
T2	420490	10	0	0
T3	37121	535	0	0
T7	10195	11	0	0
T8	90009	3995	0	0
T9	12161	458	0	0
T10	1974	14	0	0
T11	14968	178	0	0
T12	1850	33	0	0
T13	128149	3627	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	209336	0	0
T1	87950	1719	0	0
T2	420490	10	0	0
T3	37121	430	0	0
T7	10195	11	0	0
T8	90009	561	0	0
T9	12161	180	0	0
T10	1974	10	0	0
T11	14968	162	0	0
T12	1850	18	0	0
T13	128149	473	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	220726	0	0
GntImpliesValid_A	437340096	220726	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	220726	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3166089	0	0
ReadyAndValidImplyGrant_A	437340096	220726	0	0
ReqAndReadyImplyGrant_A	437340096	220726	0	0
ReqImpliesValid_A	437340096	622512	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	220726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3166089	0	0
T1	87950	980	0	0
T2	420490	3345	0	0
T3	37121	432	0	0
T7	10195	56	0	0
T8	90009	1169	0	0
T9	12161	167	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	14	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	622512	0	0
T1	87950	1371	0	0
T2	420490	10	0	0
T3	37121	481	0	0
T7	10195	9	0	0
T8	90009	2417	0	0
T9	12161	184	0	0
T10	1974	16	0	0
T11	14968	158	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	2278	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220726	0	0
T1	87950	1174	0	0
T2	420490	10	0	0
T3	37121	449	0	0
T7	10195	9	0	0
T8	90009	545	0	0
T9	12161	175	0	0
T10	1974	15	0	0
T11	14968	157	0	0
T12	1850	13	0	0
T13	128149	0	0	0
T14	0	799	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	213510	0	0
GntImpliesValid_A	437340096	213510	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	213510	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3045169	0	0
ReadyAndValidImplyGrant_A	437340096	213510	0	0
ReqAndReadyImplyGrant_A	437340096	213510	0	0
ReqImpliesValid_A	437340096	628512	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	213510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3045169	0	0
T1	87950	798	0	0
T2	420490	3273	0	0
T3	37121	417	0	0
T7	10195	62	0	0
T8	90009	1	0	0
T9	12161	146	0	0
T10	1974	18	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	628512	0	0
T1	87950	2881	0	0
T2	420490	11	0	0
T3	37121	432	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	171	0	0
T10	1974	17	0	0
T11	14968	164	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	6203	0	0
T15	0	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	213510	0	0
T1	87950	1838	0	0
T2	420490	11	0	0
T3	37121	417	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	17	0	0
T11	14968	163	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	849	0	0
T15	0	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	217302	0	0
GntImpliesValid_A	437340096	217302	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	217302	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3161304	0	0
ReadyAndValidImplyGrant_A	437340096	217302	0	0
ReqAndReadyImplyGrant_A	437340096	217302	0	0
ReqImpliesValid_A	437340096	609550	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	217302	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3161304	0	0
T1	87950	1049	0	0
T2	420490	2367	0	0
T3	37121	631	0	0
T7	10195	47	0	0
T8	90009	1	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	135	0	0
T12	1850	17	0	0
T13	128149	1051	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	609550	0	0
T1	87950	1462	0	0
T2	420490	9	0	0
T3	37121	818	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	187	0	0
T10	1974	20	0	0
T11	14968	138	0	0
T12	1850	18	0	0
T13	128149	1888	0	0
T14	0	295	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	217302	0	0
T1	87950	1254	0	0
T2	420490	9	0	0
T3	37121	717	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	178	0	0
T10	1974	17	0	0
T11	14968	136	0	0
T12	1850	17	0	0
T13	128149	472	0	0
T14	0	262	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	220419	0	0
GntImpliesValid_A	437340096	220419	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	220419	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3184623	0	0
ReadyAndValidImplyGrant_A	437340096	220419	0	0
ReqAndReadyImplyGrant_A	437340096	220419	0	0
ReqImpliesValid_A	437340096	585728	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	220419	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3184623	0	0
T1	87950	788	0	0
T2	420490	3744	0	0
T3	37121	615	0	0
T7	10195	99	0	0
T8	90009	2114	0	0
T9	12161	144	0	0
T10	1974	10	0	0
T11	14968	163	0	0
T12	1850	14	0	0
T13	128149	3581	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	585728	0	0
T1	87950	821	0	0
T2	420490	13	0	0
T3	37121	1028	0	0
T7	10195	28	0	0
T8	90009	4073	0	0
T9	12161	163	0	0
T10	1974	9	0	0
T11	14968	168	0	0
T12	1850	13	0	0
T13	128149	6384	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220419	0	0
T1	87950	803	0	0
T2	420490	13	0	0
T3	37121	814	0	0
T7	10195	13	0	0
T8	90009	976	0	0
T9	12161	153	0	0
T10	1974	9	0	0
T11	14968	165	0	0
T12	1850	13	0	0
T13	128149	1535	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	216260	0	0
GntImpliesValid_A	437340096	216260	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	216260	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3155095	0	0
ReadyAndValidImplyGrant_A	437340096	216260	0	0
ReqAndReadyImplyGrant_A	437340096	216260	0	0
ReqImpliesValid_A	437340096	634746	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	216260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3155095	0	0
T1	87950	775	0	0
T2	420490	3691	0	0
T3	37121	1016	0	0
T7	10195	66	0	0
T8	90009	490	0	0
T9	12161	145	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	17	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	634746	0	0
T1	87950	810	0	0
T2	420490	204	0	0
T3	37121	1871	0	0
T7	10195	7	0	0
T8	90009	5965	0	0
T9	12161	168	0	0
T10	1974	11	0	0
T11	14968	131	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	270	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	216260	0	0
T1	87950	791	0	0
T2	420490	9	0	0
T3	37121	1436	0	0
T7	10195	7	0	0
T8	90009	557	0	0
T9	12161	156	0	0
T10	1974	10	0	0
T11	14968	130	0	0
T12	1850	16	0	0
T13	128149	0	0	0
T14	0	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	219391	0	0
GntImpliesValid_A	437340096	219391	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	219391	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3190929	0	0
ReadyAndValidImplyGrant_A	437340096	219391	0	0
ReqAndReadyImplyGrant_A	437340096	219391	0	0
ReqImpliesValid_A	437340096	679504	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	219391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3190929	0	0
T1	87950	960	0	0
T2	420490	4477	0	0
T3	37121	409	0	0
T7	10195	49	0	0
T8	90009	1	0	0
T9	12161	175	0	0
T10	1974	14	0	0
T11	14968	168	0	0
T12	1850	7	0	0
T13	128149	1135	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	679504	0	0
T1	87950	2481	0	0
T2	420490	15	0	0
T3	37121	426	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	194	0	0
T10	1974	13	0	0
T11	14968	171	0	0
T12	1850	8	0	0
T13	128149	4279	0	0
T14	0	5000	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219391	0	0
T1	87950	1719	0	0
T2	420490	15	0	0
T3	37121	410	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	184	0	0
T10	1974	13	0	0
T11	14968	169	0	0
T12	1850	7	0	0
T13	128149	490	0	0
T14	0	745	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	214620	0	0
GntImpliesValid_A	437340096	214620	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	214620	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3139837	0	0
ReadyAndValidImplyGrant_A	437340096	214620	0	0
ReqAndReadyImplyGrant_A	437340096	214620	0	0
ReqImpliesValid_A	437340096	619275	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	214620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3139837	0	0
T1	87950	1121	0	0
T2	420490	2071	0	0
T3	37121	396	0	0
T7	10195	145	0	0
T8	90009	1006	0	0
T9	12161	157	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	20	0	0
T13	128149	1287	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	619275	0	0
T1	87950	2494	0	0
T2	420490	9	0	0
T3	37121	407	0	0
T7	10195	32	0	0
T8	90009	9326	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	153	0	0
T12	1850	19	0	0
T13	128149	1930	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	214620	0	0
T1	87950	1806	0	0
T2	420490	9	0	0
T3	37121	394	0	0
T7	10195	15	0	0
T8	90009	895	0	0
T9	12161	163	0	0
T10	1974	14	0	0
T11	14968	152	0	0
T12	1850	19	0	0
T13	128149	493	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	211963	0	0
GntImpliesValid_A	437340096	211963	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	211963	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3165232	0	0
ReadyAndValidImplyGrant_A	437340096	211963	0	0
ReqAndReadyImplyGrant_A	437340096	211963	0	0
ReqImpliesValid_A	437340096	594920	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	211963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3165232	0	0
T1	87950	746	0	0
T2	420490	1352	0	0
T3	37121	426	0	0
T7	10195	61	0	0
T8	90009	1	0	0
T9	12161	150	0	0
T10	1974	14	0	0
T11	14968	125	0	0
T12	1850	20	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	594920	0	0
T1	87950	1807	0	0
T2	420490	4	0	0
T3	37121	440	0	0
T7	10195	16	0	0
T8	90009	0	0	0
T9	12161	173	0	0
T10	1974	15	0	0
T11	14968	128	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	6194	0	0
T15	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	211963	0	0
T1	87950	1275	0	0
T2	420490	4	0	0
T3	37121	426	0	0
T7	10195	11	0	0
T8	90009	0	0	0
T9	12161	161	0	0
T10	1974	14	0	0
T11	14968	126	0	0
T12	1850	19	0	0
T13	128149	0	0	0
T14	0	935	0	0
T15	0	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	246828	0	0
GntImpliesValid_A	437340096	246828	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	246828	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3275736	0	0
ReadyAndValidImplyGrant_A	437340096	246828	0	0
ReqAndReadyImplyGrant_A	437340096	246828	0	0
ReqImpliesValid_A	437340096	662075	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	246828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3275736	0	0
T1	87950	781	0	0
T2	420490	4108	0	0
T3	37121	447	0	0
T7	10195	56	0	0
T8	90009	1	0	0
T9	12161	168	0	0
T10	1974	19	0	0
T11	14968	156	0	0
T12	1850	25	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	662075	0	0
T1	87950	1702	0	0
T2	420490	13	0	0
T3	37121	453	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	191	0	0
T10	1974	20	0	0
T11	14968	155	0	0
T12	1850	28	0	0
T13	128149	0	0	0
T14	0	304	0	0
T15	0	143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	246828	0	0
T1	87950	1240	0	0
T2	420490	13	0	0
T3	37121	443	0	0
T7	10195	7	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	19	0	0
T11	14968	155	0	0
T12	1850	26	0	0
T13	128149	0	0	0
T14	0	276	0	0
T15	0	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	219622	0	0
GntImpliesValid_A	437340096	219622	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	219622	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3143017	0	0
ReadyAndValidImplyGrant_A	437340096	219622	0	0
ReqAndReadyImplyGrant_A	437340096	219622	0	0
ReqImpliesValid_A	437340096	594780	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	219622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3143017	0	0
T1	87950	749	0	0
T2	420490	4632	0	0
T3	37121	453	0	0
T7	10195	50	0	0
T8	90009	1224	0	0
T9	12161	153	0	0
T10	1974	18	0	0
T11	14968	155	0	0
T12	1850	6	0	0
T13	128149	1060	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	594780	0	0
T1	87950	788	0	0
T2	420490	111	0	0
T3	37121	466	0	0
T7	10195	18	0	0
T8	90009	8568	0	0
T9	12161	168	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	5555	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219622	0	0
T1	87950	767	0	0
T2	420490	13	0	0
T3	37121	452	0	0
T7	10195	8	0	0
T8	90009	866	0	0
T9	12161	160	0	0
T10	1974	17	0	0
T11	14968	154	0	0
T12	1850	5	0	0
T13	128149	575	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	219634	0	0
GntImpliesValid_A	437340096	219634	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	219634	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3186236	0	0
ReadyAndValidImplyGrant_A	437340096	219634	0	0
ReqAndReadyImplyGrant_A	437340096	219634	0	0
ReqImpliesValid_A	437340096	594043	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	219634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3186236	0	0
T1	87950	737	0	0
T2	420490	4328	0	0
T3	37121	417	0	0
T7	10195	116	0	0
T8	90009	859	0	0
T9	12161	145	0	0
T10	1974	14	0	0
T11	14968	156	0	0
T12	1850	19	0	0
T13	128149	1224	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	594043	0	0
T1	87950	764	0	0
T2	420490	557	0	0
T3	37121	418	0	0
T7	10195	23	0	0
T8	90009	1812	0	0
T9	12161	156	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	4817	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	219634	0	0
T1	87950	749	0	0
T2	420490	14	0	0
T3	37121	410	0	0
T7	10195	15	0	0
T8	90009	436	0	0
T9	12161	150	0	0
T10	1974	13	0	0
T11	14968	155	0	0
T12	1850	18	0	0
T13	128149	531	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	220084	0	0
GntImpliesValid_A	437340096	220084	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	220084	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3166552	0	0
ReadyAndValidImplyGrant_A	437340096	220084	0	0
ReqAndReadyImplyGrant_A	437340096	220084	0	0
ReqImpliesValid_A	437340096	634579	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	220084	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3166552	0	0
T1	87950	987	0	0
T2	420490	2556	0	0
T3	37121	417	0	0
T7	10195	129	0	0
T8	90009	1	0	0
T9	12161	156	0	0
T10	1974	17	0	0
T11	14968	157	0	0
T12	1850	10	0	0
T13	128149	1863	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	634579	0	0
T1	87950	1490	0	0
T2	420490	10	0	0
T3	37121	426	0	0
T7	10195	24	0	0
T8	90009	0	0	0
T9	12161	183	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	9790	0	0
T14	0	5104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	220084	0	0
T1	87950	1237	0	0
T2	420490	10	0	0
T3	37121	414	0	0
T7	10195	17	0	0
T8	90009	0	0	0
T9	12161	169	0	0
T10	1974	16	0	0
T11	14968	156	0	0
T12	1850	9	0	0
T13	128149	1026	0	0
T14	0	807	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	222731	0	0
GntImpliesValid_A	437340096	222731	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	222731	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3154859	0	0
ReadyAndValidImplyGrant_A	437340096	222731	0	0
ReqAndReadyImplyGrant_A	437340096	222731	0	0
ReqImpliesValid_A	437340096	652772	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	222731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3154859	0	0
T1	87950	818	0	0
T2	420490	3389	0	0
T3	37121	439	0	0
T7	10195	40	0	0
T8	90009	1	0	0
T9	12161	145	0	0
T10	1974	10	0	0
T11	14968	145	0	0
T12	1850	18	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	652772	0	0
T1	87950	2663	0	0
T2	420490	82	0	0
T3	37121	438	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	158	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	347	0	0
T15	0	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	222731	0	0
T1	87950	1739	0	0
T2	420490	9	0	0
T3	37121	431	0	0
T7	10195	3	0	0
T8	90009	0	0	0
T9	12161	151	0	0
T10	1974	9	0	0
T11	14968	144	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	327	0	0
T15	0	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	229788	0	0
GntImpliesValid_A	437340096	229788	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	229788	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	3221415	0	0
ReadyAndValidImplyGrant_A	437340096	229788	0	0
ReqAndReadyImplyGrant_A	437340096	229788	0	0
ReqImpliesValid_A	437340096	620968	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	0	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	229788	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	3221415	0	0
T1	87950	735	0	0
T2	420490	5647	0	0
T3	37121	417	0	0
T7	10195	78	0	0
T8	90009	1	0	0
T9	12161	162	0	0
T10	1974	15	0	0
T11	14968	143	0	0
T12	1850	14	0	0
T13	128149	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	620968	0	0
T1	87950	778	0	0
T2	420490	546	0	0
T3	37121	426	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	179	0	0
T10	1974	16	0	0
T11	14968	148	0	0
T12	1850	17	0	0
T13	128149	0	0	0
T14	0	481	0	0
T15	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	229788	0	0
T1	87950	755	0	0
T2	420490	16	0	0
T3	37121	414	0	0
T7	10195	9	0	0
T8	90009	0	0	0
T9	12161	170	0	0
T10	1974	15	0	0
T11	14968	145	0	0
T12	1850	15	0	0
T13	128149	0	0	0
T14	0	331	0	0
T15	0	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	894170	0	0
GntImpliesValid_A	437340096	894170	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	894170	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	12155984	0	0
ReadyAndValidImplyGrant_A	437340096	894170	0	0
ReqAndReadyImplyGrant_A	437340096	894170	0	0
ReqImpliesValid_A	437340096	2471550	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	17359	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	894170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	12155984	0	0
T1	87950	3	0	0
T2	420490	18832	0	0
T3	37121	15	0	0
T7	10195	373	0	0
T8	90009	5082	0	0
T9	12161	1	0	0
T10	1974	1	0	0
T11	14968	1	0	0
T12	1850	1	0	0
T13	128149	5774	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	2471550	0	0
T1	87950	5098	0	0
T2	420490	1859	0	0
T3	37121	2640	0	0
T7	10195	100	0	0
T8	90009	1246	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	7457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	17359	0	900
T1	87950	322	0	1
T2	420490	0	0	1
T3	37121	186	0	1
T7	10195	0	0	1
T8	90009	0	0	1
T9	12161	13	0	1
T10	1974	0	0	1
T11	14968	2	0	1
T12	1850	0	0	1
T13	128149	13	0	1
T15	0	7	0	0
T16	0	2	0	0
T17	0	9	0	0
T18	0	2	0	0
T21	0	42	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	894170	0	0
T1	87950	5098	0	0
T2	420490	57	0	0
T3	37121	2640	0	0
T7	10195	60	0	0
T8	90009	775	0	0
T9	12161	588	0	0
T10	1974	65	0	0
T11	14968	571	0	0
T12	1850	45	0	0
T13	128149	1438	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437340096	437212690	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	437340096	864598	0	0
GntImpliesValid_A	437340096	864598	0	0
GrantKnown_A	437340096	437212690	0	0
IdxKnown_A	437340096	437212690	0	0
IndexIsCorrect_A	437340096	864598	0	0
LockArbDecision_A	437340096	0	0	0
NoReadyValidNoGrant_A	437340096	368819466	0	0
ReadyAndValidImplyGrant_A	437340096	864598	0	0
ReqAndReadyImplyGrant_A	437340096	864598	0	0
ReqImpliesValid_A	437340096	13916428	0	0
ReqStaysHighUntilGranted0_M	437340096	0	0	0
RoundRobin_A	437340096	21232	0	900
ValidKnown_A	437340096	437212690	0	0
gen_data_port_assertion.DataFlow_A	437340096	864598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	368819466	0	0
T1	87950	1	0	0
T2	420490	402783	0	0
T3	37121	1	0	0
T7	10195	8918	0	0
T8	90009	69320	0	0
T9	12161	1	0	0
T10	1974	1	0	0
T11	14968	1	0	0
T12	1850	1	0	0
T13	128149	108385	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	13916428	0	0
T1	87950	5870	0	0
T2	420490	16920	0	0
T3	37121	3291	0	0
T7	10195	383	0	0
T8	90009	13960	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	6211	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	21232	0	900
T1	87950	748	0	1
T2	420490	0	0	1
T3	37121	642	0	1
T7	10195	0	0	1
T8	90009	20	0	1
T9	12161	12	0	1
T10	1974	0	0	1
T11	14968	9	0	1
T12	1850	0	0	1
T13	128149	0	0	1
T14	0	3	0	0
T15	0	1	0	0
T17	0	10	0	0
T19	0	12	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	437212690	0	0
T1	87950	87914	0	0
T2	420490	420476	0	0
T3	37121	35998	0	0
T7	10195	10162	0	0
T8	90009	90001	0	0
T9	12161	12071	0	0
T10	1974	1969	0	0
T11	14968	14931	0	0
T12	1850	1840	0	0
T13	128149	128117	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437340096	864598	0	0
T1	87950	5870	0	0
T2	420490	46	0	0
T3	37121	3291	0	0
T7	10195	47	0	0
T8	90009	1522	0	0
T9	12161	656	0	0
T10	1974	44	0	0
T11	14968	604	0	0
T12	1850	35	0	0
T13	128149	814	0	0