Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1493594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239056

1

T1

19

T2

5

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586781	1			T1	36		T2	47		T3	164
values[0x0]	558262	1			T1	35		T2	8		T3	27
values[0x1]	587607	1			T1	46		T2	34		T3	146

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1154183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

578467

1

T1

46

T2

33

T3

122

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27094	1			T1	3		T2	2		T3	5
valid_sources[0x01]	27301	1			T2	3		T3	6		T8	14
valid_sources[0x02]	26588	1			T2	2		T3	8		T8	1
valid_sources[0x03]	27570	1			T2	1		T3	3		T8	7
valid_sources[0x04]	27648	1			T1	1		T3	5		T10	12
valid_sources[0x05]	26905	1			T1	1		T2	3		T3	3
valid_sources[0x06]	26904	1			T1	5		T2	2		T3	8
valid_sources[0x07]	27395	1			T1	2		T3	6		T8	2
valid_sources[0x08]	27303	1			T1	1		T2	3		T3	7
valid_sources[0x09]	26986	1			T2	3		T3	7		T10	34
valid_sources[0x0a]	27162	1			T1	2		T3	9		T8	2
valid_sources[0x0b]	26486	1			T1	1		T2	1		T3	5
valid_sources[0x0c]	27408	1			T1	1		T2	1		T3	4
valid_sources[0x0d]	27591	1			T1	1		T2	1		T3	9
valid_sources[0x0e]	26422	1			T1	2		T2	1		T3	5
valid_sources[0x0f]	25956	1			T1	5		T2	1		T3	8
valid_sources[0x10]	27443	1			T1	2		T2	1		T3	2
valid_sources[0x11]	27347	1			T1	2		T3	6		T10	5
valid_sources[0x12]	27163	1			T1	3		T2	1		T3	3
valid_sources[0x13]	26639	1			T1	2		T2	2		T3	5
valid_sources[0x14]	26506	1			T1	2		T2	2		T3	3
valid_sources[0x15]	26042	1			T1	2		T2	2		T3	7
valid_sources[0x16]	26461	1			T1	1		T2	2		T3	6
valid_sources[0x17]	26697	1			T1	2		T2	1		T3	4
valid_sources[0x18]	26547	1			T1	2		T2	3		T3	4
valid_sources[0x19]	26609	1			T1	2		T2	1		T3	5
valid_sources[0x1a]	27894	1			T1	2		T2	2		T3	7
valid_sources[0x1b]	26835	1			T2	1		T3	5		T10	6
valid_sources[0x1c]	28072	1			T1	3		T2	2		T3	6
valid_sources[0x1d]	27055	1			T2	4		T3	3		T8	2
valid_sources[0x1e]	26438	1			T2	1		T3	5		T8	9
valid_sources[0x1f]	27594	1			T1	1		T3	4		T8	4
valid_sources[0x20]	26642	1			T1	3		T3	3		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24944

1

T1

1

T3

12

T8

2

values[0x0]

all_enables

biggest_size

189083

1

T1

16

T2

3

T3

9

values[0x1]

all_enables

biggest_size

25029

1

T1

2

T2

2

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1500886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244959

1

T1

21

T2

11

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596479	1			T1	48		T2	43		T3	148
values[0x0]	552171	1			T1	49		T2	8		T3	17
values[0x1]	597195	1			T1	72		T2	38		T3	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1152554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

593291

1

T1

56

T2

39

T3

116

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27051	1			T1	3		T2	4		T3	5
valid_sources[0x01]	27872	1			T1	1		T2	2		T3	2
valid_sources[0x02]	27056	1			T3	3		T9	16		T10	12
valid_sources[0x03]	27541	1			T1	5		T3	8		T8	4
valid_sources[0x04]	27702	1			T1	3		T2	1		T3	3
valid_sources[0x05]	26899	1			T1	3		T2	1		T3	6
valid_sources[0x06]	26598	1			T1	2		T2	1		T3	3
valid_sources[0x07]	27349	1			T1	1		T2	1		T3	3
valid_sources[0x08]	27196	1			T1	4		T2	4		T3	2
valid_sources[0x09]	26539	1			T1	2		T2	1		T3	12
valid_sources[0x0a]	27584	1			T1	2		T2	1		T3	3
valid_sources[0x0b]	27532	1			T1	3		T3	5		T9	37
valid_sources[0x0c]	27378	1			T1	1		T2	4		T3	5
valid_sources[0x0d]	26562	1			T1	1		T2	1		T3	4
valid_sources[0x0e]	27146	1			T1	8		T2	4		T3	3
valid_sources[0x0f]	27020	1			T1	4		T3	13		T9	16
valid_sources[0x10]	27489	1			T2	1		T3	6		T9	19
valid_sources[0x11]	26944	1			T1	2		T2	1		T3	2
valid_sources[0x12]	26796	1			T1	1		T3	6		T8	6
valid_sources[0x13]	27673	1			T1	6		T2	3		T10	27
valid_sources[0x14]	26860	1			T1	3		T3	3		T8	6
valid_sources[0x15]	27067	1			T1	2		T2	5		T3	3
valid_sources[0x16]	27021	1			T1	2		T3	3		T9	18
valid_sources[0x17]	26870	1			T1	3		T3	8		T9	3
valid_sources[0x18]	26792	1			T1	6		T2	3		T3	5
valid_sources[0x19]	27316	1			T1	3		T2	1		T3	7
valid_sources[0x1a]	28423	1			T1	4		T2	4		T3	5
valid_sources[0x1b]	27529	1			T1	4		T2	1		T3	3
valid_sources[0x1c]	27575	1			T1	3		T2	1		T3	2
valid_sources[0x1d]	27819	1			T1	5		T2	3		T3	8
valid_sources[0x1e]	27013	1			T1	1		T2	2		T3	4
valid_sources[0x1f]	27545	1			T1	3		T3	8		T9	18
valid_sources[0x20]	27695	1			T1	2		T2	2		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25532

1

T1

1

T2

2

T3

16

values[0x0]

all_enables

biggest_size

193867

1

T1

18

T2

4

T3

7

values[0x1]

all_enables

biggest_size

25560

1

T1

2

T2

5

T3

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1502353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239003

1

T1

12

T2

5

T3

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	590260	1			T1	32		T2	21		T3	156
values[0x0]	561332	1			T1	30		T2	8		T3	32
values[0x1]	589764	1			T1	33		T2	42		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1161560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

579796

1

T1

23

T2

26

T3

136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26592	1			T1	2		T2	1		T3	8
valid_sources[0x01]	28102	1			T1	1		T2	1		T3	7
valid_sources[0x02]	27077	1			T1	5		T2	1		T3	5
valid_sources[0x03]	27466	1			T1	3		T2	2		T3	4
valid_sources[0x04]	27359	1			T1	3		T2	1		T3	4
valid_sources[0x05]	27477	1			T1	1		T2	1		T3	6
valid_sources[0x06]	26960	1			T2	1		T3	9		T8	2
valid_sources[0x07]	27979	1			T2	3		T3	3		T9	12
valid_sources[0x08]	27504	1			T1	4		T2	1		T3	8
valid_sources[0x09]	26661	1			T1	1		T2	2		T3	5
valid_sources[0x0a]	27394	1			T1	3		T2	2		T3	3
valid_sources[0x0b]	27614	1			T1	1		T3	6		T9	14
valid_sources[0x0c]	27934	1			T1	2		T2	1		T3	6
valid_sources[0x0d]	26344	1			T1	5		T2	1		T3	3
valid_sources[0x0e]	27848	1			T1	3		T2	1		T3	4
valid_sources[0x0f]	27522	1			T2	1		T3	13		T8	3
valid_sources[0x10]	26818	1			T1	4		T2	2		T3	6
valid_sources[0x11]	26954	1			T1	1		T3	2		T8	1
valid_sources[0x12]	26856	1			T1	1		T2	3		T3	4
valid_sources[0x13]	28037	1			T2	1		T3	10		T9	13
valid_sources[0x14]	25824	1			T1	1		T2	1		T3	8
valid_sources[0x15]	27100	1			T1	3		T3	2		T8	5
valid_sources[0x16]	27679	1			T1	1		T3	6		T9	13
valid_sources[0x17]	27230	1			T2	1		T3	3		T8	1
valid_sources[0x18]	26638	1			T1	3		T2	3		T3	4
valid_sources[0x19]	27456	1			T2	1		T3	8		T8	1
valid_sources[0x1a]	27223	1			T1	1		T3	8		T8	3
valid_sources[0x1b]	27135	1			T2	2		T3	6		T8	2
valid_sources[0x1c]	27474	1			T3	8		T8	2		T9	10
valid_sources[0x1d]	27741	1			T2	1		T3	8		T9	14
valid_sources[0x1e]	26820	1			T1	2		T3	1		T8	1
valid_sources[0x1f]	27897	1			T1	4		T2	1		T3	7
valid_sources[0x20]	26832	1			T1	3		T2	2		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24951

1

T1

2

T2

1

T3

14

values[0x0]

all_enables

biggest_size

189221

1

T1

8

T2

1

T3

11

values[0x1]

all_enables

biggest_size

24831

1

T1

2

T2

3

T3

17