Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7391851	0	0
GntImpliesValid_A	2147483647	7391851	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7391851	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	487922722	0	0
ReadyAndValidImplyGrant_A	2147483647	7391851	0	0
ReqAndReadyImplyGrant_A	2147483647	7391851	0	0
ReqImpliesValid_A	2147483647	33354341	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46921	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7391851	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	239352	238440	0	0
T2	943896	943680	0	0
T3	1032264	1029216	0	0
T7	9198384	9196200	0	0
T8	51432	50616	0	0
T9	80904	79752	0	0
T10	184824	183888	0	0
T11	45336	43776	0	0
T12	269568	268056	0	0
T13	6457392	6457248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	239352	238440	0	0
T2	943896	943680	0	0
T3	1032264	1029216	0	0
T7	9198384	9196200	0	0
T8	51432	50616	0	0
T9	80904	79752	0	0
T10	184824	183888	0	0
T11	45336	43776	0	0
T12	269568	268056	0	0
T13	6457392	6457248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	239352	238440	0	0
T2	943896	943680	0	0
T3	1032264	1029216	0	0
T7	9198384	9196200	0	0
T8	51432	50616	0	0
T9	80904	79752	0	0
T10	184824	183888	0	0
T11	45336	43776	0	0
T12	269568	268056	0	0
T13	6457392	6457248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	487922722	0	0
T1	239352	11596	0	0
T2	943896	51902	0	0
T3	1032264	12202	0	0
T7	9198384	324239	0	0
T8	51432	670	0	0
T9	80904	287	0	0
T10	184824	5782	0	0
T11	45336	1103	0	0
T12	269568	8904	0	0
T13	6457392	2119433	0	0
T14	0	236482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33354341	0	0
T1	239352	869	0	0
T2	943896	5461	0	0
T3	1032264	37819	0	0
T7	9198384	2239	0	0
T8	51432	481	0	0
T9	80904	3881	0	0
T10	184824	4577	0	0
T11	45336	1032	0	0
T12	269568	5493	0	0
T13	6457392	409174	0	0
T14	0	281718	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46921	0	21600
T3	86022	11	0	2
T7	766532	0	0	2
T8	4286	0	0	2
T9	6742	0	0	2
T10	15402	8	0	2
T11	3778	5	0	2
T12	22464	9	0	2
T13	538116	0	0	2
T14	245064	81	0	2
T15	0	855	0	0
T16	0	19	0	0
T17	0	7	0	0
T18	0	428	0	0
T19	0	4	0	0
T20	521308	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	239352	238440	0	0
T2	943896	943680	0	0
T3	1032264	1029216	0	0
T7	9198384	9196200	0	0
T8	51432	50616	0	0
T9	80904	79752	0	0
T10	184824	183888	0	0
T11	45336	43776	0	0
T12	269568	268056	0	0
T13	6457392	6457248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7391851	0	0
T1	239352	381	0	0
T2	943896	2790	0	0
T3	1032264	19363	0	0
T7	9198384	1305	0	0
T8	51432	395	0	0
T9	80904	2250	0	0
T10	184824	3774	0	0
T11	45336	873	0	0
T12	269568	4181	0	0
T13	6457392	6218	0	0
T14	0	36702	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	826249	0	0
GntImpliesValid_A	452703935	826249	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	826249	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	12287313	0	0
ReadyAndValidImplyGrant_A	452703935	826249	0	0
ReqAndReadyImplyGrant_A	452703935	826249	0	0
ReqImpliesValid_A	452703935	2404876	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	826249	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	12287313	0	0
T1	9973	485	0	0
T2	39329	2119	0	0
T3	43011	1330	0	0
T7	383266	673	0	0
T8	2143	34	0	0
T9	3371	133	0	0
T10	7701	340	0	0
T11	1889	86	0	0
T12	11232	345	0	0
T13	269058	222916	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	2404876	0	0
T1	9973	127	0	0
T2	39329	416	0	0
T3	43011	2196	0	0
T7	383266	191	0	0
T8	2143	53	0	0
T9	3371	254	0	0
T10	7701	589	0	0
T11	1889	161	0	0
T12	11232	580	0	0
T13	269058	26888	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	826249	0	0
T1	9973	59	0	0
T2	39329	281	0	0
T3	43011	1762	0	0
T7	383266	156	0	0
T8	2143	43	0	0
T9	3371	193	0	0
T10	7701	464	0	0
T11	1889	123	0	0
T12	11232	462	0	0
T13	269058	738	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	831252	0	0
GntImpliesValid_A	452703935	831252	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	831252	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	12230419	0	0
ReadyAndValidImplyGrant_A	452703935	831252	0	0
ReqAndReadyImplyGrant_A	452703935	831252	0	0
ReqImpliesValid_A	452703935	2392941	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	831252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	12230419	0	0
T1	9973	431	0	0
T2	39329	2174	0	0
T3	43011	1293	0	0
T7	383266	639	0	0
T8	2143	27	0	0
T9	3371	130	0	0
T10	7701	310	0	0
T11	1889	80	0	0
T12	11232	362	0	0
T13	269058	204924	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	2392941	0	0
T1	9973	71	0	0
T2	39329	450	0	0
T3	43011	2125	0	0
T7	383266	185	0	0
T8	2143	36	0	0
T9	3371	225	0	0
T10	7701	493	0	0
T11	1889	139	0	0
T12	11232	565	0	0
T13	269058	30065	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	831252	0	0
T1	9973	59	0	0
T2	39329	292	0	0
T3	43011	1708	0	0
T7	383266	147	0	0
T8	2143	31	0	0
T9	3371	177	0	0
T10	7701	401	0	0
T11	1889	109	0	0
T12	11232	463	0	0
T13	269058	711	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	200595	0	0
GntImpliesValid_A	452703935	200595	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	200595	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3073166	0	0
ReadyAndValidImplyGrant_A	452703935	200595	0	0
ReqAndReadyImplyGrant_A	452703935	200595	0	0
ReqImpliesValid_A	452703935	523816	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	200595	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3073166	0	0
T1	9973	58	0	0
T2	39329	623	0	0
T3	43011	288	0	0
T7	383266	153	0	0
T8	2143	19	0	0
T9	3371	1	0	0
T10	7701	86	0	0
T11	1889	17	0	0
T12	11232	120	0	0
T13	269058	52047	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	523816	0	0
T1	9973	19	0	0
T2	39329	113	0	0
T3	43011	924	0	0
T7	383266	39	0	0
T8	2143	22	0	0
T9	3371	0	0	0
T10	7701	93	0	0
T11	1889	16	0	0
T12	11232	135	0	0
T13	269058	5639	0	0
T14	0	4821	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	200595	0	0
T1	9973	12	0	0
T2	39329	89	0	0
T3	43011	605	0	0
T7	383266	36	0	0
T8	2143	20	0	0
T9	3371	0	0	0
T10	7701	89	0	0
T11	1889	16	0	0
T12	11232	127	0	0
T13	269058	163	0	0
T14	0	1560	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	209233	0	0
GntImpliesValid_A	452703935	209233	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	209233	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3089879	0	0
ReadyAndValidImplyGrant_A	452703935	209233	0	0
ReqAndReadyImplyGrant_A	452703935	209233	0	0
ReqImpliesValid_A	452703935	559611	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	209233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3089879	0	0
T1	9973	75	0	0
T2	39329	642	0	0
T3	43011	436	0	0
T7	383266	97	0	0
T8	2143	17	0	0
T9	3371	2	0	0
T10	7701	68	0	0
T11	1889	16	0	0
T12	11232	113	0	0
T13	269058	59101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	559611	0	0
T1	9973	8	0	0
T2	39329	104	0	0
T3	43011	856	0	0
T7	383266	33	0	0
T8	2143	18	0	0
T9	3371	1147	0	0
T10	7701	83	0	0
T11	1889	15	0	0
T12	11232	124	0	0
T13	269058	7988	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209233	0	0
T1	9973	8	0	0
T2	39329	88	0	0
T3	43011	645	0	0
T7	383266	23	0	0
T8	2143	17	0	0
T9	3371	574	0	0
T10	7701	75	0	0
T11	1889	15	0	0
T12	11232	118	0	0
T13	269058	186	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	204353	0	0
GntImpliesValid_A	452703935	204353	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	204353	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	5595124	0	0
ReadyAndValidImplyGrant_A	452703935	204353	0	0
ReqAndReadyImplyGrant_A	452703935	204353	0	0
ReqImpliesValid_A	452703935	1180498	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	204353	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	5595124	0	0
T1	9973	103	0	0
T2	39329	528	0	0
T3	43011	1504	0	0
T7	383266	351	0	0
T8	2143	151	0	0
T9	3371	0	0	0
T10	7701	1104	0	0
T11	1889	272	0	0
T12	11232	1200	0	0
T13	269058	111856	0	0
T14	0	67309	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	1180498	0	0
T1	9973	17	0	0
T2	39329	80	0	0
T3	43011	5397	0	0
T7	383266	62	0	0
T8	2143	57	0	0
T9	3371	0	0	0
T10	7701	294	0	0
T11	1889	65	0	0
T12	11232	229	0	0
T13	269058	7555	0	0
T14	0	40994	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204353	0	0
T1	9973	9	0	0
T2	39329	78	0	0
T3	43011	652	0	0
T7	383266	34	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	28	0	0
T12	11232	112	0	0
T13	269058	175	0	0
T14	0	2725	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	192962	0	0
GntImpliesValid_A	452703935	192962	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	192962	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	4726142	0	0
ReadyAndValidImplyGrant_A	452703935	192962	0	0
ReqAndReadyImplyGrant_A	452703935	192962	0	0
ReqImpliesValid_A	452703935	908799	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	192962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	4726142	0	0
T1	9973	125	0	0
T2	39329	260	0	0
T3	43011	1419	0	0
T7	383266	392	0	0
T8	2143	41	0	0
T9	3371	0	0	0
T10	7701	484	0	0
T11	1889	104	0	0
T12	11232	2873	0	0
T13	269058	39950	0	0
T14	0	91188	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	908799	0	0
T1	9973	30	0	0
T2	39329	61	0	0
T3	43011	6279	0	0
T7	383266	101	0	0
T8	2143	14	0	0
T9	3371	0	0	0
T10	7701	157	0	0
T11	1889	21	0	0
T12	11232	677	0	0
T13	269058	399	0	0
T14	0	29530	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	192962	0	0
T1	9973	8	0	0
T2	39329	61	0	0
T3	43011	1172	0	0
T7	383266	46	0	0
T8	2143	7	0	0
T9	3371	0	0	0
T10	7701	107	0	0
T11	1889	12	0	0
T12	11232	112	0	0
T13	269058	165	0	0
T14	0	1858	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	205170	0	0
GntImpliesValid_A	452703935	205170	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	205170	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	5817022	0	0
ReadyAndValidImplyGrant_A	452703935	205170	0	0
ReqAndReadyImplyGrant_A	452703935	205170	0	0
ReqImpliesValid_A	452703935	1247516	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	205170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	5817022	0	0
T1	9973	141	0	0
T2	39329	497	0	0
T3	43011	763	0	0
T7	383266	531	0	0
T8	2143	59	0	0
T9	3371	0	0	0
T10	7701	1295	0	0
T11	1889	108	0	0
T12	11232	708	0	0
T13	269058	136600	0	0
T14	0	53179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	1247516	0	0
T1	9973	9	0	0
T2	39329	82	0	0
T3	43011	3130	0	0
T7	383266	88	0	0
T8	2143	25	0	0
T9	3371	0	0	0
T10	7701	272	0	0
T11	1889	40	0	0
T12	11232	158	0	0
T13	269058	14971	0	0
T14	0	109361	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	205170	0	0
T1	9973	8	0	0
T2	39329	76	0	0
T3	43011	612	0	0
T7	383266	41	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	116	0	0
T11	1889	19	0	0
T12	11232	111	0	0
T13	269058	135	0	0
T14	0	4917	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	201779	0	0
GntImpliesValid_A	452703935	201779	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	201779	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	5532155	0	0
ReadyAndValidImplyGrant_A	452703935	201779	0	0
ReqAndReadyImplyGrant_A	452703935	201779	0	0
ReqImpliesValid_A	452703935	1088466	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	201779	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	5532155	0	0
T1	9973	153	0	0
T2	39329	315	0	0
T3	43011	1119	0	0
T7	383266	383	0	0
T8	2143	158	0	0
T9	3371	0	0	0
T10	7701	683	0	0
T11	1889	109	0	0
T12	11232	1566	0	0
T13	269058	46437	0	0
T14	0	24806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	1088466	0	0
T1	9973	6	0	0
T2	39329	85	0	0
T3	43011	232	0	0
T7	383266	56	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	206	0	0
T11	1889	23	0	0
T12	11232	393	0	0
T13	269058	2213	0	0
T14	0	12312	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201779	0	0
T1	9973	6	0	0
T2	39329	76	0	0
T3	43011	155	0	0
T7	383266	32	0	0
T8	2143	16	0	0
T9	3371	0	0	0
T10	7701	98	0	0
T11	1889	17	0	0
T12	11232	122	0	0
T13	269058	168	0	0
T14	0	1678	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	204240	0	0
GntImpliesValid_A	452703935	204240	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	204240	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3079133	0	0
ReadyAndValidImplyGrant_A	452703935	204240	0	0
ReqAndReadyImplyGrant_A	452703935	204240	0	0
ReqImpliesValid_A	452703935	525730	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	204240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3079133	0	0
T1	9973	83	0	0
T2	39329	586	0	0
T3	43011	227	0	0
T7	383266	162	0	0
T8	2143	11	0	0
T9	3371	1	0	0
T10	7701	95	0	0
T11	1889	22	0	0
T12	11232	114	0	0
T13	269058	49248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	525730	0	0
T1	9973	14	0	0
T2	39329	104	0	0
T3	43011	1129	0	0
T7	383266	51	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	125	0	0
T13	269058	3310	0	0
T14	0	7380	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	204240	0	0
T1	9973	14	0	0
T2	39329	77	0	0
T3	43011	677	0	0
T7	383266	40	0	0
T8	2143	11	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	25	0	0
T12	11232	119	0	0
T13	269058	170	0	0
T14	0	2617	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	199182	0	0
GntImpliesValid_A	452703935	199182	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	199182	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3031685	0	0
ReadyAndValidImplyGrant_A	452703935	199182	0	0
ReqAndReadyImplyGrant_A	452703935	199182	0	0
ReqImpliesValid_A	452703935	534783	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	199182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3031685	0	0
T1	9973	79	0	0
T2	39329	737	0	0
T3	43011	145	0	0
T7	383266	137	0	0
T8	2143	11	0	0
T9	3371	1	0	0
T10	7701	107	0	0
T11	1889	21	0	0
T12	11232	119	0	0
T13	269058	55444	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	534783	0	0
T1	9973	8	0	0
T2	39329	96	0	0
T3	43011	1205	0	0
T7	383266	42	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	24	0	0
T12	11232	128	0	0
T13	269058	3276	0	0
T14	0	12284	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199182	0	0
T1	9973	8	0	0
T2	39329	89	0	0
T3	43011	674	0	0
T7	383266	35	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	108	0	0
T11	1889	22	0	0
T12	11232	123	0	0
T13	269058	173	0	0
T14	0	2481	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	199836	0	0
GntImpliesValid_A	452703935	199836	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	199836	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3055357	0	0
ReadyAndValidImplyGrant_A	452703935	199836	0	0
ReqAndReadyImplyGrant_A	452703935	199836	0	0
ReqImpliesValid_A	452703935	538365	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	199836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3055357	0	0
T1	9973	31	0	0
T2	39329	496	0	0
T3	43011	379	0	0
T7	383266	117	0	0
T8	2143	16	0	0
T9	3371	1	0	0
T10	7701	105	0	0
T11	1889	24	0	0
T12	11232	109	0	0
T13	269058	58671	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	538365	0	0
T1	9973	6	0	0
T2	39329	86	0	0
T3	43011	907	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	25	0	0
T12	11232	116	0	0
T13	269058	1573	0	0
T14	0	1160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	199836	0	0
T1	9973	6	0	0
T2	39329	69	0	0
T3	43011	642	0	0
T7	383266	31	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	113	0	0
T11	1889	24	0	0
T12	11232	112	0	0
T13	269058	182	0	0
T14	0	1089	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	208539	0	0
GntImpliesValid_A	452703935	208539	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	208539	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3056486	0	0
ReadyAndValidImplyGrant_A	452703935	208539	0	0
ReqAndReadyImplyGrant_A	452703935	208539	0	0
ReqImpliesValid_A	452703935	567846	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	208539	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3056486	0	0
T1	9973	111	0	0
T2	39329	478	0	0
T3	43011	246	0	0
T7	383266	138	0	0
T8	2143	10	0	0
T9	3371	1	0	0
T10	7701	83	0	0
T11	1889	23	0	0
T12	11232	116	0	0
T13	269058	56746	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	567846	0	0
T1	9973	11	0	0
T2	39329	64	0	0
T3	43011	1040	0	0
T7	383266	39	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	22	0	0
T12	11232	125	0	0
T13	269058	4731	0	0
T14	0	5566	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	208539	0	0
T1	9973	11	0	0
T2	39329	62	0	0
T3	43011	642	0	0
T7	383266	33	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	85	0	0
T11	1889	22	0	0
T12	11232	120	0	0
T13	269058	170	0	0
T14	0	1699	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	202299	0	0
GntImpliesValid_A	452703935	202299	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	202299	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3078348	0	0
ReadyAndValidImplyGrant_A	452703935	202299	0	0
ReqAndReadyImplyGrant_A	452703935	202299	0	0
ReqImpliesValid_A	452703935	548738	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	202299	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3078348	0	0
T1	9973	37	0	0
T2	39329	655	0	0
T3	43011	815	0	0
T7	383266	136	0	0
T8	2143	14	0	0
T9	3371	1	0	0
T10	7701	86	0	0
T11	1889	24	0	0
T12	11232	116	0	0
T13	269058	53230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	548738	0	0
T1	9973	5	0	0
T2	39329	123	0	0
T3	43011	1605	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	91	0	0
T11	1889	23	0	0
T12	11232	131	0	0
T13	269058	4222	0	0
T14	0	9420	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	202299	0	0
T1	9973	5	0	0
T2	39329	86	0	0
T3	43011	1209	0	0
T7	383266	32	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	88	0	0
T11	1889	23	0	0
T12	11232	123	0	0
T13	269058	168	0	0
T14	0	1993	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	201025	0	0
GntImpliesValid_A	452703935	201025	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	201025	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3031165	0	0
ReadyAndValidImplyGrant_A	452703935	201025	0	0
ReqAndReadyImplyGrant_A	452703935	201025	0	0
ReqImpliesValid_A	452703935	566346	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	201025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3031165	0	0
T1	9973	87	0	0
T2	39329	598	0	0
T3	43011	542	0	0
T7	383266	123	0	0
T8	2143	18	0	0
T9	3371	1	0	0
T10	7701	107	0	0
T11	1889	28	0	0
T12	11232	135	0	0
T13	269058	62271	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	566346	0	0
T1	9973	16	0	0
T2	39329	131	0	0
T3	43011	732	0	0
T7	383266	39	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	114	0	0
T11	1889	31	0	0
T12	11232	144	0	0
T13	269058	2181	0	0
T14	0	3270	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	201025	0	0
T1	9973	10	0	0
T2	39329	82	0	0
T3	43011	636	0	0
T7	383266	34	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	110	0	0
T11	1889	29	0	0
T12	11232	139	0	0
T13	269058	180	0	0
T14	0	1551	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	206954	0	0
GntImpliesValid_A	452703935	206954	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	206954	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3138405	0	0
ReadyAndValidImplyGrant_A	452703935	206954	0	0
ReqAndReadyImplyGrant_A	452703935	206954	0	0
ReqImpliesValid_A	452703935	538070	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	206954	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3138405	0	0
T1	9973	40	0	0
T2	39329	649	0	0
T3	43011	136	0	0
T7	383266	121	0	0
T8	2143	14	0	0
T9	3371	1	0	0
T10	7701	102	0	0
T11	1889	26	0	0
T12	11232	98	0	0
T13	269058	57326	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	538070	0	0
T1	9973	5	0	0
T2	39329	94	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	17	0	0
T9	3371	0	0	0
T10	7701	105	0	0
T11	1889	25	0	0
T12	11232	101	0	0
T13	269058	1302	0	0
T14	0	8598	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	206954	0	0
T1	9973	5	0	0
T2	39329	84	0	0
T3	43011	135	0	0
T7	383266	32	0	0
T8	2143	15	0	0
T9	3371	0	0	0
T10	7701	103	0	0
T11	1889	25	0	0
T12	11232	99	0	0
T13	269058	185	0	0
T14	0	2681	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	197653	0	0
GntImpliesValid_A	452703935	197653	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	197653	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3001422	0	0
ReadyAndValidImplyGrant_A	452703935	197653	0	0
ReqAndReadyImplyGrant_A	452703935	197653	0	0
ReqImpliesValid_A	452703935	509613	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	197653	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3001422	0	0
T1	9973	12	0	0
T2	39329	477	0	0
T3	43011	142	0	0
T7	383266	175	0	0
T8	2143	11	0	0
T9	3371	2	0	0
T10	7701	120	0	0
T11	1889	25	0	0
T12	11232	120	0	0
T13	269058	56811	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	509613	0	0
T1	9973	3	0	0
T2	39329	94	0	0
T3	43011	1108	0	0
T7	383266	50	0	0
T8	2143	14	0	0
T9	3371	1089	0	0
T10	7701	131	0	0
T11	1889	28	0	0
T12	11232	127	0	0
T13	269058	3142	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197653	0	0
T1	9973	3	0	0
T2	39329	68	0	0
T3	43011	624	0	0
T7	383266	41	0	0
T8	2143	12	0	0
T9	3371	545	0	0
T10	7701	125	0	0
T11	1889	26	0	0
T12	11232	123	0	0
T13	269058	178	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	225080	0	0
GntImpliesValid_A	452703935	225080	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	225080	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3227135	0	0
ReadyAndValidImplyGrant_A	452703935	225080	0	0
ReqAndReadyImplyGrant_A	452703935	225080	0	0
ReqImpliesValid_A	452703935	613240	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	225080	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3227135	0	0
T1	9973	95	0	0
T2	39329	994	0	0
T3	43011	547	0	0
T7	383266	126	0	0
T8	2143	12	0	0
T9	3371	1	0	0
T10	7701	115	0	0
T11	1889	20	0	0
T12	11232	111	0	0
T13	269058	58826	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	613240	0	0
T1	9973	14	0	0
T2	39329	178	0	0
T3	43011	2963	0	0
T7	383266	58	0	0
T8	2143	13	0	0
T9	3371	0	0	0
T10	7701	130	0	0
T11	1889	19	0	0
T12	11232	128	0	0
T13	269058	4000	0	0
T14	0	5416	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	225080	0	0
T1	9973	9	0	0
T2	39329	145	0	0
T3	43011	1754	0	0
T7	383266	36	0	0
T8	2143	12	0	0
T9	3371	0	0	0
T10	7701	122	0	0
T11	1889	19	0	0
T12	11232	119	0	0
T13	269058	168	0	0
T14	0	1751	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	209634	0	0
GntImpliesValid_A	452703935	209634	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	209634	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3054684	0	0
ReadyAndValidImplyGrant_A	452703935	209634	0	0
ReqAndReadyImplyGrant_A	452703935	209634	0	0
ReqImpliesValid_A	452703935	541280	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	209634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3054684	0	0
T1	9973	21	0	0
T2	39329	578	0	0
T3	43011	318	0	0
T7	383266	124	0	0
T8	2143	9	0	0
T9	3371	1	0	0
T10	7701	90	0	0
T11	1889	20	0	0
T12	11232	117	0	0
T13	269058	69687	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	541280	0	0
T1	9973	3	0	0
T2	39329	96	0	0
T3	43011	984	0	0
T7	383266	36	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	115	0	0
T11	1889	23	0	0
T12	11232	130	0	0
T13	269058	2575	0	0
T14	0	12172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	209634	0	0
T1	9973	3	0	0
T2	39329	76	0	0
T3	43011	650	0	0
T7	383266	31	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	102	0	0
T11	1889	21	0	0
T12	11232	123	0	0
T13	269058	189	0	0
T14	0	2513	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	220043	0	0
GntImpliesValid_A	452703935	220043	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	220043	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3175652	0	0
ReadyAndValidImplyGrant_A	452703935	220043	0	0
ReqAndReadyImplyGrant_A	452703935	220043	0	0
ReqImpliesValid_A	452703935	575507	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	220043	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3175652	0	0
T1	9973	34	0	0
T2	39329	598	0	0
T3	43011	154	0	0
T7	383266	168	0	0
T8	2143	6	0	0
T9	3371	5	0	0
T10	7701	102	0	0
T11	1889	13	0	0
T12	11232	122	0	0
T13	269058	58772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	575507	0	0
T1	9973	13	0	0
T2	39329	81	0	0
T3	43011	158	0	0
T7	383266	34	0	0
T8	2143	9	0	0
T9	3371	814	0	0
T10	7701	115	0	0
T11	1889	14	0	0
T12	11232	131	0	0
T13	269058	4438	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	220043	0	0
T1	9973	5	0	0
T2	39329	81	0	0
T3	43011	155	0	0
T7	383266	33	0	0
T8	2143	7	0	0
T9	3371	409	0	0
T10	7701	108	0	0
T11	1889	13	0	0
T12	11232	126	0	0
T13	269058	186	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	198139	0	0
GntImpliesValid_A	452703935	198139	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	198139	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3083723	0	0
ReadyAndValidImplyGrant_A	452703935	198139	0	0
ReqAndReadyImplyGrant_A	452703935	198139	0	0
ReqImpliesValid_A	452703935	499003	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	198139	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3083723	0	0
T1	9973	108	0	0
T2	39329	662	0	0
T3	43011	137	0	0
T7	383266	147	0	0
T8	2143	11	0	0
T9	3371	1	0	0
T10	7701	97	0	0
T11	1889	24	0	0
T12	11232	111	0	0
T13	269058	49820	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	499003	0	0
T1	9973	19	0	0
T2	39329	101	0	0
T3	43011	137	0	0
T7	383266	45	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	106	0	0
T11	1889	27	0	0
T12	11232	114	0	0
T13	269058	2131	0	0
T14	0	1235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	198139	0	0
T1	9973	14	0	0
T2	39329	81	0	0
T3	43011	136	0	0
T7	383266	32	0	0
T8	2143	10	0	0
T9	3371	0	0	0
T10	7701	101	0	0
T11	1889	25	0	0
T12	11232	112	0	0
T13	269058	154	0	0
T14	0	1105	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	212825	0	0
GntImpliesValid_A	452703935	212825	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	212825	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3087127	0	0
ReadyAndValidImplyGrant_A	452703935	212825	0	0
ReqAndReadyImplyGrant_A	452703935	212825	0	0
ReqImpliesValid_A	452703935	571673	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	212825	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3087127	0	0
T1	9973	96	0	0
T2	39329	687	0	0
T3	43011	131	0	0
T7	383266	166	0	0
T8	2143	10	0	0
T9	3371	1	0	0
T10	7701	108	0	0
T11	1889	24	0	0
T12	11232	108	0	0
T13	269058	51645	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	571673	0	0
T1	9973	13	0	0
T2	39329	141	0	0
T3	43011	135	0	0
T7	383266	40	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	117	0	0
T11	1889	25	0	0
T12	11232	113	0	0
T13	269058	3733	0	0
T14	0	6485	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	212825	0	0
T1	9973	12	0	0
T2	39329	92	0	0
T3	43011	132	0	0
T7	383266	36	0	0
T8	2143	9	0	0
T9	3371	0	0	0
T10	7701	112	0	0
T11	1889	24	0	0
T12	11232	110	0	0
T13	269058	178	0	0
T14	0	1639	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	197029	0	0
GntImpliesValid_A	452703935	197029	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	197029	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	3050481	0	0
ReadyAndValidImplyGrant_A	452703935	197029	0	0
ReqAndReadyImplyGrant_A	452703935	197029	0	0
ReqImpliesValid_A	452703935	517827	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	0	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	197029	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	3050481	0	0
T1	9973	79	0	0
T2	39329	661	0	0
T3	43011	128	0	0
T7	383266	176	0	0
T8	2143	9	0	0
T9	3371	1	0	0
T10	7701	93	0	0
T11	1889	15	0	0
T12	11232	119	0	0
T13	269058	55475	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	517827	0	0
T1	9973	9	0	0
T2	39329	134	0	0
T3	43011	1036	0	0
T7	383266	53	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	100	0	0
T11	1889	16	0	0
T12	11232	144	0	0
T13	269058	1699	0	0
T14	0	11714	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	197029	0	0
T1	9973	9	0	0
T2	39329	83	0	0
T3	43011	581	0	0
T7	383266	40	0	0
T8	2143	8	0	0
T9	3371	0	0	0
T10	7701	96	0	0
T11	1889	15	0	0
T12	11232	131	0	0
T13	269058	183	0	0
T14	0	2845	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	816421	0	0
GntImpliesValid_A	452703935	816421	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	816421	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	11482907	0	0
ReadyAndValidImplyGrant_A	452703935	816421	0	0
ReqAndReadyImplyGrant_A	452703935	816421	0	0
ReqImpliesValid_A	452703935	2197110	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	17118	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	816421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	11482907	0	0
T1	9973	370	0	0
T2	39329	1927	0	0
T3	43011	2	0	0
T7	383266	475	0	0
T8	2143	1	0	0
T9	3371	1	0	0
T10	7701	1	0	0
T11	1889	1	0	0
T12	11232	1	0	0
T13	269058	207887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	2197110	0	0
T1	9973	90	0	0
T2	39329	442	0	0
T3	43011	1739	0	0
T7	383266	166	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	22744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	17118	0	900
T3	43011	7	0	1
T7	383266	0	0	1
T8	2143	0	0	1
T9	3371	0	0	1
T10	7701	4	0	1
T11	1889	3	0	1
T12	11232	6	0	1
T13	269058	0	0	1
T14	122532	78	0	1
T15	0	17	0	0
T16	0	8	0	0
T17	0	5	0	0
T18	0	364	0	0
T19	0	1	0	0
T20	260654	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	816421	0	0
T1	9973	52	0	0
T2	39329	298	0	0
T3	43011	1739	0	0
T7	383266	143	0	0
T8	2143	34	0	0
T9	3371	178	0	0
T10	7701	403	0	0
T11	1889	118	0	0
T12	11232	420	0	0
T13	269058	640	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452703935	452585039	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452703935	821359	0	0
GntImpliesValid_A	452703935	821359	0	0
GrantKnown_A	452703935	452585039	0	0
IdxKnown_A	452703935	452585039	0	0
IndexIsCorrect_A	452703935	821359	0	0
LockArbDecision_A	452703935	0	0	0
NoReadyValidNoGrant_A	452703935	380937792	0	0
ReadyAndValidImplyGrant_A	452703935	821359	0	0
ReqAndReadyImplyGrant_A	452703935	821359	0	0
ReqImpliesValid_A	452703935	13202687	0	0
ReqStaysHighUntilGranted0_M	452703935	0	0	0
RoundRobin_A	452703935	29803	0	900
ValidKnown_A	452703935	452585039	0	0
gen_data_port_assertion.DataFlow_A	452703935	821359	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	380937792	0	0
T1	9973	8742	0	0
T2	39329	33961	0	0
T3	43011	1	0	0
T7	383266	318529	0	0
T8	2143	1	0	0
T9	3371	1	0	0
T10	7701	1	0	0
T11	1889	1	0	0
T12	11232	1	0	0
T13	269058	243743	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	13202687	0	0
T1	9973	353	0	0
T2	39329	2105	0	0
T3	43011	1666	0	0
T7	383266	736	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	248399	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	29803	0	900
T3	43011	4	0	1
T7	383266	0	0	1
T8	2143	0	0	1
T9	3371	0	0	1
T10	7701	4	0	1
T11	1889	2	0	1
T12	11232	3	0	1
T13	269058	0	0	1
T14	122532	3	0	1
T15	0	838	0	0
T16	0	11	0	0
T17	0	2	0	0
T18	0	64	0	0
T19	0	3	0	0
T20	260654	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	452585039	0	0
T1	9973	9935	0	0
T2	39329	39320	0	0
T3	43011	42884	0	0
T7	383266	383175	0	0
T8	2143	2109	0	0
T9	3371	3323	0	0
T10	7701	7662	0	0
T11	1889	1824	0	0
T12	11232	11169	0	0
T13	269058	269052	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452703935	821359	0	0
T1	9973	46	0	0
T2	39329	276	0	0
T3	43011	1666	0	0
T7	383266	161	0	0
T8	2143	42	0	0
T9	3371	174	0	0
T10	7701	433	0	0
T11	1889	103	0	0
T12	11232	455	0	0
T13	269058	673	0	0