Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1550243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247899

1

T1

14

T2

12

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	610249	1			T1	39		T2	49		T3	69
values[0x0]	578374	1			T1	33		T2	33		T3	56
values[0x1]	609519	1			T1	35		T2	43		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1198136	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

600006

1

T1

30

T2

37

T3

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28160	1			T1	3		T7	4		T4	43
valid_sources[0x01]	28097	1			T1	3		T2	6		T7	18
valid_sources[0x02]	28377	1			T1	1		T2	4		T7	5
valid_sources[0x03]	27970	1			T1	4		T7	5		T4	1
valid_sources[0x04]	29272	1			T1	5		T7	5		T4	6
valid_sources[0x05]	28642	1			T1	1		T7	9		T4	31
valid_sources[0x06]	28762	1			T7	8		T4	8		T9	13
valid_sources[0x07]	28243	1			T1	2		T2	4		T7	6
valid_sources[0x08]	29048	1			T7	6		T4	11		T10	32
valid_sources[0x09]	28146	1			T1	2		T7	13		T4	3
valid_sources[0x0a]	28239	1			T7	4		T9	63		T10	29
valid_sources[0x0b]	28122	1			T1	3		T7	9		T4	6
valid_sources[0x0c]	26980	1			T1	3		T7	6		T4	14
valid_sources[0x0d]	28595	1			T1	3		T7	7		T4	17
valid_sources[0x0e]	28203	1			T1	2		T2	4		T7	6
valid_sources[0x0f]	27836	1			T2	16		T7	10		T4	15
valid_sources[0x10]	28268	1			T1	3		T7	7		T4	15
valid_sources[0x11]	27847	1			T1	2		T2	8		T7	5
valid_sources[0x12]	28590	1			T1	5		T2	2		T7	6
valid_sources[0x13]	27975	1			T7	9		T4	1		T9	25
valid_sources[0x14]	28325	1			T1	1		T7	6		T4	12
valid_sources[0x15]	27199	1			T3	9		T7	5		T10	21
valid_sources[0x16]	28211	1			T1	1		T3	22		T7	7
valid_sources[0x17]	28967	1			T3	14		T7	6		T4	55
valid_sources[0x18]	28026	1			T7	5		T4	5		T9	27
valid_sources[0x19]	28205	1			T1	1		T2	6		T7	5
valid_sources[0x1a]	28632	1			T1	1		T2	1		T7	8
valid_sources[0x1b]	27807	1			T1	3		T2	3		T7	8
valid_sources[0x1c]	27577	1			T1	2		T7	9		T4	8
valid_sources[0x1d]	28251	1			T1	1		T2	3		T7	6
valid_sources[0x1e]	27279	1			T2	4		T7	7		T4	2
valid_sources[0x1f]	27831	1			T1	1		T7	18		T8	1
valid_sources[0x20]	27252	1			T1	2		T3	17		T7	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26174

1

T1

3

T2

2

T3

1

values[0x0]

all_enables

biggest_size

195525

1

T1

10

T2

9

T3

26

values[0x1]

all_enables

biggest_size

26200

1

T1

1

T2

1

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1556848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252669

1

T1

21

T2

16

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619282	1			T1	46		T2	55		T3	43
values[0x0]	570831	1			T1	41		T2	41		T3	39
values[0x1]	619404	1			T1	50		T2	56		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615642

1

T1

48

T2

48

T3

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28696	1			T2	5		T3	3		T7	7
valid_sources[0x01]	28054	1			T2	5		T3	4		T7	7
valid_sources[0x02]	28447	1			T7	5		T4	10		T9	30
valid_sources[0x03]	28366	1			T3	3		T7	6		T4	16
valid_sources[0x04]	28530	1			T2	10		T3	2		T7	10
valid_sources[0x05]	28087	1			T3	3		T7	5		T4	16
valid_sources[0x06]	29137	1			T2	3		T7	9		T4	15
valid_sources[0x07]	28873	1			T1	6		T7	7		T4	17
valid_sources[0x08]	28235	1			T1	8		T3	2		T7	9
valid_sources[0x09]	28501	1			T3	1		T7	9		T4	19
valid_sources[0x0a]	27707	1			T1	5		T3	10		T7	7
valid_sources[0x0b]	28242	1			T7	10		T4	10		T8	1
valid_sources[0x0c]	27742	1			T1	3		T3	1		T7	3
valid_sources[0x0d]	28337	1			T1	3		T3	2		T7	7
valid_sources[0x0e]	28153	1			T3	13		T7	6		T4	16
valid_sources[0x0f]	28389	1			T1	17		T3	1		T7	6
valid_sources[0x10]	28696	1			T3	1		T7	8		T4	15
valid_sources[0x11]	27809	1			T2	2		T3	9		T7	5
valid_sources[0x12]	28785	1			T3	1		T7	7		T4	18
valid_sources[0x13]	28829	1			T1	16		T7	4		T4	9
valid_sources[0x14]	27840	1			T7	8		T4	14		T8	1
valid_sources[0x15]	28640	1			T1	1		T2	15		T3	1
valid_sources[0x16]	27630	1			T7	4		T4	15		T9	18
valid_sources[0x17]	28612	1			T3	4		T7	8		T4	9
valid_sources[0x18]	28084	1			T1	4		T7	6		T4	16
valid_sources[0x19]	28956	1			T1	5		T2	12		T7	7
valid_sources[0x1a]	27481	1			T3	1		T7	7		T4	19
valid_sources[0x1b]	27929	1			T1	1		T3	1		T7	8
valid_sources[0x1c]	28159	1			T1	6		T2	13		T7	7
valid_sources[0x1d]	28678	1			T1	2		T3	3		T7	6
valid_sources[0x1e]	28192	1			T2	20		T3	1		T7	10
valid_sources[0x1f]	28090	1			T2	1		T7	5		T4	16
valid_sources[0x20]	28284	1			T1	9		T3	6		T7	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26418

1

T1

5

T2

4

T3

5

values[0x0]

all_enables

biggest_size

199895

1

T1

13

T2

12

T3

11

values[0x1]

all_enables

biggest_size

26356

1

T1

3

T3

2

T7

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1559924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247478

1

T1

15

T2

11

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613767	1			T1	43		T2	48		T3	66
values[0x0]	580318	1			T1	35		T2	41		T3	59
values[0x1]	613317	1			T1	39		T2	34		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

602351

1

T1

42

T2

37

T3

71

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28619	1			T1	1		T2	3		T3	11
valid_sources[0x01]	27696	1			T2	6		T7	7		T4	15
valid_sources[0x02]	28185	1			T1	5		T2	3		T3	9
valid_sources[0x03]	28114	1			T1	2		T2	3		T7	8
valid_sources[0x04]	28412	1			T2	1		T7	6		T4	21
valid_sources[0x05]	28023	1			T1	3		T2	4		T7	9
valid_sources[0x06]	27994	1			T1	7		T2	3		T7	10
valid_sources[0x07]	27817	1			T1	2		T3	12		T7	6
valid_sources[0x08]	28475	1			T2	1		T7	7		T4	15
valid_sources[0x09]	29112	1			T2	2		T3	5		T7	12
valid_sources[0x0a]	28463	1			T7	7		T4	13		T9	46
valid_sources[0x0b]	27644	1			T2	3		T3	13		T7	6
valid_sources[0x0c]	27805	1			T2	3		T3	20		T7	13
valid_sources[0x0d]	28485	1			T1	1		T2	2		T7	9
valid_sources[0x0e]	28519	1			T1	2		T2	3		T7	10
valid_sources[0x0f]	28363	1			T1	2		T2	1		T7	12
valid_sources[0x10]	27594	1			T1	2		T7	6		T4	20
valid_sources[0x11]	28801	1			T1	1		T2	1		T3	12
valid_sources[0x12]	28094	1			T1	6		T7	8		T4	13
valid_sources[0x13]	28319	1			T2	1		T7	11		T4	12
valid_sources[0x14]	27764	1			T2	3		T3	8		T7	13
valid_sources[0x15]	27799	1			T2	1		T7	7		T4	5
valid_sources[0x16]	28116	1			T1	4		T2	1		T7	8
valid_sources[0x17]	28717	1			T1	2		T7	9		T4	9
valid_sources[0x18]	29016	1			T1	2		T2	5		T7	7
valid_sources[0x19]	28768	1			T2	4		T7	9		T4	11
valid_sources[0x1a]	27616	1			T1	2		T2	1		T7	10
valid_sources[0x1b]	28245	1			T1	3		T2	3		T7	4
valid_sources[0x1c]	27944	1			T1	3		T2	1		T3	7
valid_sources[0x1d]	27392	1			T1	1		T3	4		T7	8
valid_sources[0x1e]	27597	1			T1	3		T2	1		T7	8
valid_sources[0x1f]	28509	1			T7	7		T4	17		T8	1
valid_sources[0x20]	27921	1			T1	2		T2	1		T7	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25873

1

T1

1

T3

4

T7

3

values[0x0]

all_enables

biggest_size

195648

1

T1

14

T2

10

T3

20

values[0x1]

all_enables

biggest_size

25957

1

T2

1

T3

1

T7

10