Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7821123	0	0
GntImpliesValid_A	2147483647	7821123	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7821123	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	434946968	0	0
ReadyAndValidImplyGrant_A	2147483647	7821123	0	0
ReqAndReadyImplyGrant_A	2147483647	7821123	0	0
ReqImpliesValid_A	2147483647	34295545	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40374	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7821123	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48744	46896	0	0
T2	46608	45120	0	0
T3	22344	21720	0	0
T4	662496	661296	0	0
T7	375504	374688	0	0
T8	1004064	1002984	0	0
T9	233928	233640	0	0
T10	185664	185352	0	0
T11	42144	41640	0	0
T12	35400	35160	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48744	46896	0	0
T2	46608	45120	0	0
T3	22344	21720	0	0
T4	662496	661296	0	0
T7	375504	374688	0	0
T8	1004064	1002984	0	0
T9	233928	233640	0	0
T10	185664	185352	0	0
T11	42144	41640	0	0
T12	35400	35160	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48744	46896	0	0
T2	46608	45120	0	0
T3	22344	21720	0	0
T4	662496	661296	0	0
T7	375504	374688	0	0
T8	1004064	1002984	0	0
T9	233928	233640	0	0
T10	185664	185352	0	0
T11	42144	41640	0	0
T12	35400	35160	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	434946968	0	0
T1	48744	540	0	0
T2	46608	467	0	0
T3	22344	516	0	0
T4	662496	41432	0	0
T7	375504	16824	0	0
T8	1004064	63471	0	0
T9	233928	4070	0	0
T10	185664	3906	0	0
T11	42144	533	0	0
T12	35400	401	0	0
T13	0	289	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34295545	0	0
T1	48744	438	0	0
T2	46608	456	0	0
T3	22344	540	0	0
T4	662496	6700	0	0
T7	375504	8143	0	0
T8	1004064	9068	0	0
T9	233928	3797	0	0
T10	185664	3577	0	0
T11	42144	469	0	0
T12	35400	431	0	0
T13	0	244	0	0
T14	0	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40374	0	21600
T3	1862	5	0	2
T4	55208	2	0	2
T7	31292	61	0	2
T8	83672	1	0	2
T9	19494	12	0	2
T10	15472	8	0	2
T11	3512	0	0	2
T12	2950	0	0	2
T13	408854	0	0	2
T14	136784	1	0	2
T15	0	33	0	0
T16	0	13	0	0
T17	0	3	0	0
T18	0	3	0	0
T19	0	6	0	0
T20	0	5	0	0
T21	0	572	0	0
T22	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48744	46896	0	0
T2	46608	45120	0	0
T3	22344	21720	0	0
T4	662496	661296	0	0
T7	375504	374688	0	0
T8	1004064	1002984	0	0
T9	233928	233640	0	0
T10	185664	185352	0	0
T11	42144	41640	0	0
T12	35400	35160	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7821123	0	0
T1	48744	360	0	0
T2	46608	400	0	0
T3	22344	496	0	0
T4	662496	2716	0	0
T7	375504	1429	0	0
T8	1004064	3922	0	0
T9	233928	3728	0	0
T10	185664	3282	0	0
T11	42144	391	0	0
T12	35400	389	0	0
T13	0	190	0	0
T14	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	873280	0	0
GntImpliesValid_A	395462187	873280	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	873280	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	11994938	0	0
ReadyAndValidImplyGrant_A	395462187	873280	0	0
ReqAndReadyImplyGrant_A	395462187	873280	0	0
ReqImpliesValid_A	395462187	2517564	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	873280	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	11994938	0	0
T1	2031	35	0	0
T2	1942	36	0	0
T3	931	25	0	0
T4	27604	2340	0	0
T7	15646	356	0	0
T8	41836	2783	0	0
T9	9747	395	0	0
T10	7736	289	0	0
T11	1756	37	0	0
T12	1475	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2517564	0	0
T1	2031	64	0	0
T2	1942	59	0	0
T3	931	34	0	0
T4	27604	655	0	0
T7	15646	76	0	0
T8	41836	653	0	0
T9	9747	412	0	0
T10	7736	406	0	0
T11	1756	66	0	0
T12	1475	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	873280	0	0
T1	2031	49	0	0
T2	1942	47	0	0
T3	931	29	0	0
T4	27604	335	0	0
T7	15646	46	0	0
T8	41836	385	0	0
T9	9747	403	0	0
T10	7736	347	0	0
T11	1756	51	0	0
T12	1475	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	858896	0	0
GntImpliesValid_A	395462187	858896	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	858896	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	11737358	0	0
ReadyAndValidImplyGrant_A	395462187	858896	0	0
ReqAndReadyImplyGrant_A	395462187	858896	0	0
ReqImpliesValid_A	395462187	2356843	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	858896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	11737358	0	0
T1	2031	33	0	0
T2	1942	42	0	0
T3	931	32	0	0
T4	27604	1987	0	0
T7	15646	374	0	0
T8	41836	2702	0	0
T9	9747	405	0	0
T10	7736	265	0	0
T11	1756	35	0	0
T12	1475	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2356843	0	0
T1	2031	62	0	0
T2	1942	71	0	0
T3	931	47	0	0
T4	27604	483	0	0
T7	15646	82	0	0
T8	41836	762	0	0
T9	9747	432	0	0
T10	7736	352	0	0
T11	1756	62	0	0
T12	1475	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	858896	0	0
T1	2031	47	0	0
T2	1942	56	0	0
T3	931	39	0	0
T4	27604	289	0	0
T7	15646	53	0	0
T8	41836	394	0	0
T9	9747	418	0	0
T10	7736	308	0	0
T11	1756	48	0	0
T12	1475	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T4 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	217660	0	0
GntImpliesValid_A	395462187	217660	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	217660	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2957934	0	0
ReadyAndValidImplyGrant_A	395462187	217660	0	0
ReqAndReadyImplyGrant_A	395462187	217660	0	0
ReqImpliesValid_A	395462187	558000	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	217660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2957934	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	14	0	0
T4	27604	397	0	0
T7	15646	1	0	0
T8	41836	898	0	0
T9	9747	98	0	0
T10	7736	99	0	0
T11	1756	11	0	0
T12	1475	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	558000	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	15	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	153	0	0
T9	9747	101	0	0
T10	7736	102	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	217660	0	0
T1	2031	15	0	0
T2	1942	7	0	0
T3	931	14	0	0
T4	27604	60	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	99	0	0
T10	7736	100	0	0
T11	1756	10	0	0
T12	1475	11	0	0
T14	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	223831	0	0
GntImpliesValid_A	395462187	223831	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	223831	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2905341	0	0
ReadyAndValidImplyGrant_A	395462187	223831	0	0
ReqAndReadyImplyGrant_A	395462187	223831	0	0
ReqImpliesValid_A	395462187	597220	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	223831	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2905341	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	18	0	0
T4	27604	461	0	0
T7	15646	467	0	0
T8	41836	924	0	0
T9	9747	104	0	0
T10	7736	86	0	0
T11	1756	6	0	0
T12	1475	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	597220	0	0
T1	2031	12	0	0
T2	1942	14	0	0
T3	931	19	0	0
T4	27604	121	0	0
T7	15646	4993	0	0
T8	41836	198	0	0
T9	9747	105	0	0
T10	7736	89	0	0
T11	1756	5	0	0
T12	1475	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223831	0	0
T1	2031	11	0	0
T2	1942	11	0	0
T3	931	18	0	0
T4	27604	74	0	0
T7	15646	475	0	0
T8	41836	136	0	0
T9	9747	104	0	0
T10	7736	87	0	0
T11	1756	5	0	0
T12	1475	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	208381	0	0
GntImpliesValid_A	395462187	208381	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	208381	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	5118073	0	0
ReadyAndValidImplyGrant_A	395462187	208381	0	0
ReqAndReadyImplyGrant_A	395462187	208381	0	0
ReqImpliesValid_A	395462187	1120103	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	208381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	5118073	0	0
T1	2031	36	0	0
T2	1942	64	0	0
T3	931	53	0	0
T4	27604	1379	0	0
T7	15646	0	0	0
T8	41836	2301	0	0
T9	9747	366	0	0
T10	7736	346	0	0
T11	1756	127	0	0
T12	1475	39	0	0
T13	0	125	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	1120103	0	0
T1	2031	14	0	0
T2	1942	26	0	0
T3	931	13	0	0
T4	27604	202	0	0
T7	15646	0	0	0
T8	41836	346	0	0
T9	9747	110	0	0
T10	7736	149	0	0
T11	1756	20	0	0
T12	1475	17	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	208381	0	0
T1	2031	7	0	0
T2	1942	13	0	0
T3	931	13	0	0
T4	27604	77	0	0
T7	15646	0	0	0
T8	41836	114	0	0
T9	9747	107	0	0
T10	7736	101	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	218175	0	0
GntImpliesValid_A	395462187	218175	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	218175	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	5117711	0	0
ReadyAndValidImplyGrant_A	395462187	218175	0	0
ReqAndReadyImplyGrant_A	395462187	218175	0	0
ReqImpliesValid_A	395462187	1255115	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	218175	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	5117711	0	0
T1	2031	144	0	0
T2	1942	70	0	0
T3	931	41	0	0
T4	27604	2024	0	0
T7	15646	0	0	0
T8	41836	1691	0	0
T9	9747	342	0	0
T10	7736	425	0	0
T11	1756	92	0	0
T12	1475	43	0	0
T13	0	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	1255115	0	0
T1	2031	26	0	0
T2	1942	20	0	0
T3	931	11	0	0
T4	27604	314	0	0
T7	15646	0	0	0
T8	41836	383	0	0
T9	9747	104	0	0
T10	7736	102	0	0
T11	1756	24	0	0
T12	1475	22	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218175	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	11	0	0
T4	27604	71	0	0
T7	15646	0	0	0
T8	41836	121	0	0
T9	9747	100	0	0
T10	7736	86	0	0
T11	1756	16	0	0
T12	1475	15	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	215995	0	0
GntImpliesValid_A	395462187	215995	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	215995	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	5323433	0	0
ReadyAndValidImplyGrant_A	395462187	215995	0	0
ReqAndReadyImplyGrant_A	395462187	215995	0	0
ReqImpliesValid_A	395462187	1293636	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	215995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	5323433	0	0
T1	2031	41	0	0
T2	1942	38	0	0
T3	931	45	0	0
T4	27604	950	0	0
T7	15646	0	0	0
T8	41836	1840	0	0
T9	9747	441	0	0
T10	7736	622	0	0
T11	1756	38	0	0
T12	1475	38	0	0
T13	0	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	1293636	0	0
T1	2031	10	0	0
T2	1942	7	0	0
T3	931	18	0	0
T4	27604	164	0	0
T7	15646	0	0	0
T8	41836	172	0	0
T9	9747	109	0	0
T10	7736	147	0	0
T11	1756	24	0	0
T12	1475	21	0	0
T13	0	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215995	0	0
T1	2031	6	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	126	0	0
T9	9747	104	0	0
T10	7736	93	0	0
T11	1756	12	0	0
T12	1475	13	0	0
T13	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	222732	0	0
GntImpliesValid_A	395462187	222732	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	222732	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	4906998	0	0
ReadyAndValidImplyGrant_A	395462187	222732	0	0
ReqAndReadyImplyGrant_A	395462187	222732	0	0
ReqImpliesValid_A	395462187	1281379	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	222732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	4906998	0	0
T1	2031	84	0	0
T2	1942	40	0	0
T3	931	60	0	0
T4	27604	741	0	0
T7	15646	0	0	0
T8	41836	1307	0	0
T9	9747	432	0	0
T10	7736	446	0	0
T11	1756	37	0	0
T12	1475	33	0	0
T13	0	69	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	1281379	0	0
T1	2031	25	0	0
T2	1942	5	0	0
T3	931	24	0	0
T4	27604	95	0	0
T7	15646	0	0	0
T8	41836	197	0	0
T9	9747	129	0	0
T10	7736	122	0	0
T11	1756	19	0	0
T12	1475	10	0	0
T13	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	222732	0	0
T1	2031	6	0	0
T2	1942	5	0	0
T3	931	12	0	0
T4	27604	66	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	111	0	0
T10	7736	103	0	0
T11	1756	9	0	0
T12	1475	10	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	214637	0	0
GntImpliesValid_A	395462187	214637	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	214637	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2953048	0	0
ReadyAndValidImplyGrant_A	395462187	214637	0	0
ReqAndReadyImplyGrant_A	395462187	214637	0	0
ReqImpliesValid_A	395462187	555760	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	214637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2953048	0	0
T1	2031	14	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	518	0	0
T7	15646	1	0	0
T8	41836	744	0	0
T9	9747	87	0	0
T10	7736	78	0	0
T11	1756	8	0	0
T12	1475	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	555760	0	0
T1	2031	15	0	0
T2	1942	10	0	0
T3	931	23	0	0
T4	27604	99	0	0
T7	15646	0	0	0
T8	41836	159	0	0
T9	9747	86	0	0
T10	7736	85	0	0
T11	1756	15	0	0
T12	1475	10	0	0
T13	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	214637	0	0
T1	2031	14	0	0
T2	1942	10	0	0
T3	931	22	0	0
T4	27604	75	0	0
T7	15646	0	0	0
T8	41836	101	0	0
T9	9747	86	0	0
T10	7736	81	0	0
T11	1756	11	0	0
T12	1475	10	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T4 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	223735	0	0
GntImpliesValid_A	395462187	223735	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	223735	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2982681	0	0
ReadyAndValidImplyGrant_A	395462187	223735	0	0
ReqAndReadyImplyGrant_A	395462187	223735	0	0
ReqImpliesValid_A	395462187	635977	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	223735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2982681	0	0
T1	2031	5	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	517	0	0
T7	15646	1	0	0
T8	41836	735	0	0
T9	9747	107	0	0
T10	7736	86	0	0
T11	1756	11	0	0
T12	1475	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	635977	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	24	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	149	0	0
T9	9747	112	0	0
T10	7736	87	0	0
T11	1756	14	0	0
T12	1475	10	0	0
T13	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	223735	0	0
T1	2031	4	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	62	0	0
T7	15646	0	0	0
T8	41836	107	0	0
T9	9747	109	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	10	0	0
T13	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T4 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	207533	0	0
GntImpliesValid_A	395462187	207533	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	207533	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2868022	0	0
ReadyAndValidImplyGrant_A	395462187	207533	0	0
ReqAndReadyImplyGrant_A	395462187	207533	0	0
ReqImpliesValid_A	395462187	498653	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	207533	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2868022	0	0
T1	2031	12	0	0
T2	1942	9	0	0
T3	931	17	0	0
T4	27604	551	0	0
T7	15646	1	0	0
T8	41836	836	0	0
T9	9747	111	0	0
T10	7736	113	0	0
T11	1756	9	0	0
T12	1475	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	498653	0	0
T1	2031	11	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	110	0	0
T7	15646	0	0	0
T8	41836	145	0	0
T9	9747	112	0	0
T10	7736	132	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	207533	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	111	0	0
T10	7736	122	0	0
T11	1756	8	0	0
T12	1475	9	0	0
T13	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T8 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T8,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	205794	0	0
GntImpliesValid_A	395462187	205794	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	205794	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2919685	0	0
ReadyAndValidImplyGrant_A	395462187	205794	0	0
ReqAndReadyImplyGrant_A	395462187	205794	0	0
ReqImpliesValid_A	395462187	527325	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	205794	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2919685	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	16	0	0
T4	27604	616	0	0
T7	15646	1	0	0
T8	41836	820	0	0
T9	9747	100	0	0
T10	7736	94	0	0
T11	1756	11	0	0
T12	1475	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	527325	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	94	0	0
T7	15646	0	0	0
T8	41836	154	0	0
T9	9747	99	0	0
T10	7736	99	0	0
T11	1756	12	0	0
T12	1475	12	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	205794	0	0
T1	2031	8	0	0
T2	1942	8	0	0
T3	931	15	0	0
T4	27604	78	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	99	0	0
T10	7736	96	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T4 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	209693	0	0
GntImpliesValid_A	395462187	209693	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	209693	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2945968	0	0
ReadyAndValidImplyGrant_A	395462187	209693	0	0
ReqAndReadyImplyGrant_A	395462187	209693	0	0
ReqImpliesValid_A	395462187	550435	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	209693	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2945968	0	0
T1	2031	17	0	0
T2	1942	13	0	0
T3	931	16	0	0
T4	27604	545	0	0
T7	15646	1	0	0
T8	41836	1013	0	0
T9	9747	110	0	0
T10	7736	81	0	0
T11	1756	12	0	0
T12	1475	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	550435	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	17	0	0
T4	27604	141	0	0
T7	15646	0	0	0
T8	41836	197	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	20	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209693	0	0
T1	2031	16	0	0
T2	1942	12	0	0
T3	931	16	0	0
T4	27604	83	0	0
T7	15646	0	0	0
T8	41836	134	0	0
T9	9747	109	0	0
T10	7736	80	0	0
T11	1756	11	0	0
T12	1475	19	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T9 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	215957	0	0
GntImpliesValid_A	395462187	215957	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	215957	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2930995	0	0
ReadyAndValidImplyGrant_A	395462187	215957	0	0
ReqAndReadyImplyGrant_A	395462187	215957	0	0
ReqImpliesValid_A	395462187	570173	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	215957	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2930995	0	0
T1	2031	5	0	0
T2	1942	7	0	0
T3	931	13	0	0
T4	27604	503	0	0
T7	15646	1	0	0
T8	41836	882	0	0
T9	9747	92	0	0
T10	7736	86	0	0
T11	1756	12	0	0
T12	1475	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	570173	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	72	0	0
T7	15646	0	0	0
T8	41836	203	0	0
T9	9747	95	0	0
T10	7736	89	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	215957	0	0
T1	2031	4	0	0
T2	1942	6	0	0
T3	931	12	0	0
T4	27604	64	0	0
T7	15646	0	0	0
T8	41836	123	0	0
T9	9747	93	0	0
T10	7736	87	0	0
T11	1756	11	0	0
T12	1475	11	0	0
T13	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T8 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T8,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	231221	0	0
GntImpliesValid_A	395462187	231221	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	231221	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2976577	0	0
ReadyAndValidImplyGrant_A	395462187	231221	0	0
ReqAndReadyImplyGrant_A	395462187	231221	0	0
ReqImpliesValid_A	395462187	593603	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	231221	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2976577	0	0
T1	2031	7	0	0
T2	1942	11	0	0
T3	931	11	0	0
T4	27604	581	0	0
T7	15646	1	0	0
T8	41836	783	0	0
T9	9747	109	0	0
T10	7736	93	0	0
T11	1756	11	0	0
T12	1475	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	593603	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	113	0	0
T7	15646	0	0	0
T8	41836	152	0	0
T9	9747	108	0	0
T10	7736	102	0	0
T11	1756	14	0	0
T12	1475	5	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	231221	0	0
T1	2031	6	0	0
T2	1942	10	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	112	0	0
T9	9747	108	0	0
T10	7736	97	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T9 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	230575	0	0
GntImpliesValid_A	395462187	230575	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	230575	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2961872	0	0
ReadyAndValidImplyGrant_A	395462187	230575	0	0
ReqAndReadyImplyGrant_A	395462187	230575	0	0
ReqImpliesValid_A	395462187	633365	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	230575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2961872	0	0
T1	2031	10	0	0
T2	1942	10	0	0
T3	931	11	0	0
T4	27604	583	0	0
T7	15646	1	0	0
T8	41836	764	0	0
T9	9747	106	0	0
T10	7736	93	0	0
T11	1756	13	0	0
T12	1475	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	633365	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	123	0	0
T7	15646	0	0	0
T8	41836	132	0	0
T9	9747	107	0	0
T10	7736	96	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	230575	0	0
T1	2031	9	0	0
T2	1942	9	0	0
T3	931	10	0	0
T4	27604	79	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	106	0	0
T10	7736	94	0	0
T11	1756	12	0	0
T12	1475	5	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T4 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	235277	0	0
GntImpliesValid_A	395462187	235277	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	235277	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	3121554	0	0
ReadyAndValidImplyGrant_A	395462187	235277	0	0
ReqAndReadyImplyGrant_A	395462187	235277	0	0
ReqImpliesValid_A	395462187	623587	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	235277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	3121554	0	0
T1	2031	10	0	0
T2	1942	15	0	0
T3	931	19	0	0
T4	27604	387	0	0
T7	15646	1	0	0
T8	41836	764	0	0
T9	9747	107	0	0
T10	7736	141	0	0
T11	1756	7	0	0
T12	1475	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	623587	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	24	0	0
T4	27604	85	0	0
T7	15646	0	0	0
T8	41836	193	0	0
T9	9747	108	0	0
T10	7736	162	0	0
T11	1756	8	0	0
T12	1475	14	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	235277	0	0
T1	2031	9	0	0
T2	1942	14	0	0
T3	931	21	0	0
T4	27604	61	0	0
T7	15646	0	0	0
T8	41836	109	0	0
T9	9747	107	0	0
T10	7736	151	0	0
T11	1756	7	0	0
T12	1475	14	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T4 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	209173	0	0
GntImpliesValid_A	395462187	209173	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	209173	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2936995	0	0
ReadyAndValidImplyGrant_A	395462187	209173	0	0
ReqAndReadyImplyGrant_A	395462187	209173	0	0
ReqImpliesValid_A	395462187	537403	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	209173	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2936995	0	0
T1	2031	6	0	0
T2	1942	11	0	0
T3	931	23	0	0
T4	27604	642	0	0
T7	15646	1	0	0
T8	41836	794	0	0
T9	9747	116	0	0
T10	7736	92	0	0
T11	1756	11	0	0
T12	1475	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	537403	0	0
T1	2031	5	0	0
T2	1942	12	0	0
T3	931	22	0	0
T4	27604	93	0	0
T7	15646	0	0	0
T8	41836	122	0	0
T9	9747	115	0	0
T10	7736	95	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	209173	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	22	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	106	0	0
T9	9747	115	0	0
T10	7736	93	0	0
T11	1756	10	0	0
T12	1475	6	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T9 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	218536	0	0
GntImpliesValid_A	395462187	218536	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	218536	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2981382	0	0
ReadyAndValidImplyGrant_A	395462187	218536	0	0
ReqAndReadyImplyGrant_A	395462187	218536	0	0
ReqImpliesValid_A	395462187	569210	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	218536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2981382	0	0
T1	2031	5	0	0
T2	1942	11	0	0
T3	931	17	0	0
T4	27604	595	0	0
T7	15646	1	0	0
T8	41836	814	0	0
T9	9747	106	0	0
T10	7736	105	0	0
T11	1756	14	0	0
T12	1475	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	569210	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	146	0	0
T7	15646	0	0	0
T8	41836	195	0	0
T9	9747	107	0	0
T10	7736	110	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218536	0	0
T1	2031	4	0	0
T2	1942	10	0	0
T3	931	16	0	0
T4	27604	82	0	0
T7	15646	0	0	0
T8	41836	115	0	0
T9	9747	106	0	0
T10	7736	107	0	0
T11	1756	13	0	0
T12	1475	7	0	0
T13	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T4 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	213817	0	0
GntImpliesValid_A	395462187	213817	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	213817	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2943116	0	0
ReadyAndValidImplyGrant_A	395462187	213817	0	0
ReqAndReadyImplyGrant_A	395462187	213817	0	0
ReqImpliesValid_A	395462187	561454	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	213817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2943116	0	0
T1	2031	11	0	0
T2	1942	17	0	0
T3	931	15	0	0
T4	27604	467	0	0
T7	15646	1	0	0
T8	41836	683	0	0
T9	9747	106	0	0
T10	7736	84	0	0
T11	1756	6	0	0
T12	1475	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	561454	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	16	0	0
T4	27604	76	0	0
T7	15646	0	0	0
T8	41836	104	0	0
T9	9747	111	0	0
T10	7736	87	0	0
T11	1756	7	0	0
T12	1475	9	0	0
T13	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	213817	0	0
T1	2031	10	0	0
T2	1942	16	0	0
T3	931	15	0	0
T4	27604	65	0	0
T7	15646	0	0	0
T8	41836	90	0	0
T9	9747	108	0	0
T10	7736	85	0	0
T11	1756	6	0	0
T12	1475	8	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T4 T8 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T8,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	218746	0	0
GntImpliesValid_A	395462187	218746	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	218746	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2970178	0	0
ReadyAndValidImplyGrant_A	395462187	218746	0	0
ReqAndReadyImplyGrant_A	395462187	218746	0	0
ReqImpliesValid_A	395462187	596805	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	218746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2970178	0	0
T1	2031	11	0	0
T2	1942	9	0	0
T3	931	14	0	0
T4	27604	475	0	0
T7	15646	1	0	0
T8	41836	636	0	0
T9	9747	123	0	0
T10	7736	99	0	0
T11	1756	11	0	0
T12	1475	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	596805	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	80	0	0
T7	15646	0	0	0
T8	41836	91	0	0
T9	9747	122	0	0
T10	7736	104	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	218746	0	0
T1	2031	10	0	0
T2	1942	8	0	0
T3	931	13	0	0
T4	27604	70	0	0
T7	15646	0	0	0
T8	41836	88	0	0
T9	9747	122	0	0
T10	7736	101	0	0
T11	1756	10	0	0
T12	1475	10	0	0
T13	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	219810	0	0
GntImpliesValid_A	395462187	219810	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	219810	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	2924185	0	0
ReadyAndValidImplyGrant_A	395462187	219810	0	0
ReqAndReadyImplyGrant_A	395462187	219810	0	0
ReqImpliesValid_A	395462187	584638	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	0	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	219810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2924185	0	0
T1	2031	16	0	0
T2	1942	9	0	0
T3	931	17	0	0
T4	27604	598	0	0
T7	15646	1	0	0
T8	41836	983	0	0
T9	9747	105	0	0
T10	7736	81	0	0
T11	1756	12	0	0
T12	1475	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	584638	0	0
T1	2031	17	0	0
T2	1942	8	0	0
T3	931	18	0	0
T4	27604	126	0	0
T7	15646	0	0	0
T8	41836	169	0	0
T9	9747	106	0	0
T10	7736	86	0	0
T11	1756	11	0	0
T12	1475	16	0	0
T13	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	219810	0	0
T1	2031	16	0	0
T2	1942	8	0	0
T3	931	17	0	0
T4	27604	88	0	0
T7	15646	0	0	0
T8	41836	119	0	0
T9	9747	105	0	0
T10	7736	83	0	0
T11	1756	11	0	0
T12	1475	15	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T4 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T4,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	866041	0	0
GntImpliesValid_A	395462187	866041	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	866041	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	11180346	0	0
ReadyAndValidImplyGrant_A	395462187	866041	0	0
ReqAndReadyImplyGrant_A	395462187	866041	0	0
ReqImpliesValid_A	395462187	2224157	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	17705	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	866041	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	11180346	0	0
T1	2031	1	0	0
T2	1942	1	0	0
T3	931	1	0	0
T4	27604	1886	0	0
T7	15646	1713	0	0
T8	41836	2765	0	0
T9	9747	1	0	0
T10	7736	1	0	0
T11	1756	1	0	0
T12	1475	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	2224157	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	453	0	0
T7	15646	2651	0	0
T8	41836	654	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	17705	0	900
T3	931	3	0	1
T4	27604	0	0	1
T7	15646	61	0	1
T8	41836	0	0	1
T9	9747	7	0	1
T10	7736	6	0	1
T11	1756	0	0	1
T12	1475	0	0	1
T13	204427	0	0	1
T14	68392	0	0	1
T15	0	22	0	0
T16	0	7	0	0
T19	0	6	0	0
T20	0	5	0	0
T21	0	572	0	0
T22	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	866041	0	0
T1	2031	51	0	0
T2	1942	48	0	0
T3	931	68	0	0
T4	27604	288	0	0
T7	15646	807	0	0
T8	41836	450	0	0
T9	9747	389	0	0
T10	7736	338	0	0
T11	1756	34	0	0
T12	1475	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T4 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T4,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395462187	395328290	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395462187	861628	0	0
GntImpliesValid_A	395462187	861628	0	0
GrantKnown_A	395462187	395328290	0	0
IdxKnown_A	395462187	395328290	0	0
IndexIsCorrect_A	395462187	861628	0	0
LockArbDecision_A	395462187	0	0	0
NoReadyValidNoGrant_A	395462187	332288578	0	0
ReadyAndValidImplyGrant_A	395462187	861628	0	0
ReqAndReadyImplyGrant_A	395462187	861628	0	0
ReqImpliesValid_A	395462187	13053140	0	0
ReqStaysHighUntilGranted0_M	395462187	0	0	0
RoundRobin_A	395462187	22669	0	900
ValidKnown_A	395462187	395328290	0	0
gen_data_port_assertion.DataFlow_A	395462187	861628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	332288578	0	0
T1	2031	1	0	0
T2	1942	1	0	0
T3	931	1	0	0
T4	27604	21689	0	0
T7	15646	13899	0	0
T8	41836	35009	0	0
T9	9747	1	0	0
T10	7736	1	0	0
T11	1756	1	0	0
T12	1475	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	13053140	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	2703	0	0
T7	15646	341	0	0
T8	41836	3385	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	22669	0	900
T3	931	2	0	1
T4	27604	2	0	1
T7	15646	0	0	1
T8	41836	1	0	1
T9	9747	5	0	1
T10	7736	2	0	1
T11	1756	0	0	1
T12	1475	0	0	1
T13	204427	0	0	1
T14	68392	1	0	1
T15	0	11	0	0
T16	0	6	0	0
T17	0	3	0	0
T18	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	395328290	0	0
T1	2031	1954	0	0
T2	1942	1880	0	0
T3	931	905	0	0
T4	27604	27554	0	0
T7	15646	15612	0	0
T8	41836	41791	0	0
T9	9747	9735	0	0
T10	7736	7723	0	0
T11	1756	1735	0	0
T12	1475	1465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395462187	861628	0	0
T1	2031	31	0	0
T2	1942	51	0	0
T3	931	55	0	0
T4	27604	357	0	0
T7	15646	48	0	0
T8	41836	414	0	0
T9	9747	409	0	0
T10	7736	356	0	0
T11	1756	49	0	0
T12	1475	35	0	0