Unified Coverage Report :: Module :: tlul_socket_1n

Module : tlul_socket_1n

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.23	100.00	96.90			100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_57	97.92	100.00	91.67			100.00	100.00
tb.dut.u_s1n_32	98.80	100.00	95.19			100.00	100.00
tb.dut.u_s1n_27	99.65	100.00	98.61			100.00	100.00

Line Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Line Coverage for Module self-instances :

SCORE	LINE
99.65	100.00

tb.dut.u_s1n_27

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	180	6	6	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	192	4	4	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00

111                     
112        1/1            assign  accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
           Tests:       T1 T2 T3 
113        1/1            assign  accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
           Tests:       T1 T2 T3 
114                     
115                       always_ff @(posedge clk_i or negedge rst_ni) begin
116        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
117        1/1                num_req_outstanding <= '0;
           Tests:       T1 T2 T3 
118        1/1                dev_select_outstanding <= '0;
           Tests:       T1 T2 T3 
119        1/1              end else if (accept_t_req) begin
           Tests:       T1 T2 T3 
120        1/1                if (!accept_t_rsp) begin
           Tests:       T1 T2 T3 
121        1/1                  num_req_outstanding <= num_req_outstanding + 1'b1;
           Tests:       T1 T2 T3 
122                           end
                        MISSING_ELSE
123        1/1                dev_select_outstanding <= dev_select_t;
           Tests:       T1 T2 T3 
124        1/1              end else if (accept_t_rsp) begin
           Tests:       T1 T2 T3 
125        1/1                num_req_outstanding <= num_req_outstanding - 1'b1;
           Tests:       T1 T2 T3 
126                         end
                        MISSING_ELSE
127                       end
128                     
129                       `ASSERT(NotOverflowed_A,
130                               accept_t_req && !accept_t_rsp -> num_req_outstanding <= MaxOutstanding)
131                     
132        1/1            assign hold_all_requests =
           Tests:       T1 T2 T3 
133                           (num_req_outstanding != '0) &
134                           (dev_select_t != dev_select_outstanding);
135                     
136                       // Make N copies of 't' request side with modified reqvalid, call
137                       // them 'u[0]' .. 'u[n-1]'.
138                     
139                       tlul_pkg::tl_h2d_t   tl_u_o [N+1];
140                       tlul_pkg::tl_d2h_t   tl_u_i [N+1];
141                     
142                       // ensure that when a device is not selected, both command
143                       // data integrity can never match
144                       tlul_pkg::tl_a_user_t blanked_auser;
145        1/1            assign blanked_auser = '{
           Tests:       T1 T2 T3 
146                         rsvd: tl_t_o.a_user.rsvd,
147                         instr_type: tl_t_o.a_user.instr_type,
148                         cmd_intg: tlul_pkg::get_bad_cmd_intg(tl_t_o),
149                         data_intg: tlul_pkg::get_bad_data_intg(tlul_pkg::BlankedAData)
150                       };
151                     
152                       // if a host is not selected, or if requests are held off, blank the bus
153                       for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
154                         logic dev_select;
155        4/4              assign dev_select = dev_select_t == NWD'(i) & ~hold_all_requests;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156                     
157        4/4              assign tl_u_o[i].a_valid   = tl_t_o.a_valid & dev_select;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
158        4/4              assign tl_u_o[i].a_opcode  = tl_t_o.a_opcode;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
159        4/4              assign tl_u_o[i].a_param   = tl_t_o.a_param;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
160        4/4              assign tl_u_o[i].a_size    = tl_t_o.a_size;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        4/4              assign tl_u_o[i].a_source  = tl_t_o.a_source;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162        4/4              assign tl_u_o[i].a_address = tl_t_o.a_address;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
163        4/4              assign tl_u_o[i].a_mask    = tl_t_o.a_mask;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164        4/4              assign tl_u_o[i].a_data    = dev_select ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                                                      tl_t_o.a_data :
166                                                      tlul_pkg::BlankedAData;
167        4/4              assign tl_u_o[i].a_user    = dev_select ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
168                                                      tl_t_o.a_user :
169                                                      blanked_auser;
170                     
171        4/4              assign tl_u_o[i].d_ready   = tl_t_o.d_ready;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
172                       end
173                     
174                     
175                       tlul_pkg::tl_d2h_t tl_t_p ;
176                     
177                       // for the returning reqready, only look at the device we're addressing
178                       logic hfifo_reqready;
179                       always_comb begin
180        1/1              hfifo_reqready = tl_u_i[N].a_ready; // default to error
           Tests:       T1 T2 T3 
181        1/1              for (int idx = 0 ; idx < N ; idx++) begin
           Tests:       T1 T2 T3 
182                           //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
183        2/2                if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
184                         end
185        2/2              if (hold_all_requests) hfifo_reqready = 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
186                       end
187                       // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
188                       // when the address is unknown and the Host TL-UL FIFO is bypass mode.
189        1/1            assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
           Tests:       T1 T2 T3 
190                     
191                       always_comb begin
192        1/1              tl_t_p = tl_u_i[N];
           Tests:       T1 T2 T3 
193        1/1              for (int idx = 0 ; idx < N ; idx++) begin
           Tests:       T1 T2 T3 
194        2/2                if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
195                         end
196                       end
197        1/1            assign tl_t_i.d_valid  = tl_t_p.d_valid ;
           Tests:       T1 T2 T3 
198        1/1            assign tl_t_i.d_opcode = tl_t_p.d_opcode;
           Tests:       T1 T2 T3 
199        1/1            assign tl_t_i.d_param  = tl_t_p.d_param ;
           Tests:       T1 T2 T3 
200        1/1            assign tl_t_i.d_size   = tl_t_p.d_size  ;
           Tests:       T1 T2 T3 
201        1/1            assign tl_t_i.d_source = tl_t_p.d_source;
           Tests:       T1 T2 T3 
202        1/1            assign tl_t_i.d_sink   = tl_t_p.d_sink  ;
           Tests:       T1 T2 T3 
203        1/1            assign tl_t_i.d_data   = tl_t_p.d_data  ;
           Tests:       T1 T2 T3 
204        1/1            assign tl_t_i.d_user   = tl_t_p.d_user  ;
           Tests:       T1 T2 T3 
205        1/1            assign tl_t_i.d_error  = tl_t_p.d_error ;
           Tests:       T1 T2 T3 
206                     
207                       // Instantiate all the device FIFOs
208                       for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
209                         tlul_fifo_sync #(
210                           .ReqPass(DReqPass[i]),
211                           .RspPass(DRspPass[i]),
212                           .ReqDepth(DReqDepth[i*4+:4]),
213                           .RspDepth(DRspDepth[i*4+:4])
214                         ) fifo_d (
215                           .clk_i,
216                           .rst_ni,
217                           .tl_h_i      (tl_u_o[i]),
218                           .tl_h_o      (tl_u_i[i]),
219                           .tl_d_o      (tl_d_o[i]),
220                           .tl_d_i      (tl_d_i[i]),
221                           .spare_req_i (1'b0),
222                           .spare_req_o (),
223                           .spare_rsp_i (1'b0),
224                           .spare_rsp_o ());
225                       end
226                     
227                       // Instantiate the error responder. It's only needed if a value greater than
228                       // N-1 is actually representable in NWD bits.
229                       if ($clog2(N+1) <= NWD) begin : gen_err_resp
230        1/1              assign tl_u_o[N].d_ready     = tl_t_o.d_ready;
           Tests:       T1 T2 T3 
231        1/1              assign tl_u_o[N].a_valid     = tl_t_o.a_valid &
           Tests:       T1 T2 T3 
232                                                        (dev_select_t >= NWD'(N)) &
233                                                        ~hold_all_requests;
234        1/1              assign tl_u_o[N].a_opcode    = tl_t_o.a_opcode;
           Tests:       T1 T2 T3 
235        1/1              assign tl_u_o[N].a_param     = tl_t_o.a_param;
           Tests:       T1 T2 T3 
236        1/1              assign tl_u_o[N].a_size      = tl_t_o.a_size;
           Tests:       T1 T2 T3 
237        1/1              assign tl_u_o[N].a_source    = tl_t_o.a_source;
           Tests:       T1 T2 T3 
238        1/1              assign tl_u_o[N].a_address   = tl_t_o.a_address;
           Tests:       T1 T2 T3 
239        1/1              assign tl_u_o[N].a_mask      = tl_t_o.a_mask;
           Tests:       T1 T2 T3 
240        1/1              assign tl_u_o[N].a_data      = tl_t_o.a_data;
           Tests:       T1 T2 T3 
241        1/1              assign tl_u_o[N].a_user      = tl_t_o.a_user;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Line Coverage for Module self-instances :

SCORE	LINE
98.80	100.00

tb.dut.u_s1n_32

SCORE	LINE
97.92	100.00

tb.dut.u_s1n_57

	Line No.	Total	Covered	Percent
TOTAL		307	307	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	180	6	6	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	192	4	4	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00

111                     
112        1/1            assign  accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
           Tests:       T1 T2 T3 
113        1/1            assign  accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
           Tests:       T1 T2 T3 
114                     
115                       always_ff @(posedge clk_i or negedge rst_ni) begin
116        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
117        1/1                num_req_outstanding <= '0;
           Tests:       T1 T2 T3 
118        1/1                dev_select_outstanding <= '0;
           Tests:       T1 T2 T3 
119        1/1              end else if (accept_t_req) begin
           Tests:       T1 T2 T3 
120        1/1                if (!accept_t_rsp) begin
           Tests:       T1 T2 T3 
121        1/1                  num_req_outstanding <= num_req_outstanding + 1'b1;
           Tests:       T1 T2 T3 
122                           end
                        MISSING_ELSE
123        1/1                dev_select_outstanding <= dev_select_t;
           Tests:       T1 T2 T3 
124        1/1              end else if (accept_t_rsp) begin
           Tests:       T1 T2 T3 
125        1/1                num_req_outstanding <= num_req_outstanding - 1'b1;
           Tests:       T1 T2 T3 
126                         end
                        MISSING_ELSE
127                       end
128                     
129                       `ASSERT(NotOverflowed_A,
130                               accept_t_req && !accept_t_rsp -> num_req_outstanding <= MaxOutstanding)
131                     
132        1/1            assign hold_all_requests =
           Tests:       T1 T2 T3 
133                           (num_req_outstanding != '0) &
134                           (dev_select_t != dev_select_outstanding);
135                     
136                       // Make N copies of 't' request side with modified reqvalid, call
137                       // them 'u[0]' .. 'u[n-1]'.
138                     
139                       tlul_pkg::tl_h2d_t   tl_u_o [N+1];
140                       tlul_pkg::tl_d2h_t   tl_u_i [N+1];
141                     
142                       // ensure that when a device is not selected, both command
143                       // data integrity can never match
144                       tlul_pkg::tl_a_user_t blanked_auser;
145        1/1            assign blanked_auser = '{
           Tests:       T1 T2 T3 
146                         rsvd: tl_t_o.a_user.rsvd,
147                         instr_type: tl_t_o.a_user.instr_type,
148                         cmd_intg: tlul_pkg::get_bad_cmd_intg(tl_t_o),
149                         data_intg: tlul_pkg::get_bad_data_intg(tlul_pkg::BlankedAData)
150                       };
151                     
152                       // if a host is not selected, or if requests are held off, blank the bus
153                       for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
154                         logic dev_select;
155        24/24            assign dev_select = dev_select_t == NWD'(i) & ~hold_all_requests;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
156                     
157        24/24            assign tl_u_o[i].a_valid   = tl_t_o.a_valid & dev_select;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
158        24/24            assign tl_u_o[i].a_opcode  = tl_t_o.a_opcode;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
159        24/24            assign tl_u_o[i].a_param   = tl_t_o.a_param;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
160        24/24            assign tl_u_o[i].a_size    = tl_t_o.a_size;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
161        24/24            assign tl_u_o[i].a_source  = tl_t_o.a_source;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
162        24/24            assign tl_u_o[i].a_address = tl_t_o.a_address;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
163        24/24            assign tl_u_o[i].a_mask    = tl_t_o.a_mask;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
164        24/24            assign tl_u_o[i].a_data    = dev_select ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
165                                                      tl_t_o.a_data :
166                                                      tlul_pkg::BlankedAData;
167        24/24            assign tl_u_o[i].a_user    = dev_select ?
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
168                                                      tl_t_o.a_user :
169                                                      blanked_auser;
170                     
171        24/24            assign tl_u_o[i].d_ready   = tl_t_o.d_ready;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
172                       end
173                     
174                     
175                       tlul_pkg::tl_d2h_t tl_t_p ;
176                     
177                       // for the returning reqready, only look at the device we're addressing
178                       logic hfifo_reqready;
179                       always_comb begin
180        1/1              hfifo_reqready = tl_u_i[N].a_ready; // default to error
           Tests:       T1 T2 T3 
181        1/1              for (int idx = 0 ; idx < N ; idx++) begin
           Tests:       T1 T2 T3 
182                           //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
183        2/2                if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
184                         end
185        2/2              if (hold_all_requests) hfifo_reqready = 1'b0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
186                       end
187                       // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
188                       // when the address is unknown and the Host TL-UL FIFO is bypass mode.
189        1/1            assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
           Tests:       T1 T2 T3 
190                     
191                       always_comb begin
192        1/1              tl_t_p = tl_u_i[N];
           Tests:       T1 T2 T3 
193        1/1              for (int idx = 0 ; idx < N ; idx++) begin
           Tests:       T1 T2 T3 
194        2/2                if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
195                         end
196                       end
197        1/1            assign tl_t_i.d_valid  = tl_t_p.d_valid ;
           Tests:       T1 T2 T3 
198        1/1            assign tl_t_i.d_opcode = tl_t_p.d_opcode;
           Tests:       T1 T2 T3 
199        1/1            assign tl_t_i.d_param  = tl_t_p.d_param ;
           Tests:       T1 T2 T3 
200        1/1            assign tl_t_i.d_size   = tl_t_p.d_size  ;
           Tests:       T1 T2 T3 
201        1/1            assign tl_t_i.d_source = tl_t_p.d_source;
           Tests:       T1 T2 T3 
202        1/1            assign tl_t_i.d_sink   = tl_t_p.d_sink  ;
           Tests:       T1 T2 T3 
203        1/1            assign tl_t_i.d_data   = tl_t_p.d_data  ;
           Tests:       T1 T2 T3 
204        1/1            assign tl_t_i.d_user   = tl_t_p.d_user  ;
           Tests:       T1 T2 T3 
205        1/1            assign tl_t_i.d_error  = tl_t_p.d_error ;
           Tests:       T1 T2 T3 
206                     
207                       // Instantiate all the device FIFOs
208                       for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
209                         tlul_fifo_sync #(
210                           .ReqPass(DReqPass[i]),
211                           .RspPass(DRspPass[i]),
212                           .ReqDepth(DReqDepth[i*4+:4]),
213                           .RspDepth(DRspDepth[i*4+:4])
214                         ) fifo_d (
215                           .clk_i,
216                           .rst_ni,
217                           .tl_h_i      (tl_u_o[i]),
218                           .tl_h_o      (tl_u_i[i]),
219                           .tl_d_o      (tl_d_o[i]),
220                           .tl_d_i      (tl_d_i[i]),
221                           .spare_req_i (1'b0),
222                           .spare_req_o (),
223                           .spare_rsp_i (1'b0),
224                           .spare_rsp_o ());
225                       end
226                     
227                       // Instantiate the error responder. It's only needed if a value greater than
228                       // N-1 is actually representable in NWD bits.
229                       if ($clog2(N+1) <= NWD) begin : gen_err_resp
230        1/1              assign tl_u_o[N].d_ready     = tl_t_o.d_ready;
           Tests:       T1 T2 T3 
231        1/1              assign tl_u_o[N].a_valid     = tl_t_o.a_valid &
           Tests:       T1 T2 T3 
232                                                        (dev_select_t >= NWD'(N)) &
233                                                        ~hold_all_requests;
234        1/1              assign tl_u_o[N].a_opcode    = tl_t_o.a_opcode;
           Tests:       T1 T2 T3 
235        1/1              assign tl_u_o[N].a_param     = tl_t_o.a_param;
           Tests:       T1 T2 T3 
236        1/1              assign tl_u_o[N].a_size      = tl_t_o.a_size;
           Tests:       T1 T2 T3 
237        1/1              assign tl_u_o[N].a_source    = tl_t_o.a_source;
           Tests:       T1 T2 T3 
238        1/1              assign tl_u_o[N].a_address   = tl_t_o.a_address;
           Tests:       T1 T2 T3 
239        1/1              assign tl_u_o[N].a_mask      = tl_t_o.a_mask;
           Tests:       T1 T2 T3 
240        1/1              assign tl_u_o[N].a_data      = tl_t_o.a_data;
           Tests:       T1 T2 T3 
241        1/1              assign tl_u_o[N].a_user      = tl_t_o.a_user;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Cond Coverage for Module self-instances :

SCORE	COND
99.65	98.61

tb.dut.u_s1n_27

	Total	Covered	Percent
Conditions	72	71	98.61
Logical	72	71	98.61
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(0))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(1))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(2))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(3))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T25,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 3'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 3'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 3'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T10,T14,T15
1	1	1	Covered	T1,T7,T4

---

Cond Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Cond Coverage for Module self-instances :

SCORE	COND
98.80	95.19

tb.dut.u_s1n_32

SCORE	COND
97.92	91.67

tb.dut.u_s1n_57

	Total	Covered	Percent
Conditions	312	297	95.19
Logical	312	297	95.19
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
112-167	94.85
167-231	100.00

---

Branch Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.65	100.00

tb.dut.u_s1n_27

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
IF	116	5	5	100.00
IF	183	2	2	100.00
IF	185	2	2	100.00
IF	194	2	2	100.00

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

116            if (!rst_ni) begin
               -1-  
117              num_req_outstanding <= '0;
                 ==>
118              dev_select_outstanding <= '0;
119            end else if (accept_t_req) begin
                        -2-  
120              if (!accept_t_rsp) begin
                 -3-  
121                num_req_outstanding <= num_req_outstanding + 1'b1;
                   ==>
122              end
                 MISSING_ELSE
                 ==>
123              dev_select_outstanding <= dev_select_t;
124            end else if (accept_t_rsp) begin
                        -4-  
125              num_req_outstanding <= num_req_outstanding - 1'b1;
                 ==>
126            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Covered	T1,T2,T3
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

183              if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
                 -1-                                 
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

185            if (hold_all_requests) hfifo_reqready = 1'b0;
               -1-                         
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

194              if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
                 -1-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.80	100.00

tb.dut.u_s1n_32

SCORE	BRANCH
97.92	100.00

tb.dut.u_s1n_57

	Line No.	Total	Covered	Percent
Branches		107	107	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
IF	116	5	5	100.00
IF	183	2	2	100.00
IF	185	2	2	100.00
IF	194	2	2	100.00

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

164            assign tl_u_o[i].a_data    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign tl_u_o[i].a_user    = dev_select ?
                                                       -1-  
                                                       ==>  
                                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

116            if (!rst_ni) begin
               -1-  
117              num_req_outstanding <= '0;
                 ==>
118              dev_select_outstanding <= '0;
119            end else if (accept_t_req) begin
                        -2-  
120              if (!accept_t_rsp) begin
                 -3-  
121                num_req_outstanding <= num_req_outstanding + 1'b1;
                   ==>
122              end
                 MISSING_ELSE
                 ==>
123              dev_select_outstanding <= dev_select_t;
124            end else if (accept_t_rsp) begin
                        -4-  
125              num_req_outstanding <= num_req_outstanding - 1'b1;
                 ==>
126            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Covered	T1,T2,T3
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

183              if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
                 -1-                                 
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

185            if (hold_all_requests) hfifo_reqready = 1'b0;
               -1-                         
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

194              if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
                 -1-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_1n

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NotOverflowed_A	1186386561	1185984870	0	0
maxN	2700	2700	0	0

NotOverflowed_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186386561	1185984870	0	0
T1	6093	5862	0	0
T2	5826	5640	0	0
T3	2793	2715	0	0
T4	82812	82662	0	0
T7	46938	46836	0	0
T8	125508	125373	0	0
T9	29241	29205	0	0
T10	23208	23169	0	0
T11	5268	5205	0	0
T12	4425	4395	0	0

maxN

Name	Attempts	Real Successes	Failures	Incomplete
Total	2700	2700	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0
T12	3	3	0	0