Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1459706 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 231130 1 T1 9 T2 29 T3 246


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 573752 1 T1 34 T2 53 T3 569
values[0x0] 541734 1 T1 28 T2 42 T3 614
values[0x1] 575350 1 T1 29 T2 49 T3 612


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1127511 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 563325 1 T1 28 T2 52 T3 565


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26807 1 T3 14 T7 2 T8 36
valid_sources[0x01] 25466 1 T3 20 T7 1 T8 39
valid_sources[0x02] 27221 1 T3 10 T7 2 T8 50
valid_sources[0x03] 26342 1 T3 12 T7 1 T8 29
valid_sources[0x04] 26244 1 T3 16 T8 40 T9 1
valid_sources[0x05] 26047 1 T3 27 T7 1 T8 38
valid_sources[0x06] 25524 1 T3 18 T7 2 T8 33
valid_sources[0x07] 26287 1 T3 58 T7 3 T8 37
valid_sources[0x08] 26503 1 T3 43 T7 3 T8 37
valid_sources[0x09] 27210 1 T3 10 T7 1 T8 32
valid_sources[0x0a] 26754 1 T3 18 T7 4 T8 27
valid_sources[0x0b] 25162 1 T3 34 T7 2 T8 40
valid_sources[0x0c] 26608 1 T3 70 T7 3 T8 43
valid_sources[0x0d] 26012 1 T3 23 T8 53 T9 1
valid_sources[0x0e] 26619 1 T3 49 T7 1 T8 55
valid_sources[0x0f] 25744 1 T3 49 T7 1 T8 38
valid_sources[0x10] 26728 1 T3 5 T7 2 T8 32
valid_sources[0x11] 26462 1 T3 10 T7 1 T8 39
valid_sources[0x12] 27424 1 T1 27 T2 19 T3 15
valid_sources[0x13] 26155 1 T1 3 T3 16 T7 1
valid_sources[0x14] 25975 1 T3 26 T7 1 T8 49
valid_sources[0x15] 26703 1 T3 16 T7 3 T8 33
valid_sources[0x16] 26986 1 T3 3 T8 39 T9 7
valid_sources[0x17] 26809 1 T3 4 T7 2 T8 49
valid_sources[0x18] 25835 1 T3 11 T8 40 T9 1
valid_sources[0x19] 27366 1 T3 12 T7 6 T8 33
valid_sources[0x1a] 26244 1 T1 1 T2 8 T3 89
valid_sources[0x1b] 26344 1 T3 14 T7 1 T8 46
valid_sources[0x1c] 26270 1 T3 19 T7 2 T8 28
valid_sources[0x1d] 26130 1 T3 6 T7 2 T8 46
valid_sources[0x1e] 26231 1 T2 11 T3 31 T8 37
valid_sources[0x1f] 26403 1 T2 14 T3 13 T7 2
valid_sources[0x20] 26504 1 T1 8 T3 23 T8 52


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24267 1 T1 3 T2 5 T3 22
values[0x0] all_enables biggest_size 182394 1 T1 6 T2 20 T3 203
values[0x1] all_enables biggest_size 24469 1 T2 4 T3 21 T7 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1475372 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 240505 1 T1 16 T2 24 T3 266


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 587746 1 T1 57 T2 53 T3 619
values[0x0] 540667 1 T1 47 T2 59 T3 618
values[0x1] 587464 1 T1 42 T2 59 T3 568


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1132310 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 583567 1 T1 43 T2 47 T3 607


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27117 1 T2 2 T3 23 T7 14
valid_sources[0x01] 27092 1 T1 7 T2 1 T3 35
valid_sources[0x02] 26519 1 T2 2 T3 31 T8 57
valid_sources[0x03] 27102 1 T2 9 T3 31 T7 3
valid_sources[0x04] 27030 1 T1 3 T2 8 T3 39
valid_sources[0x05] 26626 1 T1 4 T2 4 T3 27
valid_sources[0x06] 26854 1 T1 1 T2 2 T3 31
valid_sources[0x07] 26161 1 T1 2 T3 32 T7 1
valid_sources[0x08] 26492 1 T2 3 T3 30 T8 42
valid_sources[0x09] 26836 1 T2 1 T3 30 T7 9
valid_sources[0x0a] 26476 1 T2 4 T3 33 T7 4
valid_sources[0x0b] 26024 1 T2 1 T3 27 T8 44
valid_sources[0x0c] 26950 1 T1 13 T2 6 T3 27
valid_sources[0x0d] 27377 1 T1 4 T2 1 T3 19
valid_sources[0x0e] 26721 1 T2 8 T3 30 T7 1
valid_sources[0x0f] 26444 1 T2 3 T3 32 T8 42
valid_sources[0x10] 26055 1 T2 6 T3 29 T7 2
valid_sources[0x11] 27625 1 T3 19 T8 51 T12 37
valid_sources[0x12] 27088 1 T3 28 T7 2 T8 38
valid_sources[0x13] 27024 1 T1 16 T2 3 T3 29
valid_sources[0x14] 26568 1 T1 20 T2 2 T3 28
valid_sources[0x15] 26281 1 T2 1 T3 23 T7 1
valid_sources[0x16] 27007 1 T3 34 T7 1 T8 54
valid_sources[0x17] 26805 1 T2 7 T3 40 T8 30
valid_sources[0x18] 26477 1 T2 1 T3 14 T7 6
valid_sources[0x19] 27213 1 T1 3 T2 3 T3 29
valid_sources[0x1a] 26612 1 T2 1 T3 24 T7 4
valid_sources[0x1b] 26458 1 T1 4 T2 7 T3 27
valid_sources[0x1c] 26511 1 T3 26 T7 3 T8 42
valid_sources[0x1d] 26808 1 T3 26 T7 7 T8 36
valid_sources[0x1e] 26690 1 T2 2 T3 30 T7 10
valid_sources[0x1f] 27245 1 T3 31 T7 7 T8 50
valid_sources[0x20] 27437 1 T1 17 T2 2 T3 18


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25312 1 T1 2 T2 3 T3 22
values[0x0] all_enables biggest_size 189788 1 T1 14 T2 19 T3 225
values[0x1] all_enables biggest_size 25405 1 T2 2 T3 19 T7 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1470150 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 233459 1 T1 12 T2 20 T3 224


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 578681 1 T1 42 T2 43 T3 529
values[0x0] 546905 1 T1 35 T2 34 T3 528
values[0x1] 578023 1 T1 41 T2 37 T3 581


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1137248 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 566361 1 T1 38 T2 39 T3 508


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26644 1 T3 6 T8 55 T9 1
valid_sources[0x01] 25962 1 T2 3 T3 22 T8 53
valid_sources[0x02] 25992 1 T1 1 T3 8 T8 34
valid_sources[0x03] 25821 1 T3 17 T8 30 T11 1
valid_sources[0x04] 26930 1 T3 27 T7 7 T8 53
valid_sources[0x05] 26555 1 T2 2 T8 30 T9 3
valid_sources[0x06] 26644 1 T1 10 T3 51 T7 1
valid_sources[0x07] 27072 1 T2 5 T3 56 T8 30
valid_sources[0x08] 26624 1 T1 4 T2 3 T3 45
valid_sources[0x09] 26831 1 T1 1 T2 5 T8 50
valid_sources[0x0a] 25921 1 T3 27 T8 48 T9 3
valid_sources[0x0b] 25759 1 T1 6 T3 93 T7 6
valid_sources[0x0c] 26509 1 T3 4 T8 35 T9 2
valid_sources[0x0d] 26559 1 T1 5 T2 1 T3 41
valid_sources[0x0e] 26611 1 T1 3 T3 34 T8 70
valid_sources[0x0f] 26237 1 T1 1 T2 4 T3 35
valid_sources[0x10] 26012 1 T3 30 T7 2 T8 47
valid_sources[0x11] 26811 1 T1 3 T3 25 T8 44
valid_sources[0x12] 27189 1 T1 1 T3 7 T8 43
valid_sources[0x13] 26429 1 T1 2 T3 8 T7 4
valid_sources[0x14] 26148 1 T3 19 T8 47 T12 12
valid_sources[0x15] 26317 1 T1 13 T3 8 T8 44
valid_sources[0x16] 27571 1 T3 23 T8 33 T9 4
valid_sources[0x17] 27019 1 T3 13 T8 42 T9 2
valid_sources[0x18] 26213 1 T3 55 T8 51 T11 2
valid_sources[0x19] 26624 1 T1 1 T3 70 T7 10
valid_sources[0x1a] 26239 1 T1 13 T8 25 T11 2
valid_sources[0x1b] 26116 1 T3 22 T8 46 T9 2
valid_sources[0x1c] 26843 1 T1 1 T2 19 T3 13
valid_sources[0x1d] 27176 1 T1 5 T8 45 T9 1
valid_sources[0x1e] 26864 1 T1 1 T2 3 T3 11
valid_sources[0x1f] 26535 1 T1 3 T3 7 T8 60
valid_sources[0x20] 27024 1 T3 1 T8 28 T9 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24586 1 T1 2 T2 3 T3 23
values[0x0] all_enables biggest_size 183969 1 T1 9 T2 14 T3 172
values[0x1] all_enables biggest_size 24904 1 T1 1 T2 3 T3 29

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%