Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1571725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250317

1

T1

25

T2

21

T8

232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617378	1			T1	68		T2	60		T3	5
values[0x0]	586903	1			T1	70		T2	47		T3	3
values[0x1]	617761	1			T1	50		T2	62		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606287

1

T1

55

T2

57

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28336	1			T2	4		T3	1		T8	25
valid_sources[0x01]	28501	1			T2	5		T8	13		T7	25
valid_sources[0x02]	28650	1			T2	1		T3	1		T8	28
valid_sources[0x03]	28217	1			T2	1		T8	46		T7	18
valid_sources[0x04]	27821	1			T2	1		T8	7		T7	18
valid_sources[0x05]	28616	1			T2	2		T8	18		T7	10
valid_sources[0x06]	28357	1			T1	29		T2	2		T7	35
valid_sources[0x07]	28479	1			T1	6		T2	4		T3	3
valid_sources[0x08]	29690	1			T1	9		T2	2		T8	29
valid_sources[0x09]	28396	1			T2	2		T8	12		T7	15
valid_sources[0x0a]	29036	1			T1	26		T2	1		T8	16
valid_sources[0x0b]	29187	1			T2	2		T8	65		T7	21
valid_sources[0x0c]	27396	1			T1	11		T2	4		T8	47
valid_sources[0x0d]	27866	1			T2	5		T8	45		T7	15
valid_sources[0x0e]	28089	1			T2	1		T8	22		T7	15
valid_sources[0x0f]	27748	1			T2	8		T8	30		T7	14
valid_sources[0x10]	28642	1			T1	6		T2	1		T8	10
valid_sources[0x11]	28839	1			T8	17		T7	17		T9	91
valid_sources[0x12]	28415	1			T2	1		T8	44		T7	16
valid_sources[0x13]	28349	1			T2	3		T8	18		T7	30
valid_sources[0x14]	27886	1			T2	1		T8	18		T7	16
valid_sources[0x15]	28473	1			T2	10		T8	36		T7	18
valid_sources[0x16]	30386	1			T2	1		T7	9		T9	79
valid_sources[0x17]	28586	1			T2	3		T8	11		T7	23
valid_sources[0x18]	28609	1			T2	2		T8	28		T7	10
valid_sources[0x19]	28473	1			T1	6		T2	2		T8	30
valid_sources[0x1a]	28653	1			T1	2		T2	3		T3	1
valid_sources[0x1b]	29459	1			T1	1		T2	1		T8	62
valid_sources[0x1c]	29064	1			T1	5		T2	5		T8	31
valid_sources[0x1d]	28185	1			T2	3		T8	18		T7	20
valid_sources[0x1e]	28136	1			T1	14		T2	5		T8	47
valid_sources[0x1f]	27539	1			T2	1		T8	40		T7	24
valid_sources[0x20]	27705	1			T2	6		T8	15		T7	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26030

1

T2

3

T8

18

T7

12

values[0x0]

all_enables

biggest_size

198344

1

T1

24

T2

15

T8

191

values[0x1]

all_enables

biggest_size

25943

1

T1

1

T2

3

T8

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1597761	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259766

1

T1

15

T2

29

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635266	1			T1	59		T2	62		T3	15
values[0x0]	585774	1			T1	49		T2	49		T3	2
values[0x1]	636487	1			T1	73		T2	51		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1226613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

630914

1

T1

54

T2

65

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28850	1			T1	12		T2	4		T8	31
valid_sources[0x01]	29214	1			T1	6		T8	13		T7	18
valid_sources[0x02]	28441	1			T1	3		T8	25		T7	16
valid_sources[0x03]	28883	1			T8	31		T7	12		T9	39
valid_sources[0x04]	28847	1			T8	11		T7	20		T9	11
valid_sources[0x05]	28381	1			T3	1		T8	9		T7	15
valid_sources[0x06]	28909	1			T1	1		T7	17		T9	24
valid_sources[0x07]	29086	1			T8	24		T7	17		T9	9
valid_sources[0x08]	29034	1			T2	7		T3	1		T8	39
valid_sources[0x09]	29248	1			T3	1		T8	33		T7	20
valid_sources[0x0a]	29432	1			T8	29		T7	21		T9	9
valid_sources[0x0b]	29852	1			T1	1		T2	1		T8	45
valid_sources[0x0c]	29475	1			T2	2		T8	60		T7	17
valid_sources[0x0d]	29082	1			T2	6		T8	27		T7	28
valid_sources[0x0e]	29244	1			T2	3		T8	26		T7	14
valid_sources[0x0f]	28897	1			T1	23		T2	2		T8	31
valid_sources[0x10]	29687	1			T2	1		T8	17		T7	24
valid_sources[0x11]	28705	1			T1	8		T2	1		T8	13
valid_sources[0x12]	29362	1			T2	5		T3	1		T8	23
valid_sources[0x13]	28626	1			T2	3		T8	25		T7	16
valid_sources[0x14]	27814	1			T2	2		T3	1		T8	24
valid_sources[0x15]	29190	1			T1	1		T2	6		T3	2
valid_sources[0x16]	29993	1			T2	1		T7	16		T9	17
valid_sources[0x17]	29491	1			T1	3		T8	14		T7	31
valid_sources[0x18]	28612	1			T2	1		T3	2		T8	32
valid_sources[0x19]	28811	1			T1	13		T2	1		T3	1
valid_sources[0x1a]	29190	1			T1	5		T3	1		T8	50
valid_sources[0x1b]	29057	1			T2	2		T8	69		T7	28
valid_sources[0x1c]	29646	1			T2	5		T8	28		T7	12
valid_sources[0x1d]	29846	1			T2	3		T3	1		T8	6
valid_sources[0x1e]	28710	1			T1	1		T8	32		T7	16
valid_sources[0x1f]	28666	1			T2	11		T8	28		T7	29
valid_sources[0x20]	29141	1			T8	8		T7	16		T9	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27312

1

T2

5

T3

1

T8

16

values[0x0]

all_enables

biggest_size

205145

1

T1

13

T2

22

T3

2

values[0x1]

all_enables

biggest_size

27309

1

T1

2

T2

2

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1583398	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251725

1

T1

19

T2

28

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	622410	1			T1	39		T2	68		T3	6
values[0x0]	591388	1			T1	33		T2	54		T3	5
values[0x1]	621325	1			T1	37		T2	58		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1225753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

609370

1

T1

33

T2

62

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28135	1			T8	16		T7	20		T9	31
valid_sources[0x01]	29037	1			T8	9		T7	16		T9	25
valid_sources[0x02]	29284	1			T1	1		T2	1		T8	30
valid_sources[0x03]	28194	1			T2	13		T8	32		T7	12
valid_sources[0x04]	29002	1			T2	2		T8	20		T7	19
valid_sources[0x05]	28993	1			T2	8		T8	13		T7	24
valid_sources[0x06]	28466	1			T7	25		T9	31		T10	9
valid_sources[0x07]	28941	1			T3	1		T8	25		T7	20
valid_sources[0x08]	28770	1			T8	40		T7	24		T9	20
valid_sources[0x09]	28608	1			T1	4		T3	1		T8	29
valid_sources[0x0a]	28849	1			T8	17		T7	15		T9	18
valid_sources[0x0b]	29134	1			T2	3		T3	1		T8	36
valid_sources[0x0c]	29437	1			T2	7		T3	1		T8	63
valid_sources[0x0d]	28480	1			T1	2		T2	8		T8	33
valid_sources[0x0e]	28135	1			T1	6		T8	38		T7	24
valid_sources[0x0f]	28592	1			T1	8		T8	44		T7	16
valid_sources[0x10]	29042	1			T1	7		T2	4		T3	1
valid_sources[0x11]	28516	1			T1	1		T2	2		T3	2
valid_sources[0x12]	28506	1			T1	2		T8	31		T7	19
valid_sources[0x13]	28658	1			T2	4		T8	21		T7	22
valid_sources[0x14]	27906	1			T1	1		T2	2		T8	23
valid_sources[0x15]	28198	1			T2	2		T3	2		T8	39
valid_sources[0x16]	28742	1			T1	1		T2	14		T7	16
valid_sources[0x17]	28270	1			T3	1		T8	10		T7	11
valid_sources[0x18]	28006	1			T8	11		T7	21		T9	25
valid_sources[0x19]	29039	1			T1	7		T2	1		T8	21
valid_sources[0x1a]	28110	1			T2	2		T3	1		T8	48
valid_sources[0x1b]	29166	1			T2	2		T3	1		T8	92
valid_sources[0x1c]	28461	1			T1	2		T8	14		T7	25
valid_sources[0x1d]	28490	1			T1	1		T3	1		T8	10
valid_sources[0x1e]	28044	1			T1	1		T8	40		T7	24
valid_sources[0x1f]	28436	1			T2	4		T8	32		T7	26
valid_sources[0x20]	28400	1			T2	1		T8	7		T7	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26250

1

T1

3

T2

3

T8

21

values[0x0]

all_enables

biggest_size

199123

1

T1

14

T2

24

T3

1

values[0x1]

all_enables

biggest_size

26352

1

T1

2

T2

1

T8

22