Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7679417	0	0
GntImpliesValid_A	2147483647	7679417	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7679417	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	495400699	0	0
ReadyAndValidImplyGrant_A	2147483647	7679417	0	0
ReqAndReadyImplyGrant_A	2147483647	7679417	0	0
ReqImpliesValid_A	2147483647	35410965	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51675	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7679417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61200	59232	0	0
T2	343752	342120	0	0
T3	189024	188712	0	0
T7	785880	784896	0	0
T8	351072	350256	0	0
T9	797592	796008	0	0
T10	233904	233736	0	0
T11	40800	40176	0	0
T12	57792	56568	0	0
T13	1821192	1819464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61200	59232	0	0
T2	343752	342120	0	0
T3	189024	188712	0	0
T7	785880	784896	0	0
T8	351072	350256	0	0
T9	797592	796008	0	0
T10	233904	233736	0	0
T11	40800	40176	0	0
T12	57792	56568	0	0
T13	1821192	1819464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61200	59232	0	0
T2	343752	342120	0	0
T3	189024	188712	0	0
T7	785880	784896	0	0
T8	351072	350256	0	0
T9	797592	796008	0	0
T10	233904	233736	0	0
T11	40800	40176	0	0
T12	57792	56568	0	0
T13	1821192	1819464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	495400699	0	0
T1	61200	707	0	0
T2	343752	17430	0	0
T3	189024	10818	0	0
T7	785880	39579	0	0
T8	351072	7152	0	0
T9	797592	45767	0	0
T10	233904	6343	0	0
T11	40800	482	0	0
T12	57792	625	0	0
T13	1821192	112575	0	0
T14	0	23192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35410965	0	0
T1	61200	547	0	0
T2	343752	1090	0	0
T3	189024	1599	0	0
T7	785880	25904	0	0
T8	351072	5084	0	0
T9	797592	4870	0	0
T10	233904	6820	0	0
T11	40800	400	0	0
T12	57792	533	0	0
T13	1821192	16740	0	0
T14	0	6509	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51675	0	21600
T7	65490	0	0	2
T8	29256	10	0	2
T9	66466	0	0	2
T10	19492	27	0	2
T11	3400	0	0	2
T12	4816	0	0	2
T13	151766	2	0	2
T14	176162	1	0	2
T15	15128	17	0	2
T16	0	46	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	36	0	0
T21	0	5	0	0
T22	0	2	0	0
T23	0	5	0	0
T24	0	38	0	0
T25	459664	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	61200	59232	0	0
T2	343752	342120	0	0
T3	189024	188712	0	0
T7	785880	784896	0	0
T8	351072	350256	0	0
T9	797592	796008	0	0
T10	233904	233736	0	0
T11	40800	40176	0	0
T12	57792	56568	0	0
T13	1821192	1819464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7679417	0	0
T1	61200	478	0	0
T2	343752	511	0	0
T3	189024	670	0	0
T7	785880	3592	0	0
T8	351072	4963	0	0
T9	797592	2147	0	0
T10	233904	5916	0	0
T11	40800	362	0	0
T12	57792	452	0	0
T13	1821192	7019	0	0
T14	0	3185	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	862604	0	0
GntImpliesValid_A	453834792	862604	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	862604	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	12985624	0	0
ReadyAndValidImplyGrant_A	453834792	862604	0	0
ReqAndReadyImplyGrant_A	453834792	862604	0	0
ReqImpliesValid_A	453834792	2549860	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	862604	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	12985624	0	0
T1	2550	50	0	0
T2	14323	415	0	0
T3	7876	327	0	0
T7	32745	2064	0	0
T8	14628	496	0	0
T9	33233	1815	0	0
T10	9746	485	0	0
T11	1700	33	0	0
T12	2408	40	0	0
T13	75883	5838	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	2549860	0	0
T1	2550	81	0	0
T2	14323	86	0	0
T3	7876	88	0	0
T7	32745	501	0	0
T8	14628	523	0	0
T9	33233	391	0	0
T10	9746	834	0	0
T11	1700	46	0	0
T12	2408	73	0	0
T13	75883	1394	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	862604	0	0
T1	2550	65	0	0
T2	14323	58	0	0
T3	7876	54	0	0
T7	32745	294	0	0
T8	14628	509	0	0
T9	33233	236	0	0
T10	9746	659	0	0
T11	1700	39	0	0
T12	2408	56	0	0
T13	75883	767	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	844169	0	0
GntImpliesValid_A	453834792	844169	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	844169	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	13216873	0	0
ReadyAndValidImplyGrant_A	453834792	844169	0	0
ReqAndReadyImplyGrant_A	453834792	844169	0	0
ReqImpliesValid_A	453834792	2476948	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	844169	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	13216873	0	0
T1	2550	49	0	0
T2	14323	370	0	0
T3	7876	681	0	0
T7	32745	2226	0	0
T8	14628	528	0	0
T9	33233	1390	0	0
T10	9746	477	0	0
T11	1700	29	0	0
T12	2408	42	0	0
T13	75883	5734	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	2476948	0	0
T1	2550	72	0	0
T2	14323	63	0	0
T3	7876	125	0	0
T7	32745	460	0	0
T8	14628	551	0	0
T9	33233	252	0	0
T10	9746	802	0	0
T11	1700	38	0	0
T12	2408	67	0	0
T13	75883	1619	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	844169	0	0
T1	2550	60	0	0
T2	14323	50	0	0
T3	7876	88	0	0
T7	32745	287	0	0
T8	14628	539	0	0
T9	33233	200	0	0
T10	9746	639	0	0
T11	1700	33	0	0
T12	2408	54	0	0
T13	75883	790	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	215574	0	0
GntImpliesValid_A	453834792	215574	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	215574	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3288505	0	0
ReadyAndValidImplyGrant_A	453834792	215574	0	0
ReqAndReadyImplyGrant_A	453834792	215574	0	0
ReqImpliesValid_A	453834792	570603	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	215574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3288505	0	0
T1	2550	16	0	0
T2	14323	53	0	0
T3	7876	98	0	0
T7	32745	1	0	0
T8	14628	136	0	0
T9	33233	488	0	0
T10	9746	160	0	0
T11	1700	6	0	0
T12	2408	10	0	0
T13	75883	1323	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	570603	0	0
T1	2550	17	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	78	0	0
T10	9746	189	0	0
T11	1700	7	0	0
T12	2408	9	0	0
T13	75883	269	0	0
T14	0	368	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215574	0	0
T1	2550	16	0	0
T2	14323	6	0	0
T3	7876	14	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	62	0	0
T10	9746	174	0	0
T11	1700	6	0	0
T12	2408	9	0	0
T13	75883	196	0	0
T14	0	235	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	225960	0	0
GntImpliesValid_A	453834792	225960	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	225960	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3269241	0	0
ReadyAndValidImplyGrant_A	453834792	225960	0	0
ReqAndReadyImplyGrant_A	453834792	225960	0	0
ReqImpliesValid_A	453834792	600945	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	225960	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3269241	0	0
T1	2550	21	0	0
T2	14323	154	0	0
T3	7876	74	0	0
T7	32745	1	0	0
T8	14628	127	0	0
T9	33233	517	0	0
T10	9746	155	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	1336	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	600945	0	0
T1	2550	20	0	0
T2	14323	25	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	82	0	0
T10	9746	178	0	0
T11	1700	19	0	0
T12	2408	17	0	0
T13	75883	305	0	0
T14	0	297	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	225960	0	0
T1	2550	20	0	0
T2	14323	17	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	129	0	0
T9	33233	73	0	0
T10	9746	166	0	0
T11	1700	19	0	0
T12	2408	14	0	0
T13	75883	179	0	0
T14	0	208	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	209237	0	0
GntImpliesValid_A	453834792	209237	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	209237	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	5248713	0	0
ReadyAndValidImplyGrant_A	453834792	209237	0	0
ReqAndReadyImplyGrant_A	453834792	209237	0	0
ReqImpliesValid_A	453834792	1005518	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	209237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	5248713	0	0
T1	2550	97	0	0
T2	14323	143	0	0
T3	7876	113	0	0
T7	32745	0	0	0
T8	14628	1299	0	0
T9	33233	2908	0	0
T10	9746	622	0	0
T11	1700	64	0	0
T12	2408	70	0	0
T13	75883	2121	0	0
T14	0	10604	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	1005518	0	0
T1	2550	42	0	0
T2	14323	22	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	185	0	0
T9	33233	407	0	0
T10	9746	217	0	0
T11	1700	18	0	0
T12	2408	22	0	0
T13	75883	417	0	0
T14	0	1177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	209237	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	65	0	0
T10	9746	159	0	0
T11	1700	6	0	0
T12	2408	13	0	0
T13	75883	200	0	0
T14	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	213292	0	0
GntImpliesValid_A	453834792	213292	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	213292	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	5665539	0	0
ReadyAndValidImplyGrant_A	453834792	213292	0	0
ReqAndReadyImplyGrant_A	453834792	213292	0	0
ReqImpliesValid_A	453834792	1283901	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	213292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	5665539	0	0
T1	2550	69	0	0
T2	14323	290	0	0
T3	7876	108	0	0
T7	32745	1485	0	0
T8	14628	983	0	0
T9	33233	660	0	0
T10	9746	709	0	0
T11	1700	25	0	0
T12	2408	83	0	0
T13	75883	3636	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	1283901	0	0
T1	2550	18	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	4923	0	0
T8	14628	152	0	0
T9	33233	84	0	0
T10	9746	283	0	0
T11	1700	6	0	0
T12	2408	23	0	0
T13	75883	696	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	213292	0	0
T1	2550	13	0	0
T2	14323	14	0	0
T3	7876	17	0	0
T7	32745	524	0	0
T8	14628	150	0	0
T9	33233	62	0	0
T10	9746	165	0	0
T11	1700	6	0	0
T12	2408	16	0	0
T13	75883	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	210812	0	0
GntImpliesValid_A	453834792	210812	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	210812	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	5649979	0	0
ReadyAndValidImplyGrant_A	453834792	210812	0	0
ReqAndReadyImplyGrant_A	453834792	210812	0	0
ReqImpliesValid_A	453834792	1328640	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	210812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	5649979	0	0
T1	2550	166	0	0
T2	14323	286	0	0
T3	7876	198	0	0
T7	32745	0	0	0
T8	14628	870	0	0
T9	33233	852	0	0
T10	9746	493	0	0
T11	1700	42	0	0
T12	2408	119	0	0
T13	75883	1872	0	0
T14	0	7036	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	1328640	0	0
T1	2550	10	0	0
T2	14323	40	0	0
T3	7876	25	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	77	0	0
T10	9746	223	0	0
T11	1700	22	0	0
T12	2408	23	0	0
T13	75883	277	0	0
T14	0	874	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210812	0	0
T1	2550	10	0	0
T2	14323	13	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	57	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	10	0	0
T13	75883	172	0	0
T14	0	215	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	210316	0	0
GntImpliesValid_A	453834792	210316	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	210316	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	5757249	0	0
ReadyAndValidImplyGrant_A	453834792	210316	0	0
ReqAndReadyImplyGrant_A	453834792	210316	0	0
ReqImpliesValid_A	453834792	1291359	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	210316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	5757249	0	0
T1	2550	78	0	0
T2	14323	1135	0	0
T3	7876	74	0	0
T7	32745	0	0	0
T8	14628	745	0	0
T9	33233	1019	0	0
T10	9746	983	0	0
T11	1700	98	0	0
T12	2408	61	0	0
T13	75883	2095	0	0
T14	0	5552	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	1291359	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	149	0	0
T9	33233	106	0	0
T10	9746	319	0	0
T11	1700	14	0	0
T12	2408	25	0	0
T13	75883	337	0	0
T14	0	934	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210316	0	0
T1	2550	8	0	0
T2	14323	17	0	0
T3	7876	16	0	0
T7	32745	0	0	0
T8	14628	134	0	0
T9	33233	59	0	0
T10	9746	168	0	0
T11	1700	14	0	0
T12	2408	13	0	0
T13	75883	216	0	0
T14	0	235	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	203550	0	0
GntImpliesValid_A	453834792	203550	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	203550	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3212114	0	0
ReadyAndValidImplyGrant_A	453834792	203550	0	0
ReqAndReadyImplyGrant_A	453834792	203550	0	0
ReqImpliesValid_A	453834792	530061	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	203550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3212114	0	0
T1	2550	11	0	0
T2	14323	56	0	0
T3	7876	105	0	0
T7	32745	1	0	0
T8	14628	155	0	0
T9	33233	343	0	0
T10	9746	161	0	0
T11	1700	11	0	0
T12	2408	10	0	0
T13	75883	1542	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	530061	0	0
T1	2550	12	0	0
T2	14323	10	0	0
T3	7876	31	0	0
T7	32745	0	0	0
T8	14628	156	0	0
T9	33233	61	0	0
T10	9746	180	0	0
T11	1700	12	0	0
T12	2408	9	0	0
T13	75883	358	0	0
T14	0	341	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	203550	0	0
T1	2550	11	0	0
T2	14323	10	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	155	0	0
T9	33233	50	0	0
T10	9746	170	0	0
T11	1700	11	0	0
T12	2408	9	0	0
T13	75883	222	0	0
T14	0	209	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	207609	0	0
GntImpliesValid_A	453834792	207609	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	207609	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3213091	0	0
ReadyAndValidImplyGrant_A	453834792	207609	0	0
ReqAndReadyImplyGrant_A	453834792	207609	0	0
ReqImpliesValid_A	453834792	539042	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	207609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3213091	0	0
T1	2550	6	0	0
T2	14323	79	0	0
T3	7876	95	0	0
T7	32745	1	0	0
T8	14628	143	0	0
T9	33233	382	0	0
T10	9746	151	0	0
T11	1700	21	0	0
T12	2408	13	0	0
T13	75883	1482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	539042	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	144	0	0
T9	33233	72	0	0
T10	9746	176	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	294	0	0
T14	0	249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207609	0	0
T1	2550	5	0	0
T2	14323	11	0	0
T3	7876	13	0	0
T7	32745	0	0	0
T8	14628	143	0	0
T9	33233	58	0	0
T10	9746	163	0	0
T11	1700	20	0	0
T12	2408	12	0	0
T13	75883	197	0	0
T14	0	209	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	212743	0	0
GntImpliesValid_A	453834792	212743	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	212743	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3249105	0	0
ReadyAndValidImplyGrant_A	453834792	212743	0	0
ReqAndReadyImplyGrant_A	453834792	212743	0	0
ReqImpliesValid_A	453834792	546852	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	212743	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3249105	0	0
T1	2550	16	0	0
T2	14323	82	0	0
T3	7876	196	0	0
T7	32745	1	0	0
T8	14628	151	0	0
T9	33233	404	0	0
T10	9746	174	0	0
T11	1700	9	0	0
T12	2408	11	0	0
T13	75883	1432	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	546852	0	0
T1	2550	17	0	0
T2	14323	12	0	0
T3	7876	26	0	0
T7	32745	0	0	0
T8	14628	152	0	0
T9	33233	80	0	0
T10	9746	195	0	0
T11	1700	12	0	0
T12	2408	12	0	0
T13	75883	278	0	0
T14	0	344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	212743	0	0
T1	2550	16	0	0
T2	14323	12	0	0
T3	7876	19	0	0
T7	32745	0	0	0
T8	14628	151	0	0
T9	33233	52	0	0
T10	9746	184	0	0
T11	1700	10	0	0
T12	2408	11	0	0
T13	75883	196	0	0
T14	0	232	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	217069	0	0
GntImpliesValid_A	453834792	217069	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	217069	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3179151	0	0
ReadyAndValidImplyGrant_A	453834792	217069	0	0
ReqAndReadyImplyGrant_A	453834792	217069	0	0
ReqImpliesValid_A	453834792	589708	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	217069	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3179151	0	0
T1	2550	14	0	0
T2	14323	159	0	0
T3	7876	117	0	0
T7	32745	1207	0	0
T8	14628	161	0	0
T9	33233	347	0	0
T10	9746	161	0	0
T11	1700	6	0	0
T12	2408	12	0	0
T13	75883	1373	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	589708	0	0
T1	2550	13	0	0
T2	14323	24	0	0
T3	7876	39	0	0
T7	32745	4119	0	0
T8	14628	162	0	0
T9	33233	62	0	0
T10	9746	184	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	217069	0	0
T1	2550	13	0	0
T2	14323	16	0	0
T3	7876	16	0	0
T7	32745	466	0	0
T8	14628	161	0	0
T9	33233	51	0	0
T10	9746	172	0	0
T11	1700	5	0	0
T12	2408	11	0	0
T13	75883	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	207292	0	0
GntImpliesValid_A	453834792	207292	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	207292	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3289876	0	0
ReadyAndValidImplyGrant_A	453834792	207292	0	0
ReqAndReadyImplyGrant_A	453834792	207292	0	0
ReqImpliesValid_A	453834792	544725	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	207292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3289876	0	0
T1	2550	11	0	0
T2	14323	106	0	0
T3	7876	174	0	0
T7	32745	1	0	0
T8	14628	145	0	0
T9	33233	369	0	0
T10	9746	178	0	0
T11	1700	13	0	0
T12	2408	16	0	0
T13	75883	1470	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	544725	0	0
T1	2550	12	0	0
T2	14323	14	0	0
T3	7876	28	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	56	0	0
T10	9746	211	0	0
T11	1700	12	0	0
T12	2408	19	0	0
T13	75883	302	0	0
T14	0	214	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207292	0	0
T1	2550	11	0	0
T2	14323	14	0	0
T3	7876	22	0	0
T7	32745	0	0	0
T8	14628	146	0	0
T9	33233	51	0	0
T10	9746	194	0	0
T11	1700	12	0	0
T12	2408	17	0	0
T13	75883	204	0	0
T14	0	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	206271	0	0
GntImpliesValid_A	453834792	206271	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	206271	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3272150	0	0
ReadyAndValidImplyGrant_A	453834792	206271	0	0
ReqAndReadyImplyGrant_A	453834792	206271	0	0
ReqImpliesValid_A	453834792	538433	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	206271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3272150	0	0
T1	2550	15	0	0
T2	14323	124	0	0
T3	7876	108	0	0
T7	32745	1	0	0
T8	14628	147	0	0
T9	33233	403	0	0
T10	9746	144	0	0
T11	1700	9	0	0
T12	2408	11	0	0
T13	75883	1445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	538433	0	0
T1	2550	16	0	0
T2	14323	15	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	150	0	0
T9	33233	75	0	0
T10	9746	169	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	298	0	0
T14	0	282	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	206271	0	0
T1	2550	15	0	0
T2	14323	15	0	0
T3	7876	17	0	0
T7	32745	0	0	0
T8	14628	148	0	0
T9	33233	59	0	0
T10	9746	156	0	0
T11	1700	8	0	0
T12	2408	10	0	0
T13	75883	201	0	0
T14	0	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	198911	0	0
GntImpliesValid_A	453834792	198911	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	198911	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3220706	0	0
ReadyAndValidImplyGrant_A	453834792	198911	0	0
ReqAndReadyImplyGrant_A	453834792	198911	0	0
ReqImpliesValid_A	453834792	511791	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	198911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3220706	0	0
T1	2550	9	0	0
T2	14323	181	0	0
T3	7876	148	0	0
T7	32745	1	0	0
T8	14628	137	0	0
T9	33233	554	0	0
T10	9746	154	0	0
T11	1700	8	0	0
T12	2408	12	0	0
T13	75883	1472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	511791	0	0
T1	2550	10	0	0
T2	14323	34	0	0
T3	7876	27	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	94	0	0
T10	9746	171	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	290	0	0
T14	0	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	198911	0	0
T1	2550	9	0	0
T2	14323	20	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	136	0	0
T9	33233	70	0	0
T10	9746	162	0	0
T11	1700	7	0	0
T12	2408	11	0	0
T13	75883	203	0	0
T14	0	217	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	211796	0	0
GntImpliesValid_A	453834792	211796	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	211796	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3246191	0	0
ReadyAndValidImplyGrant_A	453834792	211796	0	0
ReqAndReadyImplyGrant_A	453834792	211796	0	0
ReqImpliesValid_A	453834792	547796	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	211796	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3246191	0	0
T1	2550	16	0	0
T2	14323	120	0	0
T3	7876	85	0	0
T7	32745	1002	0	0
T8	14628	135	0	0
T9	33233	453	0	0
T10	9746	138	0	0
T11	1700	12	0	0
T12	2408	15	0	0
T13	75883	1428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	547796	0	0
T1	2550	19	0	0
T2	14323	25	0	0
T3	7876	15	0	0
T7	32745	4880	0	0
T8	14628	138	0	0
T9	33233	69	0	0
T10	9746	149	0	0
T11	1700	11	0	0
T12	2408	16	0	0
T13	75883	255	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	211796	0	0
T1	2550	17	0	0
T2	14323	17	0	0
T3	7876	15	0	0
T7	32745	520	0	0
T8	14628	136	0	0
T9	33233	55	0	0
T10	9746	143	0	0
T11	1700	11	0	0
T12	2408	15	0	0
T13	75883	189	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	229447	0	0
GntImpliesValid_A	453834792	229447	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	229447	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3346976	0	0
ReadyAndValidImplyGrant_A	453834792	229447	0	0
ReqAndReadyImplyGrant_A	453834792	229447	0	0
ReqImpliesValid_A	453834792	604859	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	229447	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3346976	0	0
T1	2550	8	0	0
T2	14323	195	0	0
T3	7876	222	0	0
T7	32745	1	0	0
T8	14628	134	0	0
T9	33233	738	0	0
T10	9746	171	0	0
T11	1700	13	0	0
T12	2408	19	0	0
T13	75883	1319	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	604859	0	0
T1	2550	9	0	0
T2	14323	24	0	0
T3	7876	36	0	0
T7	32745	0	0	0
T8	14628	137	0	0
T9	33233	134	0	0
T10	9746	192	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	224	0	0
T14	0	240	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	229447	0	0
T1	2550	8	0	0
T2	14323	22	0	0
T3	7876	29	0	0
T7	32745	0	0	0
T8	14628	135	0	0
T9	33233	104	0	0
T10	9746	181	0	0
T11	1700	12	0	0
T12	2408	18	0	0
T13	75883	190	0	0
T14	0	208	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	215686	0	0
GntImpliesValid_A	453834792	215686	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	215686	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3301482	0	0
ReadyAndValidImplyGrant_A	453834792	215686	0	0
ReqAndReadyImplyGrant_A	453834792	215686	0	0
ReqImpliesValid_A	453834792	571213	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	215686	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3301482	0	0
T1	2550	10	0	0
T2	14323	121	0	0
T3	7876	146	0	0
T7	32745	1	0	0
T8	14628	154	0	0
T9	33233	452	0	0
T10	9746	153	0	0
T11	1700	15	0	0
T12	2408	15	0	0
T13	75883	1526	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	571213	0	0
T1	2550	9	0	0
T2	14323	16	0	0
T3	7876	25	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	69	0	0
T10	9746	174	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	323	0	0
T14	0	311	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	215686	0	0
T1	2550	9	0	0
T2	14323	15	0	0
T3	7876	18	0	0
T7	32745	0	0	0
T8	14628	153	0	0
T9	33233	63	0	0
T10	9746	163	0	0
T11	1700	14	0	0
T12	2408	14	0	0
T13	75883	207	0	0
T14	0	214	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	220909	0	0
GntImpliesValid_A	453834792	220909	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	220909	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3309421	0	0
ReadyAndValidImplyGrant_A	453834792	220909	0	0
ReqAndReadyImplyGrant_A	453834792	220909	0	0
ReqImpliesValid_A	453834792	597948	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	220909	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3309421	0	0
T1	2550	16	0	0
T2	14323	147	0	0
T3	7876	158	0	0
T7	32745	1252	0	0
T8	14628	113	0	0
T9	33233	508	0	0
T10	9746	181	0	0
T11	1700	10	0	0
T12	2408	13	0	0
T13	75883	1264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	597948	0	0
T1	2550	21	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	4519	0	0
T8	14628	114	0	0
T9	33233	75	0	0
T10	9746	190	0	0
T11	1700	9	0	0
T12	2408	16	0	0
T13	75883	214	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	220909	0	0
T1	2550	18	0	0
T2	14323	15	0	0
T3	7876	19	0	0
T7	32745	507	0	0
T8	14628	113	0	0
T9	33233	64	0	0
T10	9746	185	0	0
T11	1700	9	0	0
T12	2408	14	0	0
T13	75883	171	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	210474	0	0
GntImpliesValid_A	453834792	210474	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	210474	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3215188	0	0
ReadyAndValidImplyGrant_A	453834792	210474	0	0
ReqAndReadyImplyGrant_A	453834792	210474	0	0
ReqImpliesValid_A	453834792	544698	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	210474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3215188	0	0
T1	2550	8	0	0
T2	14323	81	0	0
T3	7876	101	0	0
T7	32745	949	0	0
T8	14628	119	0	0
T9	33233	481	0	0
T10	9746	169	0	0
T11	1700	11	0	0
T12	2408	13	0	0
T13	75883	1396	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	544698	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	19	0	0
T7	32745	3661	0	0
T8	14628	118	0	0
T9	33233	74	0	0
T10	9746	188	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	209	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	210474	0	0
T1	2550	7	0	0
T2	14323	8	0	0
T3	7876	16	0	0
T7	32745	413	0	0
T8	14628	118	0	0
T9	33233	58	0	0
T10	9746	178	0	0
T11	1700	10	0	0
T12	2408	12	0	0
T13	75883	179	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	219557	0	0
GntImpliesValid_A	453834792	219557	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	219557	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3283585	0	0
ReadyAndValidImplyGrant_A	453834792	219557	0	0
ReqAndReadyImplyGrant_A	453834792	219557	0	0
ReqImpliesValid_A	453834792	601393	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	219557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3283585	0	0
T1	2550	5	0	0
T2	14323	150	0	0
T3	7876	163	0	0
T7	32745	1	0	0
T8	14628	133	0	0
T9	33233	373	0	0
T10	9746	162	0	0
T11	1700	13	0	0
T12	2408	15	0	0
T13	75883	1575	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	601393	0	0
T1	2550	4	0	0
T2	14323	23	0	0
T3	7876	34	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	66	0	0
T10	9746	185	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	275	0	0
T14	0	258	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	219557	0	0
T1	2550	4	0	0
T2	14323	17	0	0
T3	7876	20	0	0
T7	32745	0	0	0
T8	14628	132	0	0
T9	33233	56	0	0
T10	9746	173	0	0
T11	1700	12	0	0
T12	2408	14	0	0
T13	75883	210	0	0
T14	0	209	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	207587	0	0
GntImpliesValid_A	453834792	207587	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	207587	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	3188915	0	0
ReadyAndValidImplyGrant_A	453834792	207587	0	0
ReqAndReadyImplyGrant_A	453834792	207587	0	0
ReqImpliesValid_A	453834792	529577	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	0	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	207587	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	3188915	0	0
T1	2550	14	0	0
T2	14323	68	0	0
T3	7876	143	0	0
T7	32745	1	0	0
T8	14628	139	0	0
T9	33233	446	0	0
T10	9746	160	0	0
T11	1700	12	0	0
T12	2408	11	0	0
T13	75883	1453	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	529577	0	0
T1	2550	13	0	0
T2	14323	23	0	0
T3	7876	46	0	0
T7	32745	0	0	0
T8	14628	140	0	0
T9	33233	86	0	0
T10	9746	177	0	0
T11	1700	11	0	0
T12	2408	12	0	0
T13	75883	266	0	0
T14	0	289	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	207587	0	0
T1	2550	13	0	0
T2	14323	13	0	0
T3	7876	21	0	0
T7	32745	0	0	0
T8	14628	139	0	0
T9	33233	55	0	0
T10	9746	168	0	0
T11	1700	11	0	0
T12	2408	11	0	0
T13	75883	199	0	0
T14	0	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	867371	0	0
GntImpliesValid_A	453834792	867371	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	867371	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	12447747	0	0
ReadyAndValidImplyGrant_A	453834792	867371	0	0
ReqAndReadyImplyGrant_A	453834792	867371	0	0
ReqImpliesValid_A	453834792	2371483	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	19868	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	867371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	12447747	0	0
T1	2550	1	0	0
T2	14323	336	0	0
T3	7876	647	0	0
T7	32745	1804	0	0
T8	14628	1	0	0
T9	33233	1400	0	0
T10	9746	1	0	0
T11	1700	1	0	0
T12	2408	1	0	0
T13	75883	5056	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	2371483	0	0
T1	2550	56	0	0
T2	14323	93	0	0
T3	7876	198	0	0
T7	32745	430	0	0
T8	14628	531	0	0
T9	33233	366	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	1234	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	19868	0	900
T7	32745	0	0	1
T8	14628	3	0	1
T9	33233	0	0	1
T10	9746	13	0	1
T11	1700	0	0	1
T12	2408	0	0	1
T13	75883	0	0	1
T14	88081	0	0	1
T15	7564	5	0	1
T16	0	23	0	0
T17	0	1	0	0
T20	0	13	0	0
T21	0	5	0	0
T22	0	2	0	0
T23	0	5	0	0
T24	0	38	0	0
T25	229832	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	867371	0	0
T1	2550	56	0	0
T2	14323	56	0	0
T3	7876	89	0	0
T7	32745	300	0	0
T8	14628	531	0	0
T9	33233	249	0	0
T10	9746	605	0	0
T11	1700	39	0	0
T12	2408	47	0	0
T13	75883	773	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453834792	453709838	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	453834792	851181	0	0
GntImpliesValid_A	453834792	851181	0	0
GrantKnown_A	453834792	453709838	0	0
IdxKnown_A	453834792	453709838	0	0
IndexIsCorrect_A	453834792	851181	0	0
LockArbDecision_A	453834792	0	0	0
NoReadyValidNoGrant_A	453834792	382343278	0	0
ReadyAndValidImplyGrant_A	453834792	851181	0	0
ReqAndReadyImplyGrant_A	453834792	851181	0	0
ReqImpliesValid_A	453834792	14133612	0	0
ReqStaysHighUntilGranted0_M	453834792	0	0	0
RoundRobin_A	453834792	31807	0	900
ValidKnown_A	453834792	453709838	0	0
gen_data_port_assertion.DataFlow_A	453834792	851181	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	382343278	0	0
T1	2550	1	0	0
T2	14323	12579	0	0
T3	7876	6537	0	0
T7	32745	27578	0	0
T8	14628	1	0	0
T9	33233	28465	0	0
T10	9746	1	0	0
T11	1700	1	0	0
T12	2408	1	0	0
T13	75883	63387	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	14133612	0	0
T1	2550	56	0	0
T2	14323	470	0	0
T3	7876	702	0	0
T7	32745	2411	0	0
T8	14628	589	0	0
T9	33233	1954	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	6350	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	31807	0	900
T7	32745	0	0	1
T8	14628	7	0	1
T9	33233	0	0	1
T10	9746	14	0	1
T11	1700	0	0	1
T12	2408	0	0	1
T13	75883	2	0	1
T14	88081	1	0	1
T15	7564	12	0	1
T16	0	23	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	23	0	0
T25	229832	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	453709838	0	0
T1	2550	2468	0	0
T2	14323	14255	0	0
T3	7876	7863	0	0
T7	32745	32704	0	0
T8	14628	14594	0	0
T9	33233	33167	0	0
T10	9746	9739	0	0
T11	1700	1674	0	0
T12	2408	2357	0	0
T13	75883	75811	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453834792	851181	0	0
T1	2550	56	0	0
T2	14323	61	0	0
T3	7876	81	0	0
T7	32745	281	0	0
T8	14628	589	0	0
T9	33233	238	0	0
T10	9746	629	0	0
T11	1700	36	0	0
T12	2408	41	0	0
T13	75883	776	0	0