Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1554175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247241

1

T1

13

T2

32

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611289	1			T1	53		T2	60		T3	38
values[0x0]	578214	1			T1	36		T2	64		T3	39
values[0x1]	611913	1			T1	47		T2	62		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1201533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599883

1

T1

36

T2

74

T3

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27652	1			T1	2		T7	6		T11	7
valid_sources[0x01]	27810	1			T1	1		T7	1		T11	5
valid_sources[0x02]	28037	1			T7	1		T11	2		T14	14
valid_sources[0x03]	28509	1			T10	6		T7	8		T12	4
valid_sources[0x04]	28615	1			T1	2		T7	5		T11	4
valid_sources[0x05]	28832	1			T1	4		T10	31		T7	8
valid_sources[0x06]	27427	1			T1	2		T7	3		T11	1
valid_sources[0x07]	27995	1			T1	1		T3	13		T7	2
valid_sources[0x08]	27185	1			T1	3		T7	3		T12	1
valid_sources[0x09]	28293	1			T1	4		T7	1		T11	3
valid_sources[0x0a]	27962	1			T1	1		T3	8		T11	1
valid_sources[0x0b]	28163	1			T1	1		T7	3		T12	4
valid_sources[0x0c]	27673	1			T1	2		T7	1		T11	5
valid_sources[0x0d]	28935	1			T1	3		T7	6		T11	4
valid_sources[0x0e]	28680	1			T1	2		T2	33		T7	1
valid_sources[0x0f]	28147	1			T1	1		T3	9		T7	2
valid_sources[0x10]	28126	1			T1	5		T7	8		T12	3
valid_sources[0x11]	28528	1			T1	1		T7	3		T11	2
valid_sources[0x12]	27931	1			T11	2		T12	3		T15	3
valid_sources[0x13]	28679	1			T1	4		T7	14		T11	3
valid_sources[0x14]	28585	1			T1	1		T7	4		T11	9
valid_sources[0x15]	27275	1			T1	1		T7	9		T12	6
valid_sources[0x16]	27991	1			T1	6		T3	9		T7	4
valid_sources[0x17]	28446	1			T1	1		T7	4		T11	8
valid_sources[0x18]	27897	1			T1	2		T7	1		T11	4
valid_sources[0x19]	28469	1			T1	3		T7	8		T11	1
valid_sources[0x1a]	28055	1			T1	2		T7	5		T11	2
valid_sources[0x1b]	28155	1			T1	3		T7	2		T14	3
valid_sources[0x1c]	30241	1			T1	3		T7	4		T11	6
valid_sources[0x1d]	27492	1			T2	27		T7	4		T11	2
valid_sources[0x1e]	28052	1			T1	1		T3	12		T7	12
valid_sources[0x1f]	28461	1			T1	4		T3	19		T7	10
valid_sources[0x20]	27125	1			T1	3		T2	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25983

1

T1

3

T2

3

T3

5

values[0x0]

all_enables

biggest_size

195496

1

T1

9

T2

26

T3

12

values[0x1]

all_enables

biggest_size

25762

1

T1

1

T2

3

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1573828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256508

1

T1

24

T2

22

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	626721	1			T1	62		T2	47		T3	52
values[0x0]	576265	1			T1	49		T2	54		T3	37
values[0x1]	627350	1			T1	53		T2	41		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

622702

1

T1

53

T2

52

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28643	1			T1	1		T2	4		T7	10
valid_sources[0x01]	28431	1			T10	4		T7	15		T15	3
valid_sources[0x02]	28996	1			T1	2		T2	1		T10	2
valid_sources[0x03]	28791	1			T1	5		T10	2		T11	5
valid_sources[0x04]	28482	1			T1	2		T10	2		T14	36
valid_sources[0x05]	28845	1			T3	6		T10	2		T14	5
valid_sources[0x06]	29048	1			T10	5		T12	20		T14	10
valid_sources[0x07]	27724	1			T1	3		T10	2		T14	25
valid_sources[0x08]	27560	1			T1	2		T10	4		T11	8
valid_sources[0x09]	28677	1			T1	4		T7	6		T12	5
valid_sources[0x0a]	28991	1			T2	3		T3	2		T10	4
valid_sources[0x0b]	28285	1			T10	4		T11	13		T16	25
valid_sources[0x0c]	28275	1			T2	11		T3	12		T7	3
valid_sources[0x0d]	30057	1			T3	6		T10	1		T14	12
valid_sources[0x0e]	29095	1			T10	4		T14	24		T15	2
valid_sources[0x0f]	28183	1			T1	7		T10	1		T7	25
valid_sources[0x10]	28555	1			T1	1		T3	3		T10	6
valid_sources[0x11]	29222	1			T2	7		T3	6		T10	3
valid_sources[0x12]	28962	1			T2	8		T10	3		T14	14
valid_sources[0x13]	28415	1			T1	3		T2	38		T3	10
valid_sources[0x14]	28162	1			T3	5		T10	3		T7	16
valid_sources[0x15]	28722	1			T10	1		T7	10		T12	4
valid_sources[0x16]	28266	1			T10	5		T7	3		T14	6
valid_sources[0x17]	27875	1			T1	7		T3	7		T10	3
valid_sources[0x18]	28358	1			T1	8		T10	6		T11	12
valid_sources[0x19]	29064	1			T1	2		T10	3		T12	7
valid_sources[0x1a]	27598	1			T1	2		T2	3		T10	1
valid_sources[0x1b]	28775	1			T1	4		T2	1		T3	11
valid_sources[0x1c]	29353	1			T1	1		T10	1		T7	31
valid_sources[0x1d]	27363	1			T1	11		T3	1		T10	7
valid_sources[0x1e]	29271	1			T1	4		T2	1		T10	1
valid_sources[0x1f]	28489	1			T2	10		T10	7		T12	14
valid_sources[0x20]	28840	1			T1	6		T13	3		T14	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27053

1

T1

5

T2

4

T10

2

values[0x0]

all_enables

biggest_size

202300

1

T1

18

T2

17

T3

14

values[0x1]

all_enables

biggest_size

27155

1

T1

1

T2

1

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1561985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248544

1

T1

21

T2

19

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614100	1			T1	56		T2	42		T3	54
values[0x0]	581690	1			T1	62		T2	42		T3	49
values[0x1]	614739	1			T1	72		T2	46		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1206234	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

604295

1

T1

60

T2

45

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28558	1			T1	1		T3	1		T7	5
valid_sources[0x01]	27966	1			T3	4		T7	6		T11	1
valid_sources[0x02]	28234	1			T2	26		T3	2		T10	13
valid_sources[0x03]	27940	1			T2	5		T3	1		T7	3
valid_sources[0x04]	28402	1			T3	2		T7	2		T11	8
valid_sources[0x05]	28223	1			T2	1		T3	2		T7	1
valid_sources[0x06]	27021	1			T3	2		T7	3		T14	4
valid_sources[0x07]	28863	1			T3	4		T7	1		T11	1
valid_sources[0x08]	27758	1			T2	5		T3	1		T7	8
valid_sources[0x09]	27680	1			T2	4		T3	4		T7	2
valid_sources[0x0a]	29237	1			T3	4		T7	5		T14	7
valid_sources[0x0b]	28407	1			T2	4		T3	3		T10	19
valid_sources[0x0c]	28292	1			T3	4		T7	4		T11	5
valid_sources[0x0d]	28159	1			T3	2		T7	2		T14	9
valid_sources[0x0e]	28585	1			T1	4		T3	3		T7	5
valid_sources[0x0f]	28511	1			T2	12		T3	3		T7	1
valid_sources[0x10]	28286	1			T1	30		T3	2		T10	9
valid_sources[0x11]	27880	1			T2	1		T3	3		T10	34
valid_sources[0x12]	28343	1			T1	35		T3	2		T10	1
valid_sources[0x13]	28331	1			T3	6		T10	4		T7	5
valid_sources[0x14]	28885	1			T2	9		T3	1		T10	10
valid_sources[0x15]	27452	1			T1	6		T3	3		T10	4
valid_sources[0x16]	28152	1			T7	7		T11	4		T14	12
valid_sources[0x17]	28280	1			T1	27		T7	1		T11	4
valid_sources[0x18]	28693	1			T1	22		T7	4		T12	33
valid_sources[0x19]	27752	1			T3	2		T10	2		T7	4
valid_sources[0x1a]	27962	1			T3	4		T10	3		T11	2
valid_sources[0x1b]	27679	1			T3	2		T7	3		T11	1
valid_sources[0x1c]	28294	1			T2	4		T7	2		T11	1
valid_sources[0x1d]	27893	1			T2	4		T7	4		T14	12
valid_sources[0x1e]	28724	1			T3	3		T11	2		T12	2
valid_sources[0x1f]	29048	1			T3	2		T7	10		T11	2
valid_sources[0x20]	28620	1			T3	2		T7	6		T14	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26185

1

T1

1

T2

2

T3

4

values[0x0]

all_enables

biggest_size

196290

1

T1

19

T2

15

T3

19

values[0x1]

all_enables

biggest_size

26069

1

T1

1

T2

2

T3

4