Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8088614	0	0
GntImpliesValid_A	2147483647	8088614	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8088614	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453528677	0	0
ReadyAndValidImplyGrant_A	2147483647	8088614	0	0
ReqAndReadyImplyGrant_A	2147483647	8088614	0	0
ReqImpliesValid_A	2147483647	35302782	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50529	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8088614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52296	51600	0	0
T2	65496	64080	0	0
T3	45072	44496	0	0
T7	156456	155472	0	0
T10	39456	39264	0	0
T11	34944	34560	0	0
T12	62904	60816	0	0
T13	33000	31776	0	0
T14	53256	53016	0	0
T15	48552	47952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0
T14	24	24	0	0
T15	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52296	51600	0	0
T2	65496	64080	0	0
T3	45072	44496	0	0
T7	156456	155472	0	0
T10	39456	39264	0	0
T11	34944	34560	0	0
T12	62904	60816	0	0
T13	33000	31776	0	0
T14	53256	53016	0	0
T15	48552	47952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52296	51600	0	0
T2	65496	64080	0	0
T3	45072	44496	0	0
T7	156456	155472	0	0
T10	39456	39264	0	0
T11	34944	34560	0	0
T12	62904	60816	0	0
T13	33000	31776	0	0
T14	53256	53016	0	0
T15	48552	47952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453528677	0	0
T1	52296	669	0	0
T2	65496	926	0	0
T3	45072	562	0	0
T7	156456	8990	0	0
T10	39456	451	0	0
T11	34944	425	0	0
T12	62904	823	0	0
T13	33000	558	0	0
T14	53256	1552	0	0
T15	48552	485	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35302782	0	0
T1	52296	578	0	0
T2	65496	536	0	0
T3	45072	478	0	0
T7	156456	946	0	0
T10	39456	503	0	0
T11	34944	394	0	0
T12	62904	478	0	0
T13	33000	481	0	0
T14	53256	1822	0	0
T15	48552	610	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50529	0	21600
T8	18344	0	0	2
T9	385474	0	0	2
T13	1375	1	0	1
T14	4438	5	0	2
T15	4046	0	0	2
T16	10050	9	0	2
T17	18324	22	0	2
T18	29430	13	0	2
T19	18242	17	0	2
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	24	0	0
T24	0	1	0	0
T25	0	184	0	0
T26	0	4	0	0
T27	0	19	0	0
T28	45192	0	0	2
T29	39055	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52296	51600	0	0
T2	65496	64080	0	0
T3	45072	44496	0	0
T7	156456	155472	0	0
T10	39456	39264	0	0
T11	34944	34560	0	0
T12	62904	60816	0	0
T13	33000	31776	0	0
T14	53256	53016	0	0
T15	48552	47952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8088614	0	0
T1	52296	490	0	0
T2	65496	458	0	0
T3	45072	427	0	0
T7	156456	414	0	0
T10	39456	443	0	0
T11	34944	365	0	0
T12	62904	422	0	0
T13	33000	439	0	0
T14	53256	1617	0	0
T15	48552	539	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	903870	0	0
GntImpliesValid_A	417469597	903870	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	903870	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	12074721	0	0
ReadyAndValidImplyGrant_A	417469597	903870	0	0
ReqAndReadyImplyGrant_A	417469597	903870	0	0
ReqImpliesValid_A	417469597	2516446	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	903870	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	12074721	0	0
T1	2179	33	0	0
T2	2729	28	0	0
T3	1878	26	0	0
T7	6519	354	0	0
T10	1644	42	0	0
T11	1456	24	0	0
T12	2621	46	0	0
T13	1375	38	0	0
T14	2219	150	0	0
T15	2023	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2516446	0	0
T1	2179	62	0	0
T2	2729	43	0	0
T3	1878	43	0	0
T7	6519	56	0	0
T10	1644	69	0	0
T11	1456	25	0	0
T12	2621	57	0	0
T13	1375	57	0	0
T14	2219	259	0	0
T15	2023	68	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	903870	0	0
T1	2179	47	0	0
T2	2729	35	0	0
T3	1878	34	0	0
T7	6519	49	0	0
T10	1644	55	0	0
T11	1456	24	0	0
T12	2621	51	0	0
T13	1375	47	0	0
T14	2219	204	0	0
T15	2023	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	887704	0	0
GntImpliesValid_A	417469597	887704	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	887704	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	12053115	0	0
ReadyAndValidImplyGrant_A	417469597	887704	0	0
ReqAndReadyImplyGrant_A	417469597	887704	0	0
ReqImpliesValid_A	417469597	2406031	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	887704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	12053115	0	0
T1	2179	43	0	0
T2	2729	46	0	0
T3	1878	48	0	0
T7	6519	254	0	0
T10	1644	58	0	0
T11	1456	32	0	0
T12	2621	36	0	0
T13	1375	39	0	0
T14	2219	151	0	0
T15	2023	49	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2406031	0	0
T1	2179	54	0	0
T2	2729	63	0	0
T3	1878	69	0	0
T7	6519	71	0	0
T10	1644	91	0	0
T11	1456	45	0	0
T12	2621	47	0	0
T13	1375	52	0	0
T14	2219	258	0	0
T15	2023	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	887704	0	0
T1	2179	48	0	0
T2	2729	54	0	0
T3	1878	58	0	0
T7	6519	41	0	0
T10	1644	74	0	0
T11	1456	38	0	0
T12	2621	41	0	0
T13	1375	45	0	0
T14	2219	204	0	0
T15	2023	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	226859	0	0
GntImpliesValid_A	417469597	226859	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	226859	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3018846	0	0
ReadyAndValidImplyGrant_A	417469597	226859	0	0
ReqAndReadyImplyGrant_A	417469597	226859	0	0
ReqImpliesValid_A	417469597	614829	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	226859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3018846	0	0
T1	2179	17	0	0
T2	2729	13	0	0
T3	1878	17	0	0
T7	6519	39	0	0
T10	1644	9	0	0
T11	1456	9	0	0
T12	2621	16	0	0
T13	1375	14	0	0
T14	2219	53	0	0
T15	2023	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	614829	0	0
T1	2179	18	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	9	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	15	0	0
T14	2219	56	0	0
T15	2023	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	226859	0	0
T1	2179	17	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	8	0	0
T12	2621	15	0	0
T13	1375	14	0	0
T14	2219	54	0	0
T15	2023	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	223103	0	0
GntImpliesValid_A	417469597	223103	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	223103	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	2976531	0	0
ReadyAndValidImplyGrant_A	417469597	223103	0	0
ReqAndReadyImplyGrant_A	417469597	223103	0	0
ReqImpliesValid_A	417469597	608103	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	223103	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2976531	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	53	0	0
T10	1644	9	0	0
T11	1456	8	0	0
T12	2621	11	0	0
T13	1375	13	0	0
T14	2219	35	0	0
T15	2023	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	608103	0	0
T1	2179	20	0	0
T2	2729	12	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	38	0	0
T15	2023	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	223103	0	0
T1	2179	19	0	0
T2	2729	11	0	0
T3	1878	9	0	0
T7	6519	8	0	0
T10	1644	8	0	0
T11	1456	7	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	36	0	0
T15	2023	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	221199	0	0
GntImpliesValid_A	417469597	221199	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	221199	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	4573766	0	0
ReadyAndValidImplyGrant_A	417469597	221199	0	0
ReqAndReadyImplyGrant_A	417469597	221199	0	0
ReqImpliesValid_A	417469597	1137375	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	221199	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	4573766	0	0
T1	2179	160	0	0
T2	2729	100	0	0
T3	1878	84	0	0
T7	6519	609	0	0
T10	1644	57	0	0
T11	1456	38	0	0
T12	2621	207	0	0
T13	1375	40	0	0
T14	2219	171	0	0
T15	2023	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	1137375	0	0
T1	2179	39	0	0
T2	2729	21	0	0
T3	1878	22	0	0
T7	6519	59	0	0
T10	1644	28	0	0
T11	1456	15	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	49	0	0
T15	2023	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	221199	0	0
T1	2179	17	0	0
T2	2729	11	0	0
T3	1878	16	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	42	0	0
T15	2023	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	220737	0	0
GntImpliesValid_A	417469597	220737	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	220737	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	4697933	0	0
ReadyAndValidImplyGrant_A	417469597	220737	0	0
ReqAndReadyImplyGrant_A	417469597	220737	0	0
ReqImpliesValid_A	417469597	1286695	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	220737	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	4697933	0	0
T1	2179	90	0	0
T2	2729	347	0	0
T3	1878	57	0	0
T7	6519	69	0	0
T10	1644	30	0	0
T11	1456	40	0	0
T12	2621	253	0	0
T13	1375	92	0	0
T14	2219	160	0	0
T15	2023	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	1286695	0	0
T1	2179	26	0	0
T2	2729	35	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	25	0	0
T12	2621	28	0	0
T13	1375	23	0	0
T14	2219	44	0	0
T15	2023	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220737	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	7	0	0
T10	1644	9	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	16	0	0
T14	2219	38	0	0
T15	2023	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	209902	0	0
GntImpliesValid_A	417469597	209902	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	209902	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	5645792	0	0
ReadyAndValidImplyGrant_A	417469597	209902	0	0
ReqAndReadyImplyGrant_A	417469597	209902	0	0
ReqImpliesValid_A	417469597	1195077	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	209902	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	5645792	0	0
T1	2179	56	0	0
T2	2729	35	0	0
T3	1878	46	0	0
T7	6519	231	0	0
T10	1644	40	0	0
T11	1456	47	0	0
T12	2621	35	0	0
T13	1375	77	0	0
T14	2219	152	0	0
T15	2023	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	1195077	0	0
T1	2179	44	0	0
T2	2729	24	0	0
T3	1878	21	0	0
T7	6519	33	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	22	0	0
T14	2219	63	0	0
T15	2023	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	209902	0	0
T1	2179	19	0	0
T2	2729	5	0	0
T3	1878	12	0	0
T7	6519	12	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	3	0	0
T13	1375	11	0	0
T14	2219	48	0	0
T15	2023	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	224054	0	0
GntImpliesValid_A	417469597	224054	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	224054	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	4721592	0	0
ReadyAndValidImplyGrant_A	417469597	224054	0	0
ReqAndReadyImplyGrant_A	417469597	224054	0	0
ReqImpliesValid_A	417469597	1204401	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	224054	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	4721592	0	0
T1	2179	55	0	0
T2	2729	141	0	0
T3	1878	105	0	0
T7	6519	173	0	0
T10	1644	52	0	0
T11	1456	67	0	0
T12	2621	69	0	0
T13	1375	48	0	0
T14	2219	144	0	0
T15	2023	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	1204401	0	0
T1	2179	15	0	0
T2	2729	23	0	0
T3	1878	20	0	0
T7	6519	25	0	0
T10	1644	27	0	0
T11	1456	15	0	0
T12	2621	32	0	0
T13	1375	9	0	0
T14	2219	74	0	0
T15	2023	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224054	0	0
T1	2179	13	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	9	0	0
T10	1644	14	0	0
T11	1456	15	0	0
T12	2621	12	0	0
T13	1375	9	0	0
T14	2219	46	0	0
T15	2023	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T13 T14 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T13,T14
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	234191	0	0
GntImpliesValid_A	417469597	234191	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	234191	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3059552	0	0
ReadyAndValidImplyGrant_A	417469597	234191	0	0
ReqAndReadyImplyGrant_A	417469597	234191	0	0
ReqImpliesValid_A	417469597	623458	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	234191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3059552	0	0
T1	2179	16	0	0
T2	2729	18	0	0
T3	1878	12	0	0
T7	6519	83	0	0
T10	1644	12	0	0
T11	1456	10	0	0
T12	2621	13	0	0
T13	1375	14	0	0
T14	2219	46	0	0
T15	2023	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	623458	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	15	0	0
T14	2219	57	0	0
T15	2023	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234191	0	0
T1	2179	16	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	12	0	0
T10	1644	11	0	0
T11	1456	9	0	0
T12	2621	12	0	0
T13	1375	14	0	0
T14	2219	51	0	0
T15	2023	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	220678	0	0
GntImpliesValid_A	417469597	220678	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	220678	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3018027	0	0
ReadyAndValidImplyGrant_A	417469597	220678	0	0
ReqAndReadyImplyGrant_A	417469597	220678	0	0
ReqImpliesValid_A	417469597	601690	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	220678	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3018027	0	0
T1	2179	16	0	0
T2	2729	11	0	0
T3	1878	7	0	0
T7	6519	85	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	16	0	0
T14	2219	37	0	0
T15	2023	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	601690	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	24	0	0
T10	1644	10	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	15	0	0
T14	2219	46	0	0
T15	2023	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	220678	0	0
T1	2179	15	0	0
T2	2729	10	0	0
T3	1878	6	0	0
T7	6519	13	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T12 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T12,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T12,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	224358	0	0
GntImpliesValid_A	417469597	224358	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	224358	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3044247	0	0
ReadyAndValidImplyGrant_A	417469597	224358	0	0
ReqAndReadyImplyGrant_A	417469597	224358	0	0
ReqImpliesValid_A	417469597	621021	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	224358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3044247	0	0
T1	2179	13	0	0
T2	2729	9	0	0
T3	1878	14	0	0
T7	6519	92	0	0
T10	1644	11	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	621021	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	15	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	15	0	0
T13	1375	12	0	0
T14	2219	38	0	0
T15	2023	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	224358	0	0
T1	2179	12	0	0
T2	2729	8	0	0
T3	1878	14	0	0
T7	6519	12	0	0
T10	1644	10	0	0
T11	1456	9	0	0
T12	2621	13	0	0
T13	1375	11	0	0
T14	2219	37	0	0
T15	2023	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	222650	0	0
GntImpliesValid_A	417469597	222650	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	222650	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	2983015	0	0
ReadyAndValidImplyGrant_A	417469597	222650	0	0
ReqAndReadyImplyGrant_A	417469597	222650	0	0
ReqImpliesValid_A	417469597	632913	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	222650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2983015	0	0
T1	2179	13	0	0
T2	2729	13	0	0
T3	1878	14	0	0
T7	6519	72	0	0
T10	1644	8	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	14	0	0
T14	2219	36	0	0
T15	2023	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	632913	0	0
T1	2179	12	0	0
T2	2729	14	0	0
T3	1878	13	0	0
T7	6519	17	0	0
T10	1644	7	0	0
T11	1456	12	0	0
T12	2621	8	0	0
T13	1375	17	0	0
T14	2219	43	0	0
T15	2023	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	222650	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	12	0	0
T10	1644	7	0	0
T11	1456	11	0	0
T12	2621	7	0	0
T13	1375	15	0	0
T14	2219	39	0	0
T15	2023	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	229317	0	0
GntImpliesValid_A	417469597	229317	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	229317	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3002165	0	0
ReadyAndValidImplyGrant_A	417469597	229317	0	0
ReqAndReadyImplyGrant_A	417469597	229317	0	0
ReqImpliesValid_A	417469597	655060	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	229317	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3002165	0	0
T1	2179	12	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	103	0	0
T10	1644	14	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	19	0	0
T14	2219	39	0	0
T15	2023	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	655060	0	0
T1	2179	11	0	0
T2	2729	13	0	0
T3	1878	13	0	0
T7	6519	14	0	0
T10	1644	17	0	0
T11	1456	14	0	0
T12	2621	13	0	0
T13	1375	18	0	0
T14	2219	44	0	0
T15	2023	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229317	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	12	0	0
T7	6519	14	0	0
T10	1644	15	0	0
T11	1456	12	0	0
T12	2621	12	0	0
T13	1375	18	0	0
T14	2219	41	0	0
T15	2023	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T12 T17 T18 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T17,T18
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T17,T18

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T17,T18
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	231755	0	0
GntImpliesValid_A	417469597	231755	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	231755	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3019084	0	0
ReadyAndValidImplyGrant_A	417469597	231755	0	0
ReqAndReadyImplyGrant_A	417469597	231755	0	0
ReqImpliesValid_A	417469597	660045	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	231755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3019084	0	0
T1	2179	18	0	0
T2	2729	18	0	0
T3	1878	9	0	0
T7	6519	78	0	0
T10	1644	6	0	0
T11	1456	5	0	0
T12	2621	9	0	0
T13	1375	12	0	0
T14	2219	32	0	0
T15	2023	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	660045	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	231755	0	0
T1	2179	17	0	0
T2	2729	17	0	0
T3	1878	8	0	0
T7	6519	7	0	0
T10	1644	5	0	0
T11	1456	4	0	0
T12	2621	9	0	0
T13	1375	11	0	0
T14	2219	31	0	0
T15	2023	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T14 T15 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T14,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T14,T15
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	213470	0	0
GntImpliesValid_A	417469597	213470	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	213470	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	2987509	0	0
ReadyAndValidImplyGrant_A	417469597	213470	0	0
ReqAndReadyImplyGrant_A	417469597	213470	0	0
ReqImpliesValid_A	417469597	561815	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	213470	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2987509	0	0
T1	2179	16	0	0
T2	2729	21	0	0
T3	1878	11	0	0
T7	6519	77	0	0
T10	1644	6	0	0
T11	1456	12	0	0
T12	2621	13	0	0
T13	1375	5	0	0
T14	2219	39	0	0
T15	2023	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	561815	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	12	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	40	0	0
T15	2023	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	213470	0	0
T1	2179	15	0	0
T2	2729	20	0	0
T3	1878	11	0	0
T7	6519	10	0	0
T10	1644	5	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	4	0	0
T14	2219	39	0	0
T15	2023	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T12 T14 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T12,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T12,T14
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	214516	0	0
GntImpliesValid_A	417469597	214516	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	214516	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3014045	0	0
ReadyAndValidImplyGrant_A	417469597	214516	0	0
ReqAndReadyImplyGrant_A	417469597	214516	0	0
ReqImpliesValid_A	417469597	605151	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	214516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3014045	0	0
T1	2179	15	0	0
T2	2729	16	0	0
T3	1878	11	0	0
T7	6519	151	0	0
T10	1644	16	0	0
T11	1456	11	0	0
T12	2621	11	0	0
T13	1375	12	0	0
T14	2219	40	0	0
T15	2023	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	605151	0	0
T1	2179	14	0	0
T2	2729	19	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	14	0	0
T13	1375	11	0	0
T14	2219	43	0	0
T15	2023	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	214516	0	0
T1	2179	14	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	17	0	0
T10	1644	15	0	0
T11	1456	10	0	0
T12	2621	12	0	0
T13	1375	11	0	0
T14	2219	41	0	0
T15	2023	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T11 T14 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T11,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T11,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T11,T14
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	234819	0	0
GntImpliesValid_A	417469597	234819	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	234819	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3041283	0	0
ReadyAndValidImplyGrant_A	417469597	234819	0	0
ReqAndReadyImplyGrant_A	417469597	234819	0	0
ReqImpliesValid_A	417469597	575059	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	234819	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3041283	0	0
T1	2179	10	0	0
T2	2729	14	0	0
T3	1878	16	0	0
T7	6519	174	0	0
T10	1644	13	0	0
T11	1456	12	0	0
T12	2621	11	0	0
T13	1375	31	0	0
T14	2219	48	0	0
T15	2023	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	575059	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	26	0	0
T10	1644	12	0	0
T11	1456	13	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	63	0	0
T15	2023	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	234819	0	0
T1	2179	9	0	0
T2	2729	13	0	0
T3	1878	15	0	0
T7	6519	21	0	0
T10	1644	12	0	0
T11	1456	12	0	0
T12	2621	10	0	0
T13	1375	30	0	0
T14	2219	55	0	0
T15	2023	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T13 T15 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T15
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T13,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T13,T15
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	235378	0	0
GntImpliesValid_A	417469597	235378	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	235378	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3042373	0	0
ReadyAndValidImplyGrant_A	417469597	235378	0	0
ReqAndReadyImplyGrant_A	417469597	235378	0	0
ReqImpliesValid_A	417469597	616651	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	235378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3042373	0	0
T1	2179	11	0	0
T2	2729	13	0	0
T3	1878	9	0	0
T7	6519	45	0	0
T10	1644	10	0	0
T11	1456	11	0	0
T12	2621	9	0	0
T13	1375	18	0	0
T14	2219	40	0	0
T15	2023	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	616651	0	0
T1	2179	10	0	0
T2	2729	14	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	19	0	0
T14	2219	39	0	0
T15	2023	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	235378	0	0
T1	2179	10	0	0
T2	2729	13	0	0
T3	1878	8	0	0
T7	6519	4	0	0
T10	1644	9	0	0
T11	1456	10	0	0
T12	2621	8	0	0
T13	1375	18	0	0
T14	2219	39	0	0
T15	2023	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	229899	0	0
GntImpliesValid_A	417469597	229899	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	229899	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3047737	0	0
ReadyAndValidImplyGrant_A	417469597	229899	0	0
ReqAndReadyImplyGrant_A	417469597	229899	0	0
ReqImpliesValid_A	417469597	665134	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	229899	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3047737	0	0
T1	2179	12	0	0
T2	2729	13	0	0
T3	1878	14	0	0
T7	6519	99	0	0
T10	1644	14	0	0
T11	1456	11	0	0
T12	2621	12	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	665134	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	15	0	0
T7	6519	34	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	16	0	0
T14	2219	42	0	0
T15	2023	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	229899	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	14	0	0
T7	6519	14	0	0
T10	1644	13	0	0
T11	1456	10	0	0
T12	2621	11	0	0
T13	1375	15	0	0
T14	2219	41	0	0
T15	2023	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	215310	0	0
GntImpliesValid_A	417469597	215310	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	215310	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3034861	0	0
ReadyAndValidImplyGrant_A	417469597	215310	0	0
ReqAndReadyImplyGrant_A	417469597	215310	0	0
ReqImpliesValid_A	417469597	553921	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	215310	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3034861	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	39	0	0
T10	1644	12	0	0
T11	1456	9	0	0
T12	2621	10	0	0
T13	1375	12	0	0
T14	2219	24	0	0
T15	2023	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	553921	0	0
T1	2179	10	0	0
T2	2729	18	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	11	0	0
T13	1375	11	0	0
T14	2219	25	0	0
T15	2023	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	215310	0	0
T1	2179	9	0	0
T2	2729	17	0	0
T3	1878	10	0	0
T7	6519	8	0	0
T10	1644	11	0	0
T11	1456	8	0	0
T12	2621	10	0	0
T13	1375	11	0	0
T14	2219	24	0	0
T15	2023	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T10 T14 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T14
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	230750	0	0
GntImpliesValid_A	417469597	230750	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	230750	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	3027440	0	0
ReadyAndValidImplyGrant_A	417469597	230750	0	0
ReqAndReadyImplyGrant_A	417469597	230750	0	0
ReqImpliesValid_A	417469597	611868	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	230750	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	3027440	0	0
T1	2179	21	0	0
T2	2729	17	0	0
T3	1878	11	0	0
T7	6519	64	0	0
T10	1644	11	0	0
T11	1456	12	0	0
T12	2621	11	0	0
T13	1375	8	0	0
T14	2219	30	0	0
T15	2023	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	611868	0	0
T1	2179	24	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	12	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	33	0	0
T15	2023	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	230750	0	0
T1	2179	22	0	0
T2	2729	16	0	0
T3	1878	10	0	0
T7	6519	10	0	0
T10	1644	11	0	0
T11	1456	11	0	0
T12	2621	10	0	0
T13	1375	7	0	0
T14	2219	31	0	0
T15	2023	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	225637	0	0
GntImpliesValid_A	417469597	225637	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	225637	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	2990789	0	0
ReadyAndValidImplyGrant_A	417469597	225637	0	0
ReqAndReadyImplyGrant_A	417469597	225637	0	0
ReqImpliesValid_A	417469597	592214	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	0	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	225637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2990789	0	0
T1	2179	12	0	0
T2	2729	11	0	0
T3	1878	17	0	0
T7	6519	84	0	0
T10	1644	8	0	0
T11	1456	22	0	0
T12	2621	9	0	0
T13	1375	8	0	0
T14	2219	45	0	0
T15	2023	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	592214	0	0
T1	2179	11	0	0
T2	2729	14	0	0
T3	1878	16	0	0
T7	6519	22	0	0
T10	1644	7	0	0
T11	1456	25	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	48	0	0
T15	2023	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	225637	0	0
T1	2179	11	0	0
T2	2729	12	0	0
T3	1878	16	0	0
T7	6519	13	0	0
T10	1644	7	0	0
T11	1456	23	0	0
T12	2621	8	0	0
T13	1375	7	0	0
T14	2219	46	0	0
T15	2023	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	908819	0	0
GntImpliesValid_A	417469597	908819	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	908819	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	11569270	0	0
ReadyAndValidImplyGrant_A	417469597	908819	0	0
ReqAndReadyImplyGrant_A	417469597	908819	0	0
ReqImpliesValid_A	417469597	2414330	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	19260	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	908819	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	11569270	0	0
T1	2179	1	0	0
T2	2729	1	0	0
T3	1878	1	0	0
T7	6519	369	0	0
T10	1644	1	0	0
T11	1456	1	0	0
T12	2621	1	0	0
T13	1375	1	0	0
T14	2219	1	0	0
T15	2023	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	2414330	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	92	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	19260	0	900
T8	9172	0	0	1
T9	192737	0	0	1
T13	1375	1	0	1
T14	2219	1	0	1
T15	2023	0	0	1
T16	5025	3	0	1
T17	9162	8	0	1
T18	14715	10	0	1
T19	9121	11	0	1
T23	0	13	0	0
T24	0	1	0	0
T26	0	4	0	0
T27	0	19	0	0
T28	22596	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	908819	0	0
T1	2179	73	0	0
T2	2729	44	0	0
T3	1878	54	0	0
T7	6519	52	0	0
T10	1644	50	0	0
T11	1456	35	0	0
T12	2621	62	0	0
T13	1375	44	0	0
T14	2219	198	0	0
T15	2023	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417469597	417337914	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417469597	899639	0	0
GntImpliesValid_A	417469597	899639	0	0
GrantKnown_A	417469597	417337914	0	0
IdxKnown_A	417469597	417337914	0	0
IndexIsCorrect_A	417469597	899639	0	0
LockArbDecision_A	417469597	0	0	0
NoReadyValidNoGrant_A	417469597	349884984	0	0
ReadyAndValidImplyGrant_A	417469597	899639	0	0
ReqAndReadyImplyGrant_A	417469597	899639	0	0
ReqImpliesValid_A	417469597	13343495	0	0
ReqStaysHighUntilGranted0_M	417469597	0	0	0
RoundRobin_A	417469597	31269	0	900
ValidKnown_A	417469597	417337914	0	0
gen_data_port_assertion.DataFlow_A	417469597	899639	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	349884984	0	0
T1	2179	1	0	0
T2	2729	1	0	0
T3	1878	1	0	0
T7	6519	5593	0	0
T10	1644	1	0	0
T11	1456	1	0	0
T12	2621	1	0	0
T13	1375	1	0	0
T14	2219	1	0	0
T15	2023	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	13343495	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	369	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	31269	0	900
T8	9172	0	0	1
T9	192737	0	0	1
T14	2219	4	0	1
T15	2023	0	0	1
T16	5025	6	0	1
T17	9162	14	0	1
T18	14715	3	0	1
T19	9121	6	0	1
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	11	0	0
T25	0	184	0	0
T28	22596	0	0	1
T29	39055	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	417337914	0	0
T1	2179	2150	0	0
T2	2729	2670	0	0
T3	1878	1854	0	0
T7	6519	6478	0	0
T10	1644	1636	0	0
T11	1456	1440	0	0
T12	2621	2534	0	0
T13	1375	1324	0	0
T14	2219	2209	0	0
T15	2023	1998	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417469597	899639	0	0
T1	2179	39	0	0
T2	2729	54	0	0
T3	1878	50	0	0
T7	6519	44	0	0
T10	1644	57	0	0
T11	1456	50	0	0
T12	2621	62	0	0
T13	1375	47	0	0
T14	2219	191	0	0
T15	2023	64	0	0