Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2436699 1 T1 98 T2 164 T3 591
values[2] 176105 1 T1 10 T2 9 T3 40
values[3] 36683 1 T3 1 T7 3 T23 1
values[4] 22165 1 T22 258 T58 167 T81 65
values[5] 15230 1 T22 205 T58 113 T81 13
values[6] 11995 1 T22 178 T58 119 T81 12
values[7] 10009 1 T22 134 T58 137 T81 50
values[8] 8641 1 T22 125 T58 92 T81 16
values[9] 7488 1 T22 93 T58 104 T81 3
values[10] 6562 1 T22 78 T58 94 T81 2
values[11] 5717 1 T22 62 T58 63 T81 1
values[12] 5262 1 T22 65 T58 40 T81 1
values[13] 4790 1 T22 69 T58 38 T81 1
values[14] 4204 1 T22 46 T58 33 T81 1
values[15] 3853 1 T22 30 T58 42 T81 2
values[16] 3523 1 T22 32 T58 40 T81 1
values[17] 3351 1 T22 32 T58 33 T81 2
values[18] 3303 1 T22 58 T58 29 T81 5
values[19] 3082 1 T22 41 T58 26 T81 4
values[20] 2978 1 T22 25 T58 23 T81 9
values[21] 2798 1 T22 30 T58 16 T81 1
values[22] 2563 1 T22 27 T58 19 T81 2
values[23] 2401 1 T22 38 T58 17 T81 2
values[24] 2366 1 T22 32 T58 14 T81 1
values[25] 2375 1 T22 37 T58 17 T81 1
values[26] 2314 1 T22 14 T58 18 T81 1
values[27] 2161 1 T22 19 T58 18 T81 1
values[28] 2145 1 T22 18 T58 10 T81 1
values[29] 1945 1 T22 8 T58 10 T81 1
values[30] 1830 1 T22 10 T58 12 T81 1
values[31] 1862 1 T22 21 T58 9 T81 1
values[32] 1889 1 T22 28 T58 17 T81 1
values[33] 1777 1 T22 21 T58 14 T81 1
values[34] 1703 1 T22 23 T58 9 T81 2
values[35] 1655 1 T22 32 T58 15 T81 2
values[36] 1576 1 T22 44 T58 8 T81 4
values[37] 1569 1 T22 36 T58 8 T81 1
values[38] 1537 1 T22 23 T58 9 T81 1
values[39] 1511 1 T22 39 T58 7 T81 2
values[40] 1464 1 T22 29 T58 15 T81 2
values[41] 1380 1 T22 19 T58 12 T81 4
values[42] 1412 1 T22 20 T58 15 T81 1
values[43] 1407 1 T22 16 T58 14 T81 1
values[44] 1384 1 T22 13 T58 8 T81 4
values[45] 1352 1 T22 10 T58 5 T81 6
values[46] 1319 1 T22 10 T58 5 T81 1
values[47] 1287 1 T22 11 T58 7 T81 2
values[48] 1222 1 T22 12 T58 10 T81 3
values[49] 1269 1 T22 13 T58 8 T81 5
values[50] 1305 1 T22 16 T58 6 T81 4
values[51] 1254 1 T22 12 T58 6 T81 2
values[52] 1316 1 T22 19 T58 4 T81 1
values[53] 1299 1 T22 15 T58 6 T81 1
values[54] 1224 1 T22 8 T58 7 T81 2
values[55] 1224 1 T22 13 T58 4 T81 2
values[56] 1211 1 T22 25 T58 5 T81 1
values[57] 1215 1 T22 16 T58 13 T81 2
values[58] 1219 1 T22 12 T58 4 T81 1
values[59] 1155 1 T22 10 T58 6 T81 3
values[60] 1206 1 T22 13 T58 12 T81 1
values[61] 1408 1 T22 17 T58 11 T81 1
values[62] 2484 1 T22 39 T58 26 T81 1
values[63] 7387 1 T22 130 T58 107 T81 3
values[64] 104586 1 T22 205 T58 173 T81 88


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2458646 1 T1 109 T2 157 T3 434
values[2] 407190 1 T1 28 T2 36 T3 92
values[3] 39766 1 T2 2 T3 9 T8 1
values[4] 8203 1 T7 1 T14 2 T26 2
values[5] 3736 1 T25 1 T22 35 T58 3
values[6] 2605 1 T22 31 T58 3 T89 1
values[7] 2032 1 T22 8 T58 2 T89 1
values[8] 1768 1 T22 1 T58 3 T81 1
values[9] 1565 1 T58 2 T81 1 T53 1
values[10] 1460 1 T58 2 T81 1 T53 2
values[11] 1407 1 T58 1 T81 1 T53 2
values[12] 1400 1 T58 3 T81 1 T53 1
values[13] 1251 1 T58 2 T81 1 T53 2
values[14] 1161 1 T58 2 T81 5 T53 2
values[15] 1096 1 T58 1 T81 3 T53 1
values[16] 976 1 T58 1 T81 6 T53 2
values[17] 866 1 T58 1 T81 4 T53 3
values[18] 810 1 T58 1 T81 4 T53 2
values[19] 834 1 T58 1 T81 1 T53 2
values[20] 838 1 T58 1 T81 1 T53 2
values[21] 800 1 T58 2 T81 1 T53 2
values[22] 788 1 T58 3 T81 1 T53 2
values[23] 797 1 T58 4 T81 1 T53 1
values[24] 705 1 T58 3 T81 3 T53 1
values[25] 713 1 T58 1 T81 1 T53 2
values[26] 659 1 T58 2 T81 1 T53 3
values[27] 600 1 T58 3 T81 1 T53 2
values[28] 578 1 T58 2 T81 1 T53 2
values[29] 563 1 T58 2 T81 1 T53 2
values[30] 501 1 T58 1 T81 1 T53 2
values[31] 506 1 T58 2 T81 1 T53 2
values[32] 529 1 T58 2 T81 1 T53 2
values[33] 526 1 T58 2 T81 2 T53 2
values[34] 509 1 T58 2 T81 10 T53 2
values[35] 493 1 T58 1 T81 1 T53 2
values[36] 428 1 T58 1 T81 3 T53 2
values[37] 446 1 T58 2 T81 2 T53 2
values[38] 466 1 T58 1 T81 5 T53 2
values[39] 476 1 T58 3 T81 3 T53 2
values[40] 435 1 T58 2 T81 2 T53 2
values[41] 443 1 T58 1 T81 1 T53 2
values[42] 473 1 T58 2 T81 1 T53 2
values[43] 462 1 T58 1 T81 3 T53 2
values[44] 425 1 T58 1 T81 1 T53 2
values[45] 425 1 T58 1 T81 1 T53 2
values[46] 413 1 T58 1 T81 1 T53 2
values[47] 408 1 T58 2 T81 2 T53 1
values[48] 394 1 T58 1 T81 3 T53 1
values[49] 420 1 T58 2 T81 2 T53 2
values[50] 409 1 T58 1 T81 3 T53 4
values[51] 389 1 T58 1 T81 3 T53 2
values[52] 407 1 T58 1 T81 2 T53 2
values[53] 410 1 T58 1 T81 2 T53 2
values[54] 377 1 T58 2 T81 1 T53 2
values[55] 383 1 T58 5 T81 2 T53 2
values[56] 374 1 T58 4 T81 1 T53 2
values[57] 385 1 T58 1 T81 4 T53 2
values[58] 393 1 T58 1 T81 1 T53 2
values[59] 364 1 T58 1 T81 1 T53 2
values[60] 340 1 T58 1 T81 2 T53 2
values[61] 411 1 T58 2 T81 1 T53 2
values[62] 643 1 T58 4 T81 2 T53 2
values[63] 2823 1 T58 23 T81 10 T53 2
values[64] 26498 1 T58 81 T81 125 T53 89


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 308597 1 T1 1 T2 1 T3 6
values[2] 1728398 1 T1 97 T2 81 T3 212
values[3] 515327 1 T1 7 T2 20 T3 409
values[4] 49326 1 T2 1 T3 6 T23 2
values[5] 31669 1 T25 1 T22 301 T58 145
values[6] 23753 1 T22 225 T58 117 T87 1
values[7] 19007 1 T22 195 T58 131 T81 1
values[8] 15536 1 T22 183 T58 149 T81 4
values[9] 13080 1 T22 158 T58 144 T81 1
values[10] 11358 1 T22 107 T58 126 T81 4
values[11] 9859 1 T22 77 T58 84 T81 3
values[12] 8793 1 T22 67 T58 57 T81 1
values[13] 7839 1 T22 46 T58 47 T81 1
values[14] 7064 1 T22 58 T58 26 T81 2
values[15] 6291 1 T22 45 T58 29 T81 2
values[16] 5581 1 T22 45 T58 49 T81 3
values[17] 5071 1 T22 47 T58 34 T81 1
values[18] 4678 1 T22 59 T58 47 T81 2
values[19] 4279 1 T22 69 T58 36 T81 1
values[20] 3921 1 T22 40 T58 17 T81 1
values[21] 3680 1 T22 16 T58 18 T81 1
values[22] 3290 1 T22 23 T58 19 T81 1
values[23] 2888 1 T22 29 T58 21 T81 1
values[24] 2652 1 T22 34 T58 13 T81 1
values[25] 2379 1 T22 29 T58 19 T81 4
values[26] 2381 1 T22 22 T58 32 T81 1
values[27] 2364 1 T22 28 T58 23 T81 1
values[28] 2109 1 T22 32 T58 29 T81 1
values[29] 2038 1 T22 27 T58 12 T81 1
values[30] 1821 1 T22 15 T58 12 T81 2
values[31] 1790 1 T22 17 T58 11 T81 1
values[32] 1726 1 T22 23 T58 7 T81 8
values[33] 1686 1 T22 24 T58 8 T81 4
values[34] 1657 1 T22 25 T58 10 T81 2
values[35] 1645 1 T22 25 T58 6 T81 2
values[36] 1626 1 T22 22 T58 9 T81 2
values[37] 1566 1 T22 16 T58 7 T81 3
values[38] 1586 1 T22 26 T58 10 T81 2
values[39] 1492 1 T22 18 T58 7 T81 1
values[40] 1417 1 T22 15 T58 6 T81 1
values[41] 1430 1 T22 26 T58 5 T81 1
values[42] 1423 1 T22 24 T58 12 T81 1
values[43] 1447 1 T22 17 T58 11 T81 1
values[44] 1446 1 T22 27 T58 13 T81 2
values[45] 1373 1 T22 34 T58 10 T81 2
values[46] 1366 1 T22 22 T58 7 T81 1
values[47] 1399 1 T22 18 T58 9 T81 3
values[48] 1386 1 T22 27 T58 9 T81 3
values[49] 1307 1 T22 28 T58 8 T81 2
values[50] 1323 1 T22 14 T58 11 T81 2
values[51] 1345 1 T22 32 T58 13 T81 1
values[52] 1294 1 T22 28 T58 7 T81 1
values[53] 1295 1 T22 15 T58 5 T81 1
values[54] 1305 1 T22 22 T58 7 T81 1
values[55] 1303 1 T22 27 T58 12 T81 3
values[56] 1246 1 T22 17 T58 4 T81 1
values[57] 1274 1 T22 16 T58 8 T81 1
values[58] 1270 1 T22 9 T58 18 T81 2
values[59] 1241 1 T22 15 T58 7 T81 1
values[60] 1237 1 T22 26 T58 10 T81 1
values[61] 1415 1 T22 20 T58 5 T81 1
values[62] 2108 1 T22 32 T58 15 T81 1
values[63] 6946 1 T22 115 T58 85 T81 2
values[64] 107021 1 T22 267 T58 250 T81 170

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