Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1608948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255741

1

T1

12

T2

25

T3

99

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632093	1			T1	33		T2	65		T3	191
values[0x0]	600284	1			T1	41		T2	52		T3	231
values[0x1]	632312	1			T1	34		T2	56		T3	210

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1243908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

620781

1

T1

36

T2

64

T3

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29913	1			T1	8		T2	1		T3	9
valid_sources[0x01]	29788	1			T2	1		T3	15		T9	15
valid_sources[0x02]	29993	1			T1	2		T3	1		T9	12
valid_sources[0x03]	29500	1			T3	16		T9	14		T7	1
valid_sources[0x04]	29378	1			T3	14		T9	19		T10	19
valid_sources[0x05]	28605	1			T2	6		T3	17		T8	2
valid_sources[0x06]	29453	1			T2	4		T3	2		T8	1
valid_sources[0x07]	29963	1			T3	9		T9	9		T13	8
valid_sources[0x08]	29574	1			T1	3		T2	2		T3	3
valid_sources[0x09]	29046	1			T2	3		T3	18		T9	15
valid_sources[0x0a]	29759	1			T2	2		T3	12		T9	18
valid_sources[0x0b]	28306	1			T2	4		T3	8		T8	1
valid_sources[0x0c]	28664	1			T2	1		T3	17		T9	12
valid_sources[0x0d]	30293	1			T1	8		T2	3		T3	1
valid_sources[0x0e]	29401	1			T2	4		T3	11		T9	21
valid_sources[0x0f]	28037	1			T2	3		T3	13		T8	1
valid_sources[0x10]	30221	1			T1	4		T3	2		T9	12
valid_sources[0x11]	28875	1			T1	3		T2	4		T3	9
valid_sources[0x12]	29368	1			T2	4		T3	8		T9	15
valid_sources[0x13]	29112	1			T2	5		T3	22		T9	16
valid_sources[0x14]	28700	1			T1	4		T2	1		T3	13
valid_sources[0x15]	28983	1			T1	3		T2	2		T9	13
valid_sources[0x16]	29089	1			T1	1		T2	1		T3	1
valid_sources[0x17]	28708	1			T1	5		T3	15		T9	18
valid_sources[0x18]	29011	1			T2	3		T3	18		T8	1
valid_sources[0x19]	29278	1			T2	4		T3	7		T9	14
valid_sources[0x1a]	29475	1			T1	4		T2	3		T3	13
valid_sources[0x1b]	28863	1			T2	4		T3	12		T8	1
valid_sources[0x1c]	28899	1			T2	2		T3	1		T9	18
valid_sources[0x1d]	28796	1			T1	11		T2	2		T3	19
valid_sources[0x1e]	28352	1			T2	1		T3	8		T9	17
valid_sources[0x1f]	28933	1			T2	1		T3	14		T9	21
valid_sources[0x20]	28660	1			T1	3		T2	5		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26927

1

T2

3

T3

7

T9

12

values[0x0]

all_enables

biggest_size

202279

1

T1

12

T2

18

T3

78

values[0x1]

all_enables

biggest_size

26535

1

T2

4

T3

14

T9

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1620839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263877

1

T1

19

T2

26

T3

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	644542	1			T1	47		T2	67		T3	177
values[0x0]	595159	1			T1	38		T2	61		T3	172
values[0x1]	645015	1			T1	52		T2	67		T3	186

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1243795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640921

1

T1

47

T2

68

T3

174

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28757	1			T1	1		T2	3		T3	4
valid_sources[0x01]	29509	1			T1	1		T2	3		T3	10
valid_sources[0x02]	29197	1			T3	5		T9	34		T11	11
valid_sources[0x03]	29140	1			T1	2		T2	6		T3	13
valid_sources[0x04]	29856	1			T1	7		T2	1		T3	4
valid_sources[0x05]	28442	1			T2	2		T3	10		T8	1
valid_sources[0x06]	29060	1			T1	2		T2	4		T3	9
valid_sources[0x07]	29238	1			T1	1		T2	3		T3	11
valid_sources[0x08]	28478	1			T1	1		T2	5		T3	7
valid_sources[0x09]	29573	1			T1	2		T2	1		T3	4
valid_sources[0x0a]	30080	1			T1	1		T3	9		T9	36
valid_sources[0x0b]	29495	1			T2	1		T3	9		T9	21
valid_sources[0x0c]	29542	1			T1	2		T2	5		T3	16
valid_sources[0x0d]	29667	1			T2	8		T3	6		T9	18
valid_sources[0x0e]	29563	1			T1	3		T2	1		T3	12
valid_sources[0x0f]	29133	1			T1	3		T2	2		T3	6
valid_sources[0x10]	29635	1			T1	1		T2	9		T3	9
valid_sources[0x11]	29302	1			T1	5		T2	6		T3	6
valid_sources[0x12]	29700	1			T1	1		T2	1		T3	10
valid_sources[0x13]	29886	1			T1	3		T2	3		T3	7
valid_sources[0x14]	29806	1			T3	3		T8	1		T9	5
valid_sources[0x15]	28982	1			T1	1		T2	6		T3	3
valid_sources[0x16]	28503	1			T2	2		T3	11		T9	13
valid_sources[0x17]	29736	1			T1	3		T2	3		T3	11
valid_sources[0x18]	29630	1			T1	2		T2	2		T3	6
valid_sources[0x19]	29361	1			T1	4		T2	2		T3	7
valid_sources[0x1a]	29029	1			T1	2		T2	5		T3	9
valid_sources[0x1b]	29773	1			T1	2		T2	2		T3	6
valid_sources[0x1c]	29546	1			T1	1		T2	2		T3	7
valid_sources[0x1d]	29933	1			T1	3		T2	3		T3	8
valid_sources[0x1e]	30064	1			T1	2		T2	2		T3	6
valid_sources[0x1f]	30106	1			T1	1		T2	3		T3	11
valid_sources[0x20]	29683	1			T1	2		T2	1		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27209

1

T1

1

T2

3

T3

7

values[0x0]

all_enables

biggest_size

208883

1

T1

12

T2

19

T3

63

values[0x1]

all_enables

biggest_size

27785

1

T1

6

T2

4

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1615811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257690

1

T1

13

T2

14

T3

91

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635265	1			T1	45		T2	36		T3	183
values[0x0]	602472	1			T1	34		T2	37		T3	229
values[0x1]	635764	1			T1	26		T2	30		T3	221

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249189	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

624312

1

T1

35

T2

37

T3

205

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29612	1			T3	3		T9	1		T23	26
valid_sources[0x01]	29569	1			T1	22		T3	15		T9	27
valid_sources[0x02]	28594	1			T9	21		T11	4		T12	1
valid_sources[0x03]	29235	1			T2	3		T3	25		T9	21
valid_sources[0x04]	29778	1			T3	12		T9	20		T7	1
valid_sources[0x05]	28913	1			T3	9		T9	55		T12	4
valid_sources[0x06]	28943	1			T2	6		T3	8		T9	19
valid_sources[0x07]	28819	1			T3	4		T9	28		T12	3
valid_sources[0x08]	29571	1			T3	10		T9	27		T7	1
valid_sources[0x09]	29176	1			T3	27		T9	1		T12	1
valid_sources[0x0a]	28810	1			T3	11		T9	15		T7	1
valid_sources[0x0b]	28911	1			T1	1		T3	23		T9	6
valid_sources[0x0c]	29540	1			T3	11		T9	10		T12	1
valid_sources[0x0d]	28563	1			T3	12		T8	2		T9	27
valid_sources[0x0e]	29964	1			T2	4		T3	3		T9	17
valid_sources[0x0f]	28855	1			T3	4		T9	29		T10	17
valid_sources[0x10]	30728	1			T3	11		T8	4		T9	30
valid_sources[0x11]	29318	1			T3	5		T8	1		T7	2
valid_sources[0x12]	29403	1			T1	2		T3	11		T9	6
valid_sources[0x13]	29374	1			T3	16		T9	18		T10	18
valid_sources[0x14]	28500	1			T3	14		T8	1		T10	32
valid_sources[0x15]	28513	1			T3	17		T8	3		T9	4
valid_sources[0x16]	28595	1			T3	6		T9	22		T7	1
valid_sources[0x17]	30155	1			T2	4		T3	9		T11	15
valid_sources[0x18]	29901	1			T2	7		T3	9		T9	46
valid_sources[0x19]	29272	1			T3	18		T8	1		T9	17
valid_sources[0x1a]	28996	1			T3	5		T9	3		T7	1
valid_sources[0x1b]	28362	1			T3	8		T9	25		T10	52
valid_sources[0x1c]	29157	1			T2	7		T9	29		T10	11
valid_sources[0x1d]	29630	1			T3	32		T9	6		T10	27
valid_sources[0x1e]	29187	1			T2	14		T3	4		T9	30
valid_sources[0x1f]	29048	1			T1	25		T3	4		T7	2
valid_sources[0x20]	29551	1			T1	13		T3	7		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27029

1

T1

3

T3

6

T9

16

values[0x0]

all_enables

biggest_size

203468

1

T1

10

T2

13

T3

74

values[0x1]

all_enables

biggest_size

27193

1

T2

1

T3

11

T9

21