Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7976259	0	0
GntImpliesValid_A	2147483647	7976259	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7976259	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	429352257	0	0
ReadyAndValidImplyGrant_A	2147483647	7976259	0	0
ReqAndReadyImplyGrant_A	2147483647	7976259	0	0
ReqImpliesValid_A	2147483647	32941485	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51640	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7976259	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42768	41352	0	0
T2	293232	292224	0	0
T3	413256	412272	0	0
T7	550344	549024	0	0
T8	61392	60504	0	0
T9	183432	182448	0	0
T10	975216	974592	0	0
T11	273408	272088	0	0
T12	25704	24936	0	0
T13	65832	64512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42768	41352	0	0
T2	293232	292224	0	0
T3	413256	412272	0	0
T7	550344	549024	0	0
T8	61392	60504	0	0
T9	183432	182448	0	0
T10	975216	974592	0	0
T11	273408	272088	0	0
T12	25704	24936	0	0
T13	65832	64512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42768	41352	0	0
T2	293232	292224	0	0
T3	413256	412272	0	0
T7	550344	549024	0	0
T8	61392	60504	0	0
T9	183432	182448	0	0
T10	975216	974592	0	0
T11	273408	272088	0	0
T12	25704	24936	0	0
T13	65832	64512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	429352257	0	0
T1	42768	408	0	0
T2	293232	14094	0	0
T3	413256	27746	0	0
T7	550344	32138	0	0
T8	61392	1524	0	0
T9	183432	5964	0	0
T10	975216	54772	0	0
T11	273408	13592	0	0
T12	25704	729	0	0
T13	65832	900	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32941485	0	0
T1	42768	377	0	0
T2	293232	985	0	0
T3	413256	4119	0	0
T7	550344	2925	0	0
T8	61392	1667	0	0
T9	183432	4205	0	0
T10	975216	3828	0	0
T11	273408	1019	0	0
T12	25704	428	0	0
T13	65832	633	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51640	0	21600
T7	45862	0	0	2
T8	5116	5	0	2
T9	15286	8	0	2
T10	81268	1	0	2
T11	22784	0	0	2
T12	2142	1	0	2
T13	5486	0	0	2
T14	7528	11	0	2
T15	7004	1	0	2
T16	0	2	0	0
T17	0	10	0	0
T18	0	1	0	0
T19	0	32	0	0
T20	0	15	0	0
T21	0	8	0	0
T22	0	17	0	0
T23	67846	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42768	41352	0	0
T2	293232	292224	0	0
T3	413256	412272	0	0
T7	550344	549024	0	0
T8	61392	60504	0	0
T9	183432	182448	0	0
T10	975216	974592	0	0
T11	273408	272088	0	0
T12	25704	24936	0	0
T13	65832	64512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7976259	0	0
T1	42768	350	0	0
T2	293232	471	0	0
T3	413256	1800	0	0
T7	550344	1331	0	0
T8	61392	1438	0	0
T9	183432	3267	0	0
T10	975216	2082	0	0
T11	273408	496	0	0
T12	25704	372	0	0
T13	65832	515	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	876785	0	0
GntImpliesValid_A	395159060	876785	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	876785	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	11129122	0	0
ReadyAndValidImplyGrant_A	395159060	876785	0	0
ReqAndReadyImplyGrant_A	395159060	876785	0	0
ReqImpliesValid_A	395159060	2327454	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	876785	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	11129122	0	0
T1	1782	34	0	0
T2	12218	472	0	0
T3	17219	1398	0	0
T7	22931	934	0	0
T8	2558	123	0	0
T9	7643	280	0	0
T10	40634	1898	0	0
T11	11392	376	0	0
T12	1071	27	0	0
T13	2743	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2327454	0	0
T1	1782	55	0	0
T2	12218	99	0	0
T3	17219	277	0	0
T7	22931	250	0	0
T8	2558	216	0	0
T9	7643	447	0	0
T10	40634	272	0	0
T11	11392	92	0	0
T12	1071	30	0	0
T13	2743	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	876785	0	0
T1	1782	44	0	0
T2	12218	66	0	0
T3	17219	182	0	0
T7	22931	152	0	0
T8	2558	169	0	0
T9	7643	363	0	0
T10	40634	250	0	0
T11	11392	46	0	0
T12	1071	28	0	0
T13	2743	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	898970	0	0
GntImpliesValid_A	395159060	898970	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	898970	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	11202087	0	0
ReadyAndValidImplyGrant_A	395159060	898970	0	0
ReqAndReadyImplyGrant_A	395159060	898970	0	0
ReqImpliesValid_A	395159060	2459675	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	898970	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	11202087	0	0
T1	1782	37	0	0
T2	12218	363	0	0
T3	17219	1388	0	0
T7	22931	1048	0	0
T8	2558	128	0	0
T9	7643	270	0	0
T10	40634	1618	0	0
T11	11392	380	0	0
T12	1071	35	0	0
T13	2743	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2459675	0	0
T1	1782	50	0	0
T2	12218	96	0	0
T3	17219	359	0	0
T7	22931	221	0	0
T8	2558	221	0	0
T9	7643	429	0	0
T10	40634	241	0	0
T11	11392	94	0	0
T12	1071	64	0	0
T13	2743	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	898970	0	0
T1	1782	43	0	0
T2	12218	58	0	0
T3	17219	196	0	0
T7	22931	142	0	0
T8	2558	174	0	0
T9	7643	349	0	0
T10	40634	217	0	0
T11	11392	55	0	0
T12	1071	49	0	0
T13	2743	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	223548	0	0
GntImpliesValid_A	395159060	223548	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	223548	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2820620	0	0
ReadyAndValidImplyGrant_A	395159060	223548	0	0
ReqAndReadyImplyGrant_A	395159060	223548	0	0
ReqImpliesValid_A	395159060	533554	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	223548	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2820620	0	0
T1	1782	11	0	0
T2	12218	60	0	0
T3	17219	365	0	0
T7	22931	232	0	0
T8	2558	35	0	0
T9	7643	84	0	0
T10	40634	536	0	0
T11	11392	36	0	0
T12	1071	10	0	0
T13	2743	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	533554	0	0
T1	1782	14	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	36	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223548	0	0
T1	1782	12	0	0
T2	12218	11	0	0
T3	17219	47	0	0
T7	22931	36	0	0
T8	2558	36	0	0
T9	7643	86	0	0
T10	40634	59	0	0
T11	11392	6	0	0
T12	1071	9	0	0
T13	2743	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	220981	0	0
GntImpliesValid_A	395159060	220981	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	220981	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2749402	0	0
ReadyAndValidImplyGrant_A	395159060	220981	0	0
ReqAndReadyImplyGrant_A	395159060	220981	0	0
ReqImpliesValid_A	395159060	570826	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	220981	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2749402	0	0
T1	1782	11	0	0
T2	12218	92	0	0
T3	17219	360	0	0
T7	22931	321	0	0
T8	2558	37	0	0
T9	7643	87	0	0
T10	40634	443	0	0
T11	11392	129	0	0
T12	1071	13	0	0
T13	2743	20	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	570826	0	0
T1	1782	12	0	0
T2	12218	10	0	0
T3	17219	105	0	0
T7	22931	44	0	0
T8	2558	40	0	0
T9	7643	100	0	0
T10	40634	76	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	220981	0	0
T1	1782	11	0	0
T2	12218	10	0	0
T3	17219	57	0	0
T7	22931	38	0	0
T8	2558	38	0	0
T9	7643	93	0	0
T10	40634	60	0	0
T11	11392	18	0	0
T12	1071	12	0	0
T13	2743	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	217304	0	0
GntImpliesValid_A	395159060	217304	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	217304	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	5124250	0	0
ReadyAndValidImplyGrant_A	395159060	217304	0	0
ReqAndReadyImplyGrant_A	395159060	217304	0	0
ReqImpliesValid_A	395159060	1100379	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	217304	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	5124250	0	0
T1	1782	41	0	0
T2	12218	115	0	0
T3	17219	628	0	0
T7	22931	1367	0	0
T8	2558	189	0	0
T9	7643	823	0	0
T10	40634	728	0	0
T11	11392	113	0	0
T12	1071	97	0	0
T13	2743	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	1100379	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	113	0	0
T7	22931	224	0	0
T8	2558	89	0	0
T9	7643	259	0	0
T10	40634	60	0	0
T11	11392	27	0	0
T12	1071	20	0	0
T13	2743	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217304	0	0
T1	1782	7	0	0
T2	12218	8	0	0
T3	17219	67	0	0
T7	22931	36	0	0
T8	2558	45	0	0
T9	7643	83	0	0
T10	40634	60	0	0
T11	11392	11	0	0
T12	1071	12	0	0
T13	2743	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	223753	0	0
GntImpliesValid_A	395159060	223753	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	223753	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	4800198	0	0
ReadyAndValidImplyGrant_A	395159060	223753	0	0
ReqAndReadyImplyGrant_A	395159060	223753	0	0
ReqImpliesValid_A	395159060	1251728	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	223753	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	4800198	0	0
T1	1782	27	0	0
T2	12218	200	0	0
T3	17219	684	0	0
T7	22931	424	0	0
T8	2558	116	0	0
T9	7643	894	0	0
T10	40634	2785	0	0
T11	11392	147	0	0
T12	1071	73	0	0
T13	2743	298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	1251728	0	0
T1	1782	5	0	0
T2	12218	25	0	0
T3	17219	152	0	0
T7	22931	36	0	0
T8	2558	27	0	0
T9	7643	162	0	0
T10	40634	48	0	0
T11	11392	27	0	0
T12	1071	28	0	0
T13	2743	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	223753	0	0
T1	1782	5	0	0
T2	12218	14	0	0
T3	17219	59	0	0
T7	22931	36	0	0
T8	2558	25	0	0
T9	7643	86	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	16	0	0
T13	2743	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	215159	0	0
GntImpliesValid_A	395159060	215159	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	215159	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	5503717	0	0
ReadyAndValidImplyGrant_A	395159060	215159	0	0
ReqAndReadyImplyGrant_A	395159060	215159	0	0
ReqImpliesValid_A	395159060	1252067	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	215159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	5503717	0	0
T1	1782	64	0	0
T2	12218	169	0	0
T3	17219	1503	0	0
T7	22931	789	0	0
T8	2558	183	0	0
T9	7643	967	0	0
T10	40634	3135	0	0
T11	11392	274	0	0
T12	1071	230	0	0
T13	2743	121	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	1252067	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	123	0	0
T7	22931	52	0	0
T8	2558	67	0	0
T9	7643	273	0	0
T10	40634	190	0	0
T11	11392	28	0	0
T12	1071	13	0	0
T13	2743	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	215159	0	0
T1	1782	10	0	0
T2	12218	11	0	0
T3	17219	59	0	0
T7	22931	34	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	65	0	0
T11	11392	13	0	0
T12	1071	13	0	0
T13	2743	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	214802	0	0
GntImpliesValid_A	395159060	214802	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	214802	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	5681794	0	0
ReadyAndValidImplyGrant_A	395159060	214802	0	0
ReqAndReadyImplyGrant_A	395159060	214802	0	0
ReqImpliesValid_A	395159060	1237116	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	214802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	5681794	0	0
T1	1782	49	0	0
T2	12218	178	0	0
T3	17219	528	0	0
T7	22931	2166	0	0
T8	2558	171	0	0
T9	7643	1317	0	0
T10	40634	484	0	0
T11	11392	164	0	0
T12	1071	102	0	0
T13	2743	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	1237116	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	104	0	0
T7	22931	353	0	0
T8	2558	75	0	0
T9	7643	373	0	0
T10	40634	61	0	0
T11	11392	19	0	0
T12	1071	25	0	0
T13	2743	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	214802	0	0
T1	1782	7	0	0
T2	12218	9	0	0
T3	17219	55	0	0
T7	22931	47	0	0
T8	2558	43	0	0
T9	7643	89	0	0
T10	40634	53	0	0
T11	11392	19	0	0
T12	1071	14	0	0
T13	2743	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	224779	0	0
GntImpliesValid_A	395159060	224779	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	224779	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2735552	0	0
ReadyAndValidImplyGrant_A	395159060	224779	0	0
ReqAndReadyImplyGrant_A	395159060	224779	0	0
ReqImpliesValid_A	395159060	540092	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	224779	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2735552	0	0
T1	1782	9	0	0
T2	12218	84	0	0
T3	17219	404	0	0
T7	22931	191	0	0
T8	2558	40	0	0
T9	7643	83	0	0
T10	40634	427	0	0
T11	11392	90	0	0
T12	1071	9	0	0
T13	2743	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	540092	0	0
T1	1782	10	0	0
T2	12218	18	0	0
T3	17219	64	0	0
T7	22931	57	0	0
T8	2558	43	0	0
T9	7643	90	0	0
T10	40634	51	0	0
T11	11392	26	0	0
T12	1071	10	0	0
T13	2743	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	224779	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	50	0	0
T7	22931	30	0	0
T8	2558	41	0	0
T9	7643	86	0	0
T10	40634	51	0	0
T11	11392	14	0	0
T12	1071	9	0	0
T13	2743	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	226390	0	0
GntImpliesValid_A	395159060	226390	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	226390	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2790098	0	0
ReadyAndValidImplyGrant_A	395159060	226390	0	0
ReqAndReadyImplyGrant_A	395159060	226390	0	0
ReqImpliesValid_A	395159060	538933	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	226390	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2790098	0	0
T1	1782	10	0	0
T2	12218	93	0	0
T3	17219	454	0	0
T7	22931	275	0	0
T8	2558	41	0	0
T9	7643	77	0	0
T10	40634	357	0	0
T11	11392	130	0	0
T12	1071	10	0	0
T13	2743	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	538933	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	75	0	0
T7	22931	34	0	0
T8	2558	46	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	23	0	0
T12	1071	9	0	0
T13	2743	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	226390	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	58	0	0
T7	22931	34	0	0
T8	2558	43	0	0
T9	7643	76	0	0
T10	40634	55	0	0
T11	11392	18	0	0
T12	1071	9	0	0
T13	2743	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	219560	0	0
GntImpliesValid_A	395159060	219560	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	219560	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2810895	0	0
ReadyAndValidImplyGrant_A	395159060	219560	0	0
ReqAndReadyImplyGrant_A	395159060	219560	0	0
ReqImpliesValid_A	395159060	561783	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	219560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2810895	0	0
T1	1782	5	0	0
T2	12218	65	0	0
T3	17219	456	0	0
T7	22931	257	0	0
T8	2558	37	0	0
T9	7643	84	0	0
T10	40634	311	0	0
T11	11392	62	0	0
T12	1071	7	0	0
T13	2743	20	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	561783	0	0
T1	1782	4	0	0
T2	12218	15	0	0
T3	17219	77	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	85	0	0
T10	40634	49	0	0
T11	11392	23	0	0
T12	1071	10	0	0
T13	2743	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219560	0	0
T1	1782	4	0	0
T2	12218	11	0	0
T3	17219	56	0	0
T7	22931	35	0	0
T8	2558	36	0	0
T9	7643	84	0	0
T10	40634	49	0	0
T11	11392	9	0	0
T12	1071	8	0	0
T13	2743	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	210120	0	0
GntImpliesValid_A	395159060	210120	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	210120	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2765616	0	0
ReadyAndValidImplyGrant_A	395159060	210120	0	0
ReqAndReadyImplyGrant_A	395159060	210120	0	0
ReqImpliesValid_A	395159060	504919	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	210120	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2765616	0	0
T1	1782	10	0	0
T2	12218	86	0	0
T3	17219	295	0	0
T7	22931	306	0	0
T8	2558	43	0	0
T9	7643	86	0	0
T10	40634	470	0	0
T11	11392	103	0	0
T12	1071	6	0	0
T13	2743	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	504919	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	63	0	0
T7	22931	45	0	0
T8	2558	42	0	0
T9	7643	97	0	0
T10	40634	57	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	210120	0	0
T1	1782	9	0	0
T2	12218	10	0	0
T3	17219	43	0	0
T7	22931	43	0	0
T8	2558	42	0	0
T9	7643	91	0	0
T10	40634	56	0	0
T11	11392	12	0	0
T12	1071	5	0	0
T13	2743	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	219809	0	0
GntImpliesValid_A	395159060	219809	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	219809	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2798153	0	0
ReadyAndValidImplyGrant_A	395159060	219809	0	0
ReqAndReadyImplyGrant_A	395159060	219809	0	0
ReqImpliesValid_A	395159060	553650	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	219809	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2798153	0	0
T1	1782	10	0	0
T2	12218	101	0	0
T3	17219	433	0	0
T7	22931	171	0	0
T8	2558	35	0	0
T9	7643	89	0	0
T10	40634	416	0	0
T11	11392	94	0	0
T12	1071	7	0	0
T13	2743	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	553650	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	65	0	0
T7	22931	46	0	0
T8	2558	42	0	0
T9	7643	90	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	219809	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	58	0	0
T7	22931	32	0	0
T8	2558	38	0	0
T9	7643	89	0	0
T10	40634	56	0	0
T11	11392	14	0	0
T12	1071	6	0	0
T13	2743	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	227170	0	0
GntImpliesValid_A	395159060	227170	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	227170	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2752531	0	0
ReadyAndValidImplyGrant_A	395159060	227170	0	0
ReqAndReadyImplyGrant_A	395159060	227170	0	0
ReqImpliesValid_A	395159060	551198	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	227170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2752531	0	0
T1	1782	9	0	0
T2	12218	98	0	0
T3	17219	433	0	0
T7	22931	245	0	0
T8	2558	37	0	0
T9	7643	84	0	0
T10	40634	465	0	0
T11	11392	73	0	0
T12	1071	12	0	0
T13	2743	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	551198	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	85	0	0
T7	22931	42	0	0
T8	2558	38	0	0
T9	7643	87	0	0
T10	40634	74	0	0
T11	11392	18	0	0
T12	1071	13	0	0
T13	2743	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227170	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	61	0	0
T7	22931	37	0	0
T8	2558	37	0	0
T9	7643	85	0	0
T10	40634	62	0	0
T11	11392	9	0	0
T12	1071	12	0	0
T13	2743	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	225010	0	0
GntImpliesValid_A	395159060	225010	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	225010	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2808636	0	0
ReadyAndValidImplyGrant_A	395159060	225010	0	0
ReqAndReadyImplyGrant_A	395159060	225010	0	0
ReqImpliesValid_A	395159060	571024	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	225010	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2808636	0	0
T1	1782	9	0	0
T2	12218	116	0	0
T3	17219	412	0	0
T7	22931	307	0	0
T8	2558	43	0	0
T9	7643	94	0	0
T10	40634	369	0	0
T11	11392	162	0	0
T12	1071	12	0	0
T13	2743	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	571024	0	0
T1	1782	8	0	0
T2	12218	23	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	44	0	0
T9	7643	99	0	0
T10	40634	56	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	225010	0	0
T1	1782	8	0	0
T2	12218	13	0	0
T3	17219	46	0	0
T7	22931	36	0	0
T8	2558	43	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	21	0	0
T12	1071	11	0	0
T13	2743	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	217619	0	0
GntImpliesValid_A	395159060	217619	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	217619	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2790290	0	0
ReadyAndValidImplyGrant_A	395159060	217619	0	0
ReqAndReadyImplyGrant_A	395159060	217619	0	0
ReqImpliesValid_A	395159060	557526	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	217619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2790290	0	0
T1	1782	10	0	0
T2	12218	99	0	0
T3	17219	389	0	0
T7	22931	284	0	0
T8	2558	44	0	0
T9	7643	89	0	0
T10	40634	536	0	0
T11	11392	134	0	0
T12	1071	12	0	0
T13	2743	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	557526	0	0
T1	1782	9	0	0
T2	12218	25	0	0
T3	17219	66	0	0
T7	22931	47	0	0
T8	2558	49	0	0
T9	7643	94	0	0
T10	40634	86	0	0
T11	11392	20	0	0
T12	1071	11	0	0
T13	2743	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	217619	0	0
T1	1782	9	0	0
T2	12218	12	0	0
T3	17219	51	0	0
T7	22931	35	0	0
T8	2558	46	0	0
T9	7643	91	0	0
T10	40634	72	0	0
T11	11392	15	0	0
T12	1071	11	0	0
T13	2743	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	232131	0	0
GntImpliesValid_A	395159060	232131	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	232131	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2830567	0	0
ReadyAndValidImplyGrant_A	395159060	232131	0	0
ReqAndReadyImplyGrant_A	395159060	232131	0	0
ReqImpliesValid_A	395159060	579494	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	232131	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2830567	0	0
T1	1782	11	0	0
T2	12218	77	0	0
T3	17219	356	0	0
T7	22931	527	0	0
T8	2558	39	0	0
T9	7643	85	0	0
T10	40634	550	0	0
T11	11392	167	0	0
T12	1071	9	0	0
T13	2743	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	579494	0	0
T1	1782	12	0	0
T2	12218	12	0	0
T3	17219	57	0	0
T7	22931	124	0	0
T8	2558	40	0	0
T9	7643	88	0	0
T10	40634	69	0	0
T11	11392	31	0	0
T12	1071	12	0	0
T13	2743	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	232131	0	0
T1	1782	11	0	0
T2	12218	12	0	0
T3	17219	46	0	0
T7	22931	70	0	0
T8	2558	39	0	0
T9	7643	86	0	0
T10	40634	69	0	0
T11	11392	20	0	0
T12	1071	10	0	0
T13	2743	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	227038	0	0
GntImpliesValid_A	395159060	227038	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	227038	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2849636	0	0
ReadyAndValidImplyGrant_A	395159060	227038	0	0
ReqAndReadyImplyGrant_A	395159060	227038	0	0
ReqImpliesValid_A	395159060	545724	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	227038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2849636	0	0
T1	1782	10	0	0
T2	12218	72	0	0
T3	17219	328	0	0
T7	22931	358	0	0
T8	2558	39	0	0
T9	7643	87	0	0
T10	40634	485	0	0
T11	11392	140	0	0
T12	1071	15	0	0
T13	2743	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	545724	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	54	0	0
T7	22931	55	0	0
T8	2558	40	0	0
T9	7643	96	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227038	0	0
T1	1782	9	0	0
T2	12218	8	0	0
T3	17219	48	0	0
T7	22931	44	0	0
T8	2558	39	0	0
T9	7643	91	0	0
T10	40634	55	0	0
T11	11392	12	0	0
T12	1071	14	0	0
T13	2743	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	221015	0	0
GntImpliesValid_A	395159060	221015	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	221015	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2771408	0	0
ReadyAndValidImplyGrant_A	395159060	221015	0	0
ReqAndReadyImplyGrant_A	395159060	221015	0	0
ReqImpliesValid_A	395159060	552265	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	221015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2771408	0	0
T1	1782	8	0	0
T2	12218	81	0	0
T3	17219	320	0	0
T7	22931	357	0	0
T8	2558	32	0	0
T9	7643	99	0	0
T10	40634	345	0	0
T11	11392	137	0	0
T12	1071	9	0	0
T13	2743	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	552265	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	59	0	0
T7	22931	64	0	0
T8	2558	41	0	0
T9	7643	104	0	0
T10	40634	48	0	0
T11	11392	30	0	0
T12	1071	10	0	0
T13	2743	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	221015	0	0
T1	1782	7	0	0
T2	12218	12	0	0
T3	17219	41	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	101	0	0
T10	40634	48	0	0
T11	11392	17	0	0
T12	1071	9	0	0
T13	2743	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	227362	0	0
GntImpliesValid_A	395159060	227362	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	227362	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2739617	0	0
ReadyAndValidImplyGrant_A	395159060	227362	0	0
ReqAndReadyImplyGrant_A	395159060	227362	0	0
ReqImpliesValid_A	395159060	600782	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	227362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2739617	0	0
T1	1782	10	0	0
T2	12218	136	0	0
T3	17219	404	0	0
T7	22931	279	0	0
T8	2558	35	0	0
T9	7643	96	0	0
T10	40634	345	0	0
T11	11392	117	0	0
T12	1071	8	0	0
T13	2743	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	600782	0	0
T1	1782	11	0	0
T2	12218	15	0	0
T3	17219	88	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	107	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	227362	0	0
T1	1782	10	0	0
T2	12218	15	0	0
T3	17219	49	0	0
T7	22931	35	0	0
T8	2558	34	0	0
T9	7643	101	0	0
T10	40634	52	0	0
T11	11392	13	0	0
T12	1071	7	0	0
T13	2743	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	218182	0	0
GntImpliesValid_A	395159060	218182	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	218182	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2752106	0	0
ReadyAndValidImplyGrant_A	395159060	218182	0	0
ReqAndReadyImplyGrant_A	395159060	218182	0	0
ReqImpliesValid_A	395159060	523581	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	218182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2752106	0	0
T1	1782	13	0	0
T2	12218	78	0	0
T3	17219	370	0	0
T7	22931	431	0	0
T8	2558	36	0	0
T9	7643	94	0	0
T10	40634	460	0	0
T11	11392	163	0	0
T12	1071	15	0	0
T13	2743	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	523581	0	0
T1	1782	16	0	0
T2	12218	13	0	0
T3	17219	81	0	0
T7	22931	61	0	0
T8	2558	37	0	0
T9	7643	99	0	0
T10	40634	62	0	0
T11	11392	29	0	0
T12	1071	14	0	0
T13	2743	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	218182	0	0
T1	1782	14	0	0
T2	12218	10	0	0
T3	17219	53	0	0
T7	22931	47	0	0
T8	2558	36	0	0
T9	7643	96	0	0
T10	40634	62	0	0
T11	11392	17	0	0
T12	1071	14	0	0
T13	2743	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	212636	0	0
GntImpliesValid_A	395159060	212636	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	212636	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	2752490	0	0
ReadyAndValidImplyGrant_A	395159060	212636	0	0
ReqAndReadyImplyGrant_A	395159060	212636	0	0
ReqImpliesValid_A	395159060	513048	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	0	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	212636	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2752490	0	0
T1	1782	8	0	0
T2	12218	73	0	0
T3	17219	314	0	0
T7	22931	230	0	0
T8	2558	39	0	0
T9	7643	93	0	0
T10	40634	454	0	0
T11	11392	123	0	0
T12	1071	9	0	0
T13	2743	22	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	513048	0	0
T1	1782	9	0	0
T2	12218	11	0	0
T3	17219	69	0	0
T7	22931	31	0	0
T8	2558	50	0	0
T9	7643	104	0	0
T10	40634	68	0	0
T11	11392	15	0	0
T12	1071	10	0	0
T13	2743	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	212636	0	0
T1	1782	8	0	0
T2	12218	11	0	0
T3	17219	50	0	0
T7	22931	31	0	0
T8	2558	44	0	0
T9	7643	98	0	0
T10	40634	61	0	0
T11	11392	15	0	0
T12	1071	9	0	0
T13	2743	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	883382	0	0
GntImpliesValid_A	395159060	883382	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	883382	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	10419615	0	0
ReadyAndValidImplyGrant_A	395159060	883382	0	0
ReqAndReadyImplyGrant_A	395159060	883382	0	0
ReqImpliesValid_A	395159060	2177219	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	18512	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	883382	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	10419615	0	0
T1	1782	1	0	0
T2	12218	478	0	0
T3	17219	1329	0	0
T7	22931	875	0	0
T8	2558	1	0	0
T9	7643	1	0	0
T10	40634	1778	0	0
T11	11392	343	0	0
T12	1071	1	0	0
T13	2743	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	2177219	0	0
T1	1782	42	0	0
T2	12218	104	0	0
T3	17219	285	0	0
T7	22931	175	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	244	0	0
T11	11392	116	0	0
T12	1071	37	0	0
T13	2743	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	18512	0	900
T7	22931	0	0	1
T8	2558	2	0	1
T9	7643	3	0	1
T10	40634	0	0	1
T11	11392	0	0	1
T12	1071	1	0	1
T13	2743	0	0	1
T14	3764	4	0	1
T15	3502	1	0	1
T17	0	6	0	0
T19	0	11	0	0
T20	0	4	0	0
T21	0	5	0	0
T22	0	17	0	0
T23	33923	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	883382	0	0
T1	1782	42	0	0
T2	12218	69	0	0
T3	17219	186	0	0
T7	22931	143	0	0
T8	2558	147	0	0
T9	7643	390	0	0
T10	40634	239	0	0
T11	11392	55	0	0
T12	1071	37	0	0
T13	2743	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395159060	395031657	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395159060	892754	0	0
GntImpliesValid_A	395159060	892754	0	0
GrantKnown_A	395159060	395031657	0	0
IdxKnown_A	395159060	395031657	0	0
IndexIsCorrect_A	395159060	892754	0	0
LockArbDecision_A	395159060	0	0	0
NoReadyValidNoGrant_A	395159060	330973857	0	0
ReadyAndValidImplyGrant_A	395159060	892754	0	0
ReqAndReadyImplyGrant_A	395159060	892754	0	0
ReqImpliesValid_A	395159060	12337448	0	0
ReqStaysHighUntilGranted0_M	395159060	0	0	0
RoundRobin_A	395159060	33128	0	900
ValidKnown_A	395159060	395031657	0	0
gen_data_port_assertion.DataFlow_A	395159060	892754	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	330973857	0	0
T1	1782	1	0	0
T2	12218	10708	0	0
T3	17219	14195	0	0
T7	22931	19764	0	0
T8	2558	1	0	0
T9	7643	1	0	0
T10	40634	35377	0	0
T11	11392	9935	0	0
T12	1071	1	0	0
T13	2743	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	12337448	0	0
T1	1782	45	0	0
T2	12218	412	0	0
T3	17219	1596	0	0
T7	22931	822	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	1739	0	0
T11	11392	305	0	0
T12	1071	48	0	0
T13	2743	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	33128	0	900
T7	22931	0	0	1
T8	2558	3	0	1
T9	7643	5	0	1
T10	40634	1	0	1
T11	11392	0	0	1
T12	1071	0	0	1
T13	2743	0	0	1
T14	3764	7	0	1
T15	3502	0	0	1
T16	0	2	0	0
T17	0	4	0	0
T18	0	1	0	0
T19	0	21	0	0
T20	0	11	0	0
T21	0	3	0	0
T23	33923	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	395031657	0	0
T1	1782	1723	0	0
T2	12218	12176	0	0
T3	17219	17178	0	0
T7	22931	22876	0	0
T8	2558	2521	0	0
T9	7643	7602	0	0
T10	40634	40608	0	0
T11	11392	11337	0	0
T12	1071	1039	0	0
T13	2743	2688	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395159060	892754	0	0
T1	1782	45	0	0
T2	12218	53	0	0
T3	17219	182	0	0
T7	22931	111	0	0
T8	2558	165	0	0
T9	7643	367	0	0
T10	40634	228	0	0
T11	11392	50	0	0
T12	1071	48	0	0
T13	2743	66	0	0