Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1559175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248076

1

T1

8

T2

27

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613350	1			T1	39		T2	55		T3	38
values[0x0]	580847	1			T1	35		T2	49		T3	43
values[0x1]	613054	1			T1	38		T2	49		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

601928

1

T1

31

T2

61

T3

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28541	1			T1	6		T2	4		T3	3
valid_sources[0x01]	27909	1			T1	1		T2	4		T8	40
valid_sources[0x02]	28242	1			T1	3		T2	3		T3	2
valid_sources[0x03]	28008	1			T1	2		T2	1		T3	1
valid_sources[0x04]	27924	1			T2	2		T8	11		T7	27
valid_sources[0x05]	28070	1			T3	3		T8	43		T7	4
valid_sources[0x06]	28031	1			T1	4		T3	10		T8	59
valid_sources[0x07]	28144	1			T1	2		T2	2		T3	1
valid_sources[0x08]	27673	1			T1	2		T2	5		T8	7
valid_sources[0x09]	29001	1			T1	1		T2	1		T8	57
valid_sources[0x0a]	28271	1			T1	2		T2	3		T3	1
valid_sources[0x0b]	28233	1			T2	6		T3	1		T8	37
valid_sources[0x0c]	27418	1			T2	3		T8	87		T7	127
valid_sources[0x0d]	28170	1			T2	1		T3	3		T8	46
valid_sources[0x0e]	28498	1			T1	3		T2	2		T3	5
valid_sources[0x0f]	27688	1			T2	1		T3	2		T8	41
valid_sources[0x10]	28988	1			T1	2		T3	4		T8	31
valid_sources[0x11]	28355	1			T1	2		T2	1		T3	1
valid_sources[0x12]	27786	1			T1	2		T3	5		T8	32
valid_sources[0x13]	28156	1			T1	3		T2	6		T3	1
valid_sources[0x14]	28172	1			T1	6		T2	4		T3	12
valid_sources[0x15]	28058	1			T2	3		T3	2		T8	42
valid_sources[0x16]	27414	1			T1	2		T2	3		T3	1
valid_sources[0x17]	26411	1			T1	1		T8	24		T7	31
valid_sources[0x18]	28739	1			T2	1		T3	4		T8	49
valid_sources[0x19]	29096	1			T1	1		T2	2		T3	2
valid_sources[0x1a]	28504	1			T1	1		T2	3		T8	59
valid_sources[0x1b]	28061	1			T1	2		T2	1		T3	2
valid_sources[0x1c]	29033	1			T1	1		T3	1		T8	52
valid_sources[0x1d]	28442	1			T1	3		T2	2		T3	1
valid_sources[0x1e]	27337	1			T2	3		T3	3		T8	70
valid_sources[0x1f]	27802	1			T1	2		T2	7		T3	3
valid_sources[0x20]	28079	1			T1	4		T2	3		T8	83

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25956

1

T2

3

T3

1

T8

36

values[0x0]

all_enables

biggest_size

196199

1

T1

8

T2

20

T3

19

values[0x1]

all_enables

biggest_size

25921

1

T2

4

T3

2

T8

39

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1575576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256986

1

T1

14

T2

27

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	626051	1			T1	39		T2	49		T3	48
values[0x0]	578143	1			T1	38		T2	58		T3	59
values[0x1]	628368	1			T1	31		T2	39		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1209368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623194

1

T1

29

T2

54

T3

65

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29402	1			T1	2		T2	3		T3	5
valid_sources[0x01]	28281	1			T3	5		T8	45		T9	1
valid_sources[0x02]	28735	1			T1	5		T2	3		T3	5
valid_sources[0x03]	28572	1			T2	1		T3	2		T8	55
valid_sources[0x04]	28467	1			T1	2		T2	3		T8	50
valid_sources[0x05]	29069	1			T1	12		T2	2		T3	2
valid_sources[0x06]	28513	1			T1	4		T2	3		T3	2
valid_sources[0x07]	28497	1			T1	8		T2	3		T3	2
valid_sources[0x08]	28316	1			T2	2		T3	4		T8	58
valid_sources[0x09]	28739	1			T1	3		T2	5		T3	5
valid_sources[0x0a]	28868	1			T1	5		T2	4		T3	1
valid_sources[0x0b]	28448	1			T1	1		T2	1		T3	3
valid_sources[0x0c]	28711	1			T1	5		T2	1		T3	3
valid_sources[0x0d]	29758	1			T1	3		T2	5		T3	1
valid_sources[0x0e]	29205	1			T1	4		T2	1		T3	4
valid_sources[0x0f]	28550	1			T1	1		T2	1		T8	56
valid_sources[0x10]	27998	1			T3	4		T8	13		T9	7
valid_sources[0x11]	29150	1			T2	4		T3	2		T8	42
valid_sources[0x12]	28145	1			T1	6		T2	3		T3	4
valid_sources[0x13]	28643	1			T1	2		T2	3		T8	86
valid_sources[0x14]	29353	1			T3	2		T8	74		T9	5
valid_sources[0x15]	27976	1			T2	2		T3	2		T8	62
valid_sources[0x16]	28460	1			T1	1		T2	2		T3	2
valid_sources[0x17]	27455	1			T2	1		T3	10		T8	37
valid_sources[0x18]	28341	1			T1	1		T2	1		T3	3
valid_sources[0x19]	28863	1			T1	1		T2	4		T3	3
valid_sources[0x1a]	28990	1			T2	1		T3	2		T8	33
valid_sources[0x1b]	28693	1			T2	4		T3	3		T8	36
valid_sources[0x1c]	28314	1			T1	1		T2	3		T3	1
valid_sources[0x1d]	28759	1			T1	1		T2	2		T3	3
valid_sources[0x1e]	28535	1			T1	1		T2	3		T3	3
valid_sources[0x1f]	28521	1			T2	3		T3	3		T8	37
valid_sources[0x20]	27679	1			T1	1		T2	4		T8	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27036

1

T1

2

T3

1

T8

43

values[0x0]

all_enables

biggest_size

202815

1

T1

8

T2

26

T3

22

values[0x1]

all_enables

biggest_size

27135

1

T1

4

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1572809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249616

1

T1

34

T2

22

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	618197	1			T1	72		T2	44		T3	54
values[0x0]	585296	1			T1	62		T2	40		T3	42
values[0x1]	618932	1			T1	62		T2	53		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607095

1

T1

80

T2

44

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28700	1			T1	12		T2	5		T8	42
valid_sources[0x01]	28665	1			T1	1		T2	4		T8	23
valid_sources[0x02]	28339	1			T1	2		T2	1		T8	45
valid_sources[0x03]	28396	1			T1	2		T3	11		T8	45
valid_sources[0x04]	27987	1			T1	3		T2	2		T3	2
valid_sources[0x05]	28326	1			T1	5		T2	1		T3	1
valid_sources[0x06]	29241	1			T1	6		T2	5		T3	2
valid_sources[0x07]	28309	1			T1	2		T2	6		T3	2
valid_sources[0x08]	28246	1			T1	1		T2	2		T3	2
valid_sources[0x09]	28141	1			T1	7		T2	2		T8	27
valid_sources[0x0a]	28213	1			T1	1		T3	6		T8	44
valid_sources[0x0b]	29042	1			T1	4		T8	34		T9	1
valid_sources[0x0c]	28281	1			T1	4		T3	1		T8	34
valid_sources[0x0d]	28666	1			T1	2		T2	4		T8	50
valid_sources[0x0e]	28886	1			T1	3		T2	1		T3	1
valid_sources[0x0f]	28484	1			T1	11		T2	6		T3	1
valid_sources[0x10]	29522	1			T1	7		T3	2		T8	29
valid_sources[0x11]	29178	1			T1	4		T2	3		T8	57
valid_sources[0x12]	27628	1			T1	2		T2	1		T3	1
valid_sources[0x13]	28452	1			T1	4		T8	53		T9	1
valid_sources[0x14]	28747	1			T1	1		T2	2		T8	49
valid_sources[0x15]	28706	1			T1	3		T8	49		T9	5
valid_sources[0x16]	29114	1			T1	3		T2	3		T8	40
valid_sources[0x17]	28309	1			T2	2		T8	46		T9	3
valid_sources[0x18]	27975	1			T1	3		T2	1		T3	1
valid_sources[0x19]	27936	1			T1	4		T2	2		T3	3
valid_sources[0x1a]	29055	1			T1	6		T2	3		T3	2
valid_sources[0x1b]	28820	1			T1	3		T2	2		T8	59
valid_sources[0x1c]	27225	1			T2	4		T3	9		T8	52
valid_sources[0x1d]	28212	1			T1	1		T2	4		T8	38
valid_sources[0x1e]	29013	1			T1	4		T2	1		T3	1
valid_sources[0x1f]	28836	1			T1	2		T2	7		T3	4
valid_sources[0x20]	27956	1			T1	1		T2	3		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26048

1

T1

1

T2

2

T3

5

values[0x0]

all_enables

biggest_size

197549

1

T1

29

T2

18

T3

21

values[0x1]

all_enables

biggest_size

26019

1

T1

4

T2

2

T3

1