Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1550890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246227

1

T1

22

T2

20

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	610579	1			T1	62		T2	59		T3	54
values[0x0]	577174	1			T1	59		T2	45		T3	47
values[0x1]	609364	1			T1	78		T2	59		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597620

1

T1

59

T2

54

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29170	1			T2	3		T3	2		T10	2
valid_sources[0x01]	29376	1			T3	4		T10	1		T7	4
valid_sources[0x02]	28446	1			T1	5		T3	1		T8	20
valid_sources[0x03]	28342	1			T1	8		T2	3		T3	3
valid_sources[0x04]	29482	1			T3	2		T10	1		T11	4
valid_sources[0x05]	27858	1			T2	2		T3	3		T10	2
valid_sources[0x06]	28521	1			T1	11		T2	1		T10	1
valid_sources[0x07]	28961	1			T2	1		T3	5		T10	1
valid_sources[0x08]	27881	1			T3	5		T10	2		T7	2
valid_sources[0x09]	27624	1			T1	1		T3	4		T10	2
valid_sources[0x0a]	27573	1			T2	1		T3	4		T10	1
valid_sources[0x0b]	28832	1			T1	11		T2	4		T3	1
valid_sources[0x0c]	28414	1			T3	2		T10	1		T11	10
valid_sources[0x0d]	27686	1			T2	1		T3	1		T10	3
valid_sources[0x0e]	28778	1			T1	14		T2	1		T3	4
valid_sources[0x0f]	28232	1			T2	10		T3	1		T10	4
valid_sources[0x10]	28674	1			T2	11		T3	3		T10	2
valid_sources[0x11]	29407	1			T3	5		T10	3		T7	2
valid_sources[0x12]	27319	1			T1	6		T7	2		T8	16
valid_sources[0x13]	27747	1			T2	1		T3	1		T10	2
valid_sources[0x14]	28150	1			T1	10		T2	2		T3	3
valid_sources[0x15]	28635	1			T1	1		T2	1		T3	2
valid_sources[0x16]	28348	1			T1	6		T2	8		T3	4
valid_sources[0x17]	27862	1			T3	2		T10	2		T7	4
valid_sources[0x18]	28047	1			T1	2		T2	2		T3	2
valid_sources[0x19]	28348	1			T1	6		T2	6		T3	4
valid_sources[0x1a]	27313	1			T2	5		T3	2		T10	5
valid_sources[0x1b]	27382	1			T1	5		T2	9		T3	3
valid_sources[0x1c]	27428	1			T1	6		T3	3		T10	2
valid_sources[0x1d]	28625	1			T1	3		T2	1		T11	20
valid_sources[0x1e]	28013	1			T3	5		T10	3		T8	21
valid_sources[0x1f]	27897	1			T1	6		T2	2		T10	1
valid_sources[0x20]	28031	1			T1	4		T3	3		T7	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25902

1

T1

4

T2

5

T3

1

values[0x0]

all_enables

biggest_size

194725

1

T1

17

T2

13

T3

17

values[0x1]

all_enables

biggest_size

25600

1

T1

1

T2

2

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1566523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256139

1

T1

9

T2

13

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	622499	1			T1	41		T2	49		T3	55
values[0x0]	576257	1			T1	37		T2	30		T3	66
values[0x1]	623906	1			T1	39		T2	48		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1203505	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619157

1

T1

35

T2

37

T3

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29142	1			T3	6		T10	1		T11	1
valid_sources[0x01]	28800	1			T10	3		T11	1		T7	3
valid_sources[0x02]	28413	1			T10	4		T11	3		T8	5
valid_sources[0x03]	27665	1			T10	2		T7	2		T8	17
valid_sources[0x04]	29565	1			T1	15		T2	23		T3	5
valid_sources[0x05]	28088	1			T3	4		T10	3		T11	3
valid_sources[0x06]	28800	1			T3	3		T11	7		T7	1
valid_sources[0x07]	28236	1			T3	4		T10	1		T11	3
valid_sources[0x08]	28123	1			T1	2		T10	3		T11	3
valid_sources[0x09]	28529	1			T3	3		T10	3		T11	1
valid_sources[0x0a]	27699	1			T2	13		T3	5		T10	4
valid_sources[0x0b]	28219	1			T1	1		T3	1		T10	7
valid_sources[0x0c]	28778	1			T3	1		T10	1		T11	2
valid_sources[0x0d]	27679	1			T2	6		T3	1		T10	3
valid_sources[0x0e]	28832	1			T2	1		T3	7		T10	1
valid_sources[0x0f]	28466	1			T10	1		T11	2		T7	1
valid_sources[0x10]	28356	1			T10	2		T11	3		T7	2
valid_sources[0x11]	27944	1			T3	3		T11	1		T8	21
valid_sources[0x12]	28630	1			T1	23		T3	2		T10	2
valid_sources[0x13]	27965	1			T3	2		T10	2		T11	4
valid_sources[0x14]	28583	1			T1	2		T2	3		T10	1
valid_sources[0x15]	29027	1			T3	5		T11	3		T7	1
valid_sources[0x16]	27983	1			T2	17		T3	6		T10	1
valid_sources[0x17]	27707	1			T7	2		T12	1		T8	7
valid_sources[0x18]	27991	1			T3	4		T10	2		T11	2
valid_sources[0x19]	28343	1			T3	5		T11	2		T7	3
valid_sources[0x1a]	28131	1			T1	5		T11	1		T12	6
valid_sources[0x1b]	28522	1			T2	13		T3	2		T10	7
valid_sources[0x1c]	28594	1			T10	1		T8	4		T9	16
valid_sources[0x1d]	28727	1			T3	6		T11	3		T7	6
valid_sources[0x1e]	28681	1			T1	3		T11	1		T8	9
valid_sources[0x1f]	28315	1			T3	5		T10	2		T11	1
valid_sources[0x20]	29216	1			T1	12		T3	1		T10	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26722

1

T2

1

T3

2

T11

1

values[0x0]

all_enables

biggest_size

202318

1

T1

8

T2

10

T3

20

values[0x1]

all_enables

biggest_size

27099

1

T1

1

T2

2

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1563158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248594

1

T1

27

T2

28

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613960	1			T1	66		T2	62		T3	65
values[0x0]	583210	1			T1	60		T2	45		T3	62
values[0x1]	614582	1			T1	71		T2	62		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1208781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

602971

1

T1

75

T2

59

T3

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27678	1			T1	7		T2	2		T10	5
valid_sources[0x01]	28319	1			T1	2		T2	4		T3	10
valid_sources[0x02]	28471	1			T1	3		T2	1		T10	2
valid_sources[0x03]	29628	1			T1	4		T10	1		T12	40
valid_sources[0x04]	29174	1			T1	4		T2	5		T10	1
valid_sources[0x05]	28330	1			T1	3		T10	1		T11	5
valid_sources[0x06]	27923	1			T1	1		T2	4		T11	2
valid_sources[0x07]	28181	1			T1	3		T2	2		T10	2
valid_sources[0x08]	28530	1			T1	1		T3	13		T10	1
valid_sources[0x09]	28618	1			T1	1		T2	1		T10	1
valid_sources[0x0a]	27935	1			T1	3		T2	4		T10	5
valid_sources[0x0b]	27994	1			T1	2		T10	2		T11	3
valid_sources[0x0c]	27775	1			T1	4		T3	2		T10	2
valid_sources[0x0d]	27806	1			T1	1		T2	5		T10	5
valid_sources[0x0e]	28344	1			T10	2		T11	3		T7	2
valid_sources[0x0f]	28019	1			T1	2		T2	4		T10	3
valid_sources[0x10]	28436	1			T1	3		T10	6		T11	3
valid_sources[0x11]	28070	1			T1	1		T2	3		T10	1
valid_sources[0x12]	28222	1			T1	8		T2	5		T10	4
valid_sources[0x13]	28489	1			T1	3		T2	1		T3	49
valid_sources[0x14]	28466	1			T1	2		T2	7		T3	6
valid_sources[0x15]	28028	1			T1	3		T2	5		T3	12
valid_sources[0x16]	28560	1			T1	4		T10	3		T11	2
valid_sources[0x17]	27587	1			T2	4		T10	1		T11	4
valid_sources[0x18]	28113	1			T1	5		T10	5		T11	6
valid_sources[0x19]	27977	1			T1	3		T2	4		T10	2
valid_sources[0x1a]	28136	1			T1	5		T2	1		T10	2
valid_sources[0x1b]	27856	1			T1	5		T3	40		T10	3
valid_sources[0x1c]	28534	1			T1	2		T2	5		T10	4
valid_sources[0x1d]	28364	1			T1	3		T2	3		T3	14
valid_sources[0x1e]	28624	1			T1	5		T2	5		T10	3
valid_sources[0x1f]	28850	1			T1	5		T2	5		T10	4
valid_sources[0x20]	27730	1			T1	1		T10	1		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25977

1

T1

1

T2

7

T3

4

values[0x0]

all_enables

biggest_size

196314

1

T1

24

T2

17

T3

17

values[0x1]

all_enables

biggest_size

26303

1

T1

2

T2

4

T3

2