Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7719694	0	0
GntImpliesValid_A	2147483647	7719694	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7719694	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	429610411	0	0
ReadyAndValidImplyGrant_A	2147483647	7719694	0	0
ReqAndReadyImplyGrant_A	2147483647	7719694	0	0
ReqImpliesValid_A	2147483647	33930457	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48316	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7719694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52728	52248	0	0
T2	67992	66144	0	0
T3	47616	47400	0	0
T7	271248	270144	0	0
T8	506448	504744	0	0
T9	579912	579168	0	0
T10	38208	37872	0	0
T11	48264	47184	0	0
T12	58872	57648	0	0
T13	647856	646584	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52728	52248	0	0
T2	67992	66144	0	0
T3	47616	47400	0	0
T7	271248	270144	0	0
T8	506448	504744	0	0
T9	579912	579168	0	0
T10	38208	37872	0	0
T11	48264	47184	0	0
T12	58872	57648	0	0
T13	647856	646584	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52728	52248	0	0
T2	67992	66144	0	0
T3	47616	47400	0	0
T7	271248	270144	0	0
T8	506448	504744	0	0
T9	579912	579168	0	0
T10	38208	37872	0	0
T11	48264	47184	0	0
T12	58872	57648	0	0
T13	647856	646584	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	429610411	0	0
T1	52728	718	0	0
T2	67992	966	0	0
T3	47616	560	0	0
T4	0	3838	0	0
T7	271248	13025	0	0
T8	506448	25131	0	0
T9	579912	38869	0	0
T10	38208	456	0	0
T11	48264	531	0	0
T12	58872	659	0	0
T13	647856	34232	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33930457	0	0
T1	52728	570	0	0
T2	67992	550	0	0
T3	47616	585	0	0
T4	0	2968	0	0
T7	271248	897	0	0
T8	506448	14351	0	0
T9	579912	7032	0	0
T10	38208	449	0	0
T11	48264	513	0	0
T12	58872	598	0	0
T13	647856	2847	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48316	0	21600
T4	18754	13	0	2
T14	4032	6	0	2
T15	13684	19	0	2
T16	18442	2	0	2
T17	30160	20	0	2
T18	7922	12	0	2
T19	19390	441	0	2
T20	18364	23	0	2
T21	21540	28	0	2
T22	0	11	0	0
T23	0	6	0	0
T24	422926	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	52728	52248	0	0
T2	67992	66144	0	0
T3	47616	47400	0	0
T7	271248	270144	0	0
T8	506448	504744	0	0
T9	579912	579168	0	0
T10	38208	37872	0	0
T11	48264	47184	0	0
T12	58872	57648	0	0
T13	647856	646584	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7719694	0	0
T1	52728	513	0	0
T2	67992	459	0	0
T3	47616	532	0	0
T4	0	2081	0	0
T7	271248	418	0	0
T8	506448	2154	0	0
T9	579912	3000	0	0
T10	38208	392	0	0
T11	48264	464	0	0
T12	58872	492	0	0
T13	647856	1535	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	868408	0	0
GntImpliesValid_A	389103870	868408	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	868408	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	11959439	0	0
ReadyAndValidImplyGrant_A	389103870	868408	0	0
ReqAndReadyImplyGrant_A	389103870	868408	0	0
ReqImpliesValid_A	389103870	2502373	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	868408	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	11959439	0	0
T1	2197	38	0	0
T2	2833	40	0	0
T3	1984	49	0	0
T7	11302	309	0	0
T8	21102	1112	0	0
T9	24163	2256	0	0
T10	1592	36	0	0
T11	2011	44	0	0
T12	2453	46	0	0
T13	26994	1279	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2502373	0	0
T1	2197	61	0	0
T2	2833	61	0	0
T3	1984	78	0	0
T7	11302	70	0	0
T8	21102	256	0	0
T9	24163	630	0	0
T10	1592	49	0	0
T11	2011	65	0	0
T12	2453	79	0	0
T13	26994	198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868408	0	0
T1	2197	49	0	0
T2	2833	50	0	0
T3	1984	63	0	0
T7	11302	44	0	0
T8	21102	159	0	0
T9	24163	324	0	0
T10	1592	42	0	0
T11	2011	54	0	0
T12	2453	62	0	0
T13	26994	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	868425	0	0
GntImpliesValid_A	389103870	868425	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	868425	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	11877092	0	0
ReadyAndValidImplyGrant_A	389103870	868425	0	0
ReqAndReadyImplyGrant_A	389103870	868425	0	0
ReqImpliesValid_A	389103870	2444712	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	868425	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	11877092	0	0
T1	2197	32	0	0
T2	2833	34	0	0
T3	1984	43	0	0
T7	11302	342	0	0
T8	21102	1015	0	0
T9	24163	2229	0	0
T10	1592	32	0	0
T11	2011	37	0	0
T12	2453	39	0	0
T13	26994	1256	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2444712	0	0
T1	2197	37	0	0
T2	2833	53	0	0
T3	1984	64	0	0
T7	11302	81	0	0
T8	21102	225	0	0
T9	24163	592	0	0
T10	1592	45	0	0
T11	2011	66	0	0
T12	2453	54	0	0
T13	26994	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	868425	0	0
T1	2197	34	0	0
T2	2833	43	0	0
T3	1984	53	0	0
T7	11302	53	0	0
T8	21102	168	0	0
T9	24163	330	0	0
T10	1592	38	0	0
T11	2011	51	0	0
T12	2453	46	0	0
T13	26994	170	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T9 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	203415	0	0
GntImpliesValid_A	389103870	203415	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	203415	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2984691	0	0
ReadyAndValidImplyGrant_A	389103870	203415	0	0
ReqAndReadyImplyGrant_A	389103870	203415	0	0
ReqImpliesValid_A	389103870	518872	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	203415	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2984691	0	0
T1	2197	23	0	0
T2	2833	11	0	0
T3	1984	17	0	0
T7	11302	86	0	0
T8	21102	1	0	0
T9	24163	672	0	0
T10	1592	13	0	0
T11	2011	12	0	0
T12	2453	16	0	0
T13	26994	320	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	518872	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	139	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	125	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	203415	0	0
T1	2197	22	0	0
T2	2833	10	0	0
T3	1984	16	0	0
T4	0	129	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	88	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	210367	0	0
GntImpliesValid_A	389103870	210367	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	210367	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2973805	0	0
ReadyAndValidImplyGrant_A	389103870	210367	0	0
ReqAndReadyImplyGrant_A	389103870	210367	0	0
ReqImpliesValid_A	389103870	538810	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	210367	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2973805	0	0
T1	2197	20	0	0
T2	2833	12	0	0
T3	1984	14	0	0
T7	11302	97	0	0
T8	21102	1	0	0
T9	24163	617	0	0
T10	1592	8	0	0
T11	2011	11	0	0
T12	2453	15	0	0
T13	26994	362	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	538810	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	15	0	0
T4	0	121	0	0
T7	11302	14	0	0
T8	21102	0	0	0
T9	24163	118	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	16	0	0
T13	26994	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210367	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	14	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	86	0	0
T10	1592	7	0	0
T11	2011	10	0	0
T12	2453	15	0	0
T13	26994	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	217037	0	0
GntImpliesValid_A	389103870	217037	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	217037	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	4787981	0	0
ReadyAndValidImplyGrant_A	389103870	217037	0	0
ReqAndReadyImplyGrant_A	389103870	217037	0	0
ReqImpliesValid_A	389103870	1293871	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	217037	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	4787981	0	0
T1	2197	83	0	0
T2	2833	86	0	0
T3	1984	61	0	0
T4	0	1875	0	0
T7	11302	238	0	0
T8	21102	0	0	0
T9	24163	566	0	0
T10	1592	98	0	0
T11	2011	70	0	0
T12	2453	87	0	0
T13	26994	980	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	1293871	0	0
T1	2197	27	0	0
T2	2833	20	0	0
T3	1984	20	0	0
T4	0	627	0	0
T7	11302	66	0	0
T8	21102	0	0	0
T9	24163	135	0	0
T10	1592	42	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217037	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	18	0	0
T4	0	131	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	217052	0	0
GntImpliesValid_A	389103870	217052	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	217052	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	4864466	0	0
ReadyAndValidImplyGrant_A	389103870	217052	0	0
ReqAndReadyImplyGrant_A	389103870	217052	0	0
ReqImpliesValid_A	389103870	1170733	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	217052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	4864466	0	0
T1	2197	78	0	0
T2	2833	394	0	0
T3	1984	60	0	0
T4	0	986	0	0
T7	11302	149	0	0
T8	21102	0	0	0
T9	24163	562	0	0
T10	1592	29	0	0
T11	2011	44	0	0
T12	2453	35	0	0
T13	26994	366	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	1170733	0	0
T1	2197	30	0	0
T2	2833	33	0	0
T3	1984	22	0	0
T4	0	212	0	0
T7	11302	20	0	0
T8	21102	0	0	0
T9	24163	108	0	0
T10	1592	12	0	0
T11	2011	23	0	0
T12	2453	23	0	0
T13	26994	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	217052	0	0
T1	2197	20	0	0
T2	2833	17	0	0
T3	1984	15	0	0
T4	0	98	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	80	0	0
T10	1592	9	0	0
T11	2011	9	0	0
T12	2453	7	0	0
T13	26994	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	210905	0	0
GntImpliesValid_A	389103870	210905	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	210905	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	5446938	0	0
ReadyAndValidImplyGrant_A	389103870	210905	0	0
ReqAndReadyImplyGrant_A	389103870	210905	0	0
ReqImpliesValid_A	389103870	1198265	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	210905	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	5446938	0	0
T1	2197	149	0	0
T2	2833	121	0	0
T3	1984	77	0	0
T7	11302	196	0	0
T8	21102	1633	0	0
T9	24163	685	0	0
T10	1592	34	0	0
T11	2011	75	0	0
T12	2453	83	0	0
T13	26994	409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	1198265	0	0
T1	2197	29	0	0
T2	2833	44	0	0
T3	1984	25	0	0
T7	11302	40	0	0
T8	21102	5437	0	0
T9	24163	105	0	0
T10	1592	17	0	0
T11	2011	19	0	0
T12	2453	42	0	0
T13	26994	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	210905	0	0
T1	2197	19	0	0
T2	2833	11	0	0
T3	1984	22	0	0
T7	11302	16	0	0
T8	21102	467	0	0
T9	24163	86	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	208331	0	0
GntImpliesValid_A	389103870	208331	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	208331	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	5391388	0	0
ReadyAndValidImplyGrant_A	389103870	208331	0	0
ReqAndReadyImplyGrant_A	389103870	208331	0	0
ReqImpliesValid_A	389103870	1101648	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	208331	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	5391388	0	0
T1	2197	59	0	0
T2	2833	54	0	0
T3	1984	43	0	0
T4	0	977	0	0
T7	11302	340	0	0
T8	21102	0	0	0
T9	24163	1153	0	0
T10	1592	32	0	0
T11	2011	32	0	0
T12	2453	126	0	0
T13	26994	286	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	1101648	0	0
T1	2197	21	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	307	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	186	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	43	0	0
T13	26994	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208331	0	0
T1	2197	14	0	0
T2	2833	8	0	0
T3	1984	12	0	0
T4	0	133	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	89	0	0
T10	1592	9	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	212213	0	0
GntImpliesValid_A	389103870	212213	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	212213	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2927119	0	0
ReadyAndValidImplyGrant_A	389103870	212213	0	0
ReqAndReadyImplyGrant_A	389103870	212213	0	0
ReqImpliesValid_A	389103870	546431	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	212213	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2927119	0	0
T1	2197	10	0	0
T2	2833	18	0	0
T3	1984	17	0	0
T7	11302	76	0	0
T8	21102	1	0	0
T9	24163	594	0	0
T10	1592	14	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	346	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	546431	0	0
T1	2197	9	0	0
T2	2833	19	0	0
T3	1984	16	0	0
T4	0	125	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	122	0	0
T10	1592	13	0	0
T11	2011	14	0	0
T12	2453	19	0	0
T13	26994	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212213	0	0
T1	2197	9	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	84	0	0
T10	1592	13	0	0
T11	2011	13	0	0
T12	2453	18	0	0
T13	26994	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	207465	0	0
GntImpliesValid_A	389103870	207465	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	207465	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2903922	0	0
ReadyAndValidImplyGrant_A	389103870	207465	0	0
ReqAndReadyImplyGrant_A	389103870	207465	0	0
ReqImpliesValid_A	389103870	526682	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	207465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2903922	0	0
T1	2197	18	0	0
T2	2833	15	0	0
T3	1984	17	0	0
T7	11302	62	0	0
T8	21102	1	0	0
T9	24163	719	0	0
T10	1592	19	0	0
T11	2011	14	0	0
T12	2453	11	0	0
T13	26994	263	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	526682	0	0
T1	2197	17	0	0
T2	2833	18	0	0
T3	1984	16	0	0
T4	0	134	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	128	0	0
T10	1592	22	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207465	0	0
T1	2197	17	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	124	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	20	0	0
T11	2011	13	0	0
T12	2453	10	0	0
T13	26994	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	216081	0	0
GntImpliesValid_A	389103870	216081	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	216081	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2973789	0	0
ReadyAndValidImplyGrant_A	389103870	216081	0	0
ReqAndReadyImplyGrant_A	389103870	216081	0	0
ReqImpliesValid_A	389103870	549714	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	216081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2973789	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T7	11302	105	0	0
T8	21102	1	0	0
T9	24163	452	0	0
T10	1592	8	0	0
T11	2011	21	0	0
T12	2453	15	0	0
T13	26994	356	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	549714	0	0
T1	2197	13	0	0
T2	2833	15	0	0
T3	1984	13	0	0
T4	0	122	0	0
T7	11302	14	0	0
T8	21102	0	0	0
T9	24163	64	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	216081	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	12	0	0
T4	0	118	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	58	0	0
T10	1592	7	0	0
T11	2011	20	0	0
T12	2453	14	0	0
T13	26994	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T10 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	207200	0	0
GntImpliesValid_A	389103870	207200	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	207200	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2962205	0	0
ReadyAndValidImplyGrant_A	389103870	207200	0	0
ReqAndReadyImplyGrant_A	389103870	207200	0	0
ReqImpliesValid_A	389103870	564003	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	207200	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2962205	0	0
T1	2197	15	0	0
T2	2833	13	0	0
T3	1984	7	0	0
T7	11302	73	0	0
T8	21102	1	0	0
T9	24163	604	0	0
T10	1592	14	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	300	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	564003	0	0
T1	2197	18	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	135	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	95	0	0
T10	1592	15	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	207200	0	0
T1	2197	16	0	0
T2	2833	12	0	0
T3	1984	6	0	0
T4	0	128	0	0
T7	11302	8	0	0
T8	21102	0	0	0
T9	24163	77	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	12	0	0
T13	26994	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	219334	0	0
GntImpliesValid_A	389103870	219334	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	219334	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2937226	0	0
ReadyAndValidImplyGrant_A	389103870	219334	0	0
ReqAndReadyImplyGrant_A	389103870	219334	0	0
ReqImpliesValid_A	389103870	594427	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	219334	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2937226	0	0
T1	2197	20	0	0
T2	2833	14	0	0
T3	1984	16	0	0
T7	11302	54	0	0
T8	21102	1220	0	0
T9	24163	696	0	0
T10	1592	12	0	0
T11	2011	14	0	0
T12	2453	14	0	0
T13	26994	356	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	594427	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	19	0	0
T7	11302	9	0	0
T8	21102	2035	0	0
T9	24163	112	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219334	0	0
T1	2197	19	0	0
T2	2833	13	0	0
T3	1984	17	0	0
T7	11302	9	0	0
T8	21102	507	0	0
T9	24163	89	0	0
T10	1592	11	0	0
T11	2011	13	0	0
T12	2453	13	0	0
T13	26994	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	218518	0	0
GntImpliesValid_A	389103870	218518	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	218518	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2903865	0	0
ReadyAndValidImplyGrant_A	389103870	218518	0	0
ReqAndReadyImplyGrant_A	389103870	218518	0	0
ReqImpliesValid_A	389103870	564112	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	218518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2903865	0	0
T1	2197	17	0	0
T2	2833	20	0	0
T3	1984	17	0	0
T7	11302	62	0	0
T8	21102	1302	0	0
T9	24163	602	0	0
T10	1592	14	0	0
T11	2011	12	0	0
T12	2453	14	0	0
T13	26994	368	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	564112	0	0
T1	2197	20	0	0
T2	2833	19	0	0
T3	1984	18	0	0
T7	11302	8	0	0
T8	21102	4717	0	0
T9	24163	132	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218518	0	0
T1	2197	18	0	0
T2	2833	19	0	0
T3	1984	17	0	0
T7	11302	8	0	0
T8	21102	529	0	0
T9	24163	82	0	0
T10	1592	13	0	0
T11	2011	11	0	0
T12	2453	13	0	0
T13	26994	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	212619	0	0
GntImpliesValid_A	389103870	212619	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	212619	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2928926	0	0
ReadyAndValidImplyGrant_A	389103870	212619	0	0
ReqAndReadyImplyGrant_A	389103870	212619	0	0
ReqImpliesValid_A	389103870	540604	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	212619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2928926	0	0
T1	2197	19	0	0
T2	2833	17	0	0
T3	1984	8	0	0
T7	11302	51	0	0
T8	21102	1	0	0
T9	24163	485	0	0
T10	1592	14	0	0
T11	2011	21	0	0
T12	2453	17	0	0
T13	26994	331	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	540604	0	0
T1	2197	20	0	0
T2	2833	16	0	0
T3	1984	9	0	0
T4	0	129	0	0
T7	11302	28	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	15	0	0
T11	2011	20	0	0
T12	2453	18	0	0
T13	26994	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	212619	0	0
T1	2197	19	0	0
T2	2833	16	0	0
T3	1984	8	0	0
T4	0	122	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	72	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	17	0	0
T13	26994	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T9 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	221270	0	0
GntImpliesValid_A	389103870	221270	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	221270	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	3001458	0	0
ReadyAndValidImplyGrant_A	389103870	221270	0	0
ReqAndReadyImplyGrant_A	389103870	221270	0	0
ReqImpliesValid_A	389103870	586536	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	221270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	3001458	0	0
T1	2197	16	0	0
T2	2833	10	0	0
T3	1984	10	0	0
T7	11302	51	0	0
T8	21102	1	0	0
T9	24163	629	0	0
T10	1592	13	0	0
T11	2011	9	0	0
T12	2453	16	0	0
T13	26994	330	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	586536	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	109	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	137	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	221270	0	0
T1	2197	15	0	0
T2	2833	9	0	0
T3	1984	9	0	0
T4	0	105	0	0
T7	11302	10	0	0
T8	21102	0	0	0
T9	24163	85	0	0
T10	1592	12	0	0
T11	2011	8	0	0
T12	2453	15	0	0
T13	26994	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	219692	0	0
GntImpliesValid_A	389103870	219692	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	219692	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	3066797	0	0
ReadyAndValidImplyGrant_A	389103870	219692	0	0
ReqAndReadyImplyGrant_A	389103870	219692	0	0
ReqImpliesValid_A	389103870	547725	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	219692	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	3066797	0	0
T1	2197	24	0	0
T2	2833	20	0	0
T3	1984	10	0	0
T7	11302	115	0	0
T8	21102	1	0	0
T9	24163	678	0	0
T10	1592	13	0	0
T11	2011	15	0	0
T12	2453	15	0	0
T13	26994	364	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	547725	0	0
T1	2197	29	0	0
T2	2833	23	0	0
T3	1984	9	0	0
T4	0	154	0	0
T7	11302	36	0	0
T8	21102	0	0	0
T9	24163	135	0	0
T10	1592	16	0	0
T11	2011	14	0	0
T12	2453	16	0	0
T13	26994	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	219692	0	0
T1	2197	26	0	0
T2	2833	21	0	0
T3	1984	9	0	0
T4	0	142	0	0
T7	11302	15	0	0
T8	21102	0	0	0
T9	24163	93	0	0
T10	1592	14	0	0
T11	2011	14	0	0
T12	2453	15	0	0
T13	26994	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	206659	0	0
GntImpliesValid_A	389103870	206659	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	206659	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2925682	0	0
ReadyAndValidImplyGrant_A	389103870	206659	0	0
ReqAndReadyImplyGrant_A	389103870	206659	0	0
ReqImpliesValid_A	389103870	529448	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	206659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2925682	0	0
T1	2197	19	0	0
T2	2833	17	0	0
T3	1984	16	0	0
T7	11302	113	0	0
T8	21102	1	0	0
T9	24163	480	0	0
T10	1592	8	0	0
T11	2011	8	0	0
T12	2453	18	0	0
T13	26994	344	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	529448	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	126	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	206659	0	0
T1	2197	18	0	0
T2	2833	16	0	0
T3	1984	16	0	0
T4	0	116	0	0
T7	11302	12	0	0
T8	21102	0	0	0
T9	24163	69	0	0
T10	1592	7	0	0
T11	2011	7	0	0
T12	2453	17	0	0
T13	26994	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T12 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T12,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T12,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	218656	0	0
GntImpliesValid_A	389103870	218656	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	218656	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	3055537	0	0
ReadyAndValidImplyGrant_A	389103870	218656	0	0
ReqAndReadyImplyGrant_A	389103870	218656	0	0
ReqImpliesValid_A	389103870	585125	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	218656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	3055537	0	0
T1	2197	21	0	0
T2	2833	10	0	0
T3	1984	17	0	0
T7	11302	113	0	0
T8	21102	1	0	0
T9	24163	682	0	0
T10	1592	7	0	0
T11	2011	18	0	0
T12	2453	13	0	0
T13	26994	269	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	585125	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	18	0	0
T4	0	162	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	156	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	14	0	0
T13	26994	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	218656	0	0
T1	2197	20	0	0
T2	2833	9	0	0
T3	1984	17	0	0
T4	0	152	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	90	0	0
T10	1592	6	0	0
T11	2011	17	0	0
T12	2453	13	0	0
T13	26994	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	208377	0	0
GntImpliesValid_A	389103870	208377	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	208377	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2947478	0	0
ReadyAndValidImplyGrant_A	389103870	208377	0	0
ReqAndReadyImplyGrant_A	389103870	208377	0	0
ReqImpliesValid_A	389103870	511941	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	208377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2947478	0	0
T1	2197	15	0	0
T2	2833	13	0	0
T3	1984	21	0	0
T7	11302	128	0	0
T8	21102	1	0	0
T9	24163	498	0	0
T10	1592	14	0	0
T11	2011	20	0	0
T12	2453	18	0	0
T13	26994	280	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	511941	0	0
T1	2197	14	0	0
T2	2833	16	0	0
T3	1984	24	0	0
T4	0	123	0	0
T7	11302	32	0	0
T8	21102	0	0	0
T9	24163	81	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	23	0	0
T13	26994	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208377	0	0
T1	2197	14	0	0
T2	2833	14	0	0
T3	1984	22	0	0
T4	0	115	0	0
T7	11302	19	0	0
T8	21102	0	0	0
T9	24163	73	0	0
T10	1592	13	0	0
T11	2011	19	0	0
T12	2453	20	0	0
T13	26994	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	208550	0	0
GntImpliesValid_A	389103870	208550	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	208550	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2933279	0	0
ReadyAndValidImplyGrant_A	389103870	208550	0	0
ReqAndReadyImplyGrant_A	389103870	208550	0	0
ReqImpliesValid_A	389103870	545163	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	208550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2933279	0	0
T1	2197	12	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T7	11302	77	0	0
T8	21102	1	0	0
T9	24163	743	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	427	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	545163	0	0
T1	2197	11	0	0
T2	2833	17	0	0
T3	1984	18	0	0
T4	0	122	0	0
T7	11302	13	0	0
T8	21102	0	0	0
T9	24163	113	0	0
T10	1592	12	0	0
T11	2011	15	0	0
T12	2453	18	0	0
T13	26994	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	208550	0	0
T1	2197	11	0	0
T2	2833	16	0	0
T3	1984	17	0	0
T4	0	115	0	0
T7	11302	11	0	0
T8	21102	0	0	0
T9	24163	96	0	0
T10	1592	11	0	0
T11	2011	14	0	0
T12	2453	17	0	0
T13	26994	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T10 T9 T4 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T9,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T9,T4
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	215591	0	0
GntImpliesValid_A	389103870	215591	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	215591	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	2996227	0	0
ReadyAndValidImplyGrant_A	389103870	215591	0	0
ReqAndReadyImplyGrant_A	389103870	215591	0	0
ReqImpliesValid_A	389103870	569666	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	0	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	215591	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2996227	0	0
T1	2197	14	0	0
T2	2833	15	0	0
T3	1984	9	0	0
T7	11302	57	0	0
T8	21102	1	0	0
T9	24163	660	0	0
T10	1592	11	0	0
T11	2011	12	0	0
T12	2453	11	0	0
T13	26994	301	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	569666	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	121	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	162	0	0
T10	1592	12	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	215591	0	0
T1	2197	13	0	0
T2	2833	14	0	0
T3	1984	8	0	0
T4	0	115	0	0
T7	11302	9	0	0
T8	21102	0	0	0
T9	24163	91	0	0
T10	1592	11	0	0
T11	2011	11	0	0
T12	2453	10	0	0
T13	26994	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	861343	0	0
GntImpliesValid_A	389103870	861343	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	861343	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	11391364	0	0
ReadyAndValidImplyGrant_A	389103870	861343	0	0
ReqAndReadyImplyGrant_A	389103870	861343	0	0
ReqImpliesValid_A	389103870	2269317	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	16488	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	861343	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	11391364	0	0
T1	2197	1	0	0
T2	2833	1	0	0
T3	1984	1	0	0
T7	11302	253	0	0
T8	21102	994	0	0
T9	24163	2068	0	0
T10	1592	1	0	0
T11	2011	1	0	0
T12	2453	1	0	0
T13	26994	1047	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	2269317	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	45	0	0
T8	21102	203	0	0
T9	24163	679	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	225	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	16488	0	900
T4	9377	10	0	1
T14	2016	2	0	1
T15	6842	11	0	1
T16	9221	1	0	1
T17	15080	12	0	1
T18	3961	6	0	1
T19	9695	0	0	1
T20	9182	12	0	1
T21	10770	16	0	1
T22	0	4	0	0
T23	0	6	0	0
T24	211463	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	861343	0	0
T1	2197	51	0	0
T2	2833	35	0	0
T3	1984	66	0	0
T7	11302	41	0	0
T8	21102	154	0	0
T9	24163	333	0	0
T10	1592	48	0	0
T11	2011	56	0	0
T12	2453	44	0	0
T13	26994	159	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389103870	388964206	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389103870	862186	0	0
GntImpliesValid_A	389103870	862186	0	0
GrantKnown_A	389103870	388964206	0	0
IdxKnown_A	389103870	388964206	0	0
IndexIsCorrect_A	389103870	862186	0	0
LockArbDecision_A	389103870	0	0	0
NoReadyValidNoGrant_A	389103870	326469737	0	0
ReadyAndValidImplyGrant_A	389103870	862186	0	0
ReqAndReadyImplyGrant_A	389103870	862186	0	0
ReqImpliesValid_A	389103870	13130279	0	0
ReqStaysHighUntilGranted0_M	389103870	0	0	0
RoundRobin_A	389103870	31828	0	900
ValidKnown_A	389103870	388964206	0	0
gen_data_port_assertion.DataFlow_A	389103870	862186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	326469737	0	0
T1	2197	1	0	0
T2	2833	1	0	0
T3	1984	1	0	0
T7	11302	9878	0	0
T8	21102	17841	0	0
T9	24163	19539	0	0
T10	1592	1	0	0
T11	2011	1	0	0
T12	2453	1	0	0
T13	26994	23292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	13130279	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	321	0	0
T8	21102	1478	0	0
T9	24163	2730	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	1358	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	31828	0	900
T4	9377	3	0	1
T14	2016	4	0	1
T15	6842	8	0	1
T16	9221	1	0	1
T17	15080	8	0	1
T18	3961	6	0	1
T19	9695	441	0	1
T20	9182	11	0	1
T21	10770	12	0	1
T22	0	7	0	0
T24	211463	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	388964206	0	0
T1	2197	2177	0	0
T2	2833	2756	0	0
T3	1984	1975	0	0
T7	11302	11256	0	0
T8	21102	21031	0	0
T9	24163	24132	0	0
T10	1592	1578	0	0
T11	2011	1966	0	0
T12	2453	2402	0	0
T13	26994	26941	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389103870	862186	0	0
T1	2197	37	0	0
T2	2833	51	0	0
T3	1984	63	0	0
T7	11302	48	0	0
T8	21102	170	0	0
T9	24163	345	0	0
T10	1592	34	0	0
T11	2011	48	0	0
T12	2453	59	0	0
T13	26994	180	0	0