Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1642822	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261745

1

T1

17

T2

22

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	644544	1			T1	42		T2	49		T3	49
values[0x0]	614558	1			T1	44		T2	51		T3	64
values[0x1]	645465	1			T1	48		T2	43		T3	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1269539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

635028

1

T1

36

T2

50

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30404	1			T1	5		T3	6		T7	7
valid_sources[0x01]	30197	1			T2	18		T3	6		T7	2
valid_sources[0x02]	29110	1			T2	25		T3	8		T9	2
valid_sources[0x03]	29386	1			T3	10		T9	1		T7	6
valid_sources[0x04]	29822	1			T3	3		T7	3		T10	5
valid_sources[0x05]	29821	1			T3	2		T9	5		T7	4
valid_sources[0x06]	29326	1			T2	2		T9	7		T7	1
valid_sources[0x07]	29201	1			T3	5		T9	2		T10	6
valid_sources[0x08]	29106	1			T2	1		T3	4		T9	13
valid_sources[0x09]	30097	1			T3	3		T7	2		T10	6
valid_sources[0x0a]	31123	1			T1	2		T2	2		T3	3
valid_sources[0x0b]	29215	1			T1	12		T2	7		T3	2
valid_sources[0x0c]	31119	1			T3	3		T10	3		T8	6
valid_sources[0x0d]	30368	1			T3	8		T9	7		T7	11
valid_sources[0x0e]	29819	1			T3	5		T9	11		T7	4
valid_sources[0x0f]	29727	1			T1	3		T2	19		T3	4
valid_sources[0x10]	29572	1			T1	2		T3	5		T7	2
valid_sources[0x11]	29888	1			T3	4		T9	13		T8	2
valid_sources[0x12]	29481	1			T9	1		T10	3		T8	3
valid_sources[0x13]	28697	1			T3	2		T11	22		T13	1
valid_sources[0x14]	29677	1			T1	2		T3	2		T10	5
valid_sources[0x15]	29913	1			T2	16		T3	1		T7	2
valid_sources[0x16]	29701	1			T3	1		T9	3		T7	2
valid_sources[0x17]	29631	1			T3	2		T9	10		T10	2
valid_sources[0x18]	29862	1			T3	5		T7	1		T10	2
valid_sources[0x19]	29244	1			T1	21		T2	4		T9	11
valid_sources[0x1a]	29898	1			T2	10		T7	1		T8	7
valid_sources[0x1b]	29719	1			T3	2		T9	4		T7	1
valid_sources[0x1c]	29901	1			T3	2		T10	7		T8	2
valid_sources[0x1d]	29581	1			T3	5		T10	1		T8	2
valid_sources[0x1e]	29388	1			T3	2		T9	5		T10	2
valid_sources[0x1f]	28926	1			T2	2		T9	3		T7	5
valid_sources[0x20]	29471	1			T9	10		T10	3		T8	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27200

1

T2

1

T3

1

T9

4

values[0x0]

all_enables

biggest_size

207382

1

T1

16

T2

20

T3

26

values[0x1]

all_enables

biggest_size

27163

1

T1

1

T2

1

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1654974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269618

1

T1

20

T2

23

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	656646	1			T1	55		T2	65		T3	51
values[0x0]	610003	1			T1	60		T2	68		T3	41
values[0x1]	657943	1			T1	63		T2	48		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1271101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

653491

1

T1

60

T2

51

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30034	1			T1	4		T3	1		T9	2
valid_sources[0x01]	30154	1			T3	2		T9	1		T8	1
valid_sources[0x02]	29235	1			T1	1		T10	4		T11	20
valid_sources[0x03]	30213	1			T1	4		T2	9		T7	4
valid_sources[0x04]	29512	1			T1	5		T2	10		T3	4
valid_sources[0x05]	29923	1			T3	3		T9	4		T7	3
valid_sources[0x06]	29444	1			T1	2		T9	1		T11	16
valid_sources[0x07]	30529	1			T1	10		T9	4		T7	3
valid_sources[0x08]	29862	1			T1	1		T2	2		T3	5
valid_sources[0x09]	30522	1			T2	3		T3	1		T7	8
valid_sources[0x0a]	29951	1			T1	9		T3	1		T9	8
valid_sources[0x0b]	29126	1			T1	2		T9	3		T11	8
valid_sources[0x0c]	30234	1			T1	2		T9	4		T7	1
valid_sources[0x0d]	30121	1			T1	2		T2	3		T3	1
valid_sources[0x0e]	30412	1			T1	3		T2	6		T7	7
valid_sources[0x0f]	30360	1			T1	3		T3	7		T9	7
valid_sources[0x10]	29984	1			T10	7		T8	1		T11	17
valid_sources[0x11]	30572	1			T1	1		T9	5		T7	2
valid_sources[0x12]	30302	1			T1	2		T3	2		T9	1
valid_sources[0x13]	29281	1			T1	3		T3	6		T9	7
valid_sources[0x14]	29463	1			T3	3		T9	1		T7	3
valid_sources[0x15]	29020	1			T1	5		T3	4		T9	3
valid_sources[0x16]	30143	1			T1	2		T7	3		T8	6
valid_sources[0x17]	29651	1			T1	3		T9	1		T7	3
valid_sources[0x18]	30307	1			T1	5		T2	1		T3	2
valid_sources[0x19]	29907	1			T1	3		T3	4		T7	13
valid_sources[0x1a]	30736	1			T1	1		T7	4		T8	2
valid_sources[0x1b]	30268	1			T2	4		T3	5		T10	5
valid_sources[0x1c]	30030	1			T1	4		T3	7		T10	1
valid_sources[0x1d]	30574	1			T9	2		T7	3		T11	22
valid_sources[0x1e]	29882	1			T1	5		T10	8		T8	3
valid_sources[0x1f]	30038	1			T1	6		T9	3		T10	2
valid_sources[0x20]	29549	1			T1	1		T3	6		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28056

1

T2

3

T3

2

T9

3

values[0x0]

all_enables

biggest_size

213496

1

T1

18

T2

18

T3

14

values[0x1]

all_enables

biggest_size

28066

1

T1

2

T2

2

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1647335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262036

1

T1

16

T2

11

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647447	1			T1	33		T2	46		T3	71
values[0x0]	615168	1			T1	43		T2	41		T3	56
values[0x1]	646756	1			T1	45		T2	34		T3	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1273772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

635599

1

T1

36

T2

38

T3

76

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29920	1			T2	1		T3	1		T9	1
valid_sources[0x01]	29119	1			T2	5		T3	3		T9	3
valid_sources[0x02]	29242	1			T1	1		T2	2		T9	6
valid_sources[0x03]	29536	1			T1	2		T3	1		T11	9
valid_sources[0x04]	29205	1			T1	1		T2	2		T3	1
valid_sources[0x05]	29299	1			T1	2		T2	2		T9	3
valid_sources[0x06]	29234	1			T1	3		T2	1		T3	5
valid_sources[0x07]	29376	1			T2	5		T3	2		T9	2
valid_sources[0x08]	29935	1			T3	2		T9	3		T10	3
valid_sources[0x09]	30063	1			T1	2		T2	2		T9	2
valid_sources[0x0a]	29931	1			T1	1		T3	6		T9	3
valid_sources[0x0b]	29666	1			T1	2		T3	4		T9	2
valid_sources[0x0c]	29718	1			T1	3		T2	1		T9	2
valid_sources[0x0d]	30231	1			T1	1		T2	1		T3	4
valid_sources[0x0e]	30196	1			T1	3		T2	2		T9	1
valid_sources[0x0f]	30238	1			T1	2		T2	4		T3	1
valid_sources[0x10]	30408	1			T1	2		T2	6		T9	3
valid_sources[0x11]	29502	1			T1	2		T2	3		T3	3
valid_sources[0x12]	29283	1			T2	4		T9	1		T10	7
valid_sources[0x13]	29121	1			T1	2		T2	2		T3	4
valid_sources[0x14]	29708	1			T1	2		T3	3		T9	13
valid_sources[0x15]	30193	1			T1	3		T3	3		T7	1
valid_sources[0x16]	30071	1			T1	4		T2	2		T3	2
valid_sources[0x17]	29557	1			T2	4		T3	5		T9	1
valid_sources[0x18]	29373	1			T3	1		T9	1		T7	9
valid_sources[0x19]	30313	1			T1	4		T3	2		T9	2
valid_sources[0x1a]	29994	1			T1	3		T3	1		T9	5
valid_sources[0x1b]	30689	1			T1	2		T2	2		T9	3
valid_sources[0x1c]	29467	1			T1	3		T2	3		T3	6
valid_sources[0x1d]	30443	1			T1	1		T2	11		T3	2
valid_sources[0x1e]	30196	1			T1	3		T2	2		T3	3
valid_sources[0x1f]	29318	1			T1	2		T2	1		T3	1
valid_sources[0x20]	30346	1			T1	5		T2	9		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27467

1

T1

2

T2

1

T3

4

values[0x0]

all_enables

biggest_size

207511

1

T1

12

T2

10

T3

25

values[0x1]

all_enables

biggest_size

27058

1

T1

2

T3

3

T7

1