Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1304114 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 206824 1 T1 21 T2 11 T3 11


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 514311 1 T1 59 T2 42 T3 36
values[0x0] 482398 1 T1 54 T2 38 T3 37
values[0x1] 514229 1 T1 50 T2 38 T3 44


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1006903 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 504035 1 T1 62 T2 31 T3 34


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 23157 1 T3 1 T8 98 T9 8
valid_sources[0x01] 24230 1 T2 4 T3 1 T8 40
valid_sources[0x02] 23892 1 T8 16 T9 29 T10 39
valid_sources[0x03] 23994 1 T2 2 T3 3 T8 79
valid_sources[0x04] 24562 1 T3 1 T8 40 T9 86
valid_sources[0x05] 23672 1 T3 1 T8 171 T9 41
valid_sources[0x06] 23722 1 T1 11 T8 45 T9 38
valid_sources[0x07] 23852 1 T3 10 T8 14 T9 46
valid_sources[0x08] 23712 1 T3 11 T8 79 T9 37
valid_sources[0x09] 24000 1 T2 5 T3 2 T8 24
valid_sources[0x0a] 22790 1 T2 2 T8 52 T9 7
valid_sources[0x0b] 24193 1 T2 1 T8 12 T9 5
valid_sources[0x0c] 23803 1 T1 28 T2 3 T8 32
valid_sources[0x0d] 23088 1 T1 1 T2 1 T3 2
valid_sources[0x0e] 23028 1 T2 3 T3 5 T8 13
valid_sources[0x0f] 23762 1 T2 6 T8 53 T9 34
valid_sources[0x10] 23279 1 T2 1 T8 52 T9 51
valid_sources[0x11] 23455 1 T8 56 T9 32 T10 24
valid_sources[0x12] 23603 1 T2 2 T8 30 T9 7
valid_sources[0x13] 22056 1 T2 2 T8 16 T9 16
valid_sources[0x14] 23496 1 T1 27 T2 7 T3 1
valid_sources[0x15] 23584 1 T1 6 T2 5 T8 73
valid_sources[0x16] 23584 1 T2 1 T3 5 T8 50
valid_sources[0x17] 24049 1 T2 2 T8 103 T9 28
valid_sources[0x18] 24214 1 T1 12 T3 1 T8 23
valid_sources[0x19] 23447 1 T2 2 T8 34 T9 30
valid_sources[0x1a] 23560 1 T2 1 T8 10 T10 26
valid_sources[0x1b] 23455 1 T8 68 T9 26 T10 37
valid_sources[0x1c] 23375 1 T2 2 T3 2 T8 11
valid_sources[0x1d] 24170 1 T2 2 T8 15 T9 14
valid_sources[0x1e] 23305 1 T1 14 T2 1 T9 27
valid_sources[0x1f] 24305 1 T2 1 T3 1 T8 23
valid_sources[0x20] 24083 1 T2 1 T3 8 T8 116


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 21757 1 T1 2 T2 3 T3 1
values[0x0] all_enables biggest_size 163089 1 T1 19 T2 6 T3 9
values[0x1] all_enables biggest_size 21978 1 T2 2 T3 1 T8 42


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1313008 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 213435 1 T1 23 T2 25 T3 23


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 523952 1 T1 57 T2 51 T3 52
values[0x0] 479068 1 T1 60 T2 51 T3 46
values[0x1] 523423 1 T1 56 T2 66 T3 66


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1007125 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 519318 1 T1 64 T2 63 T3 60


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 24583 1 T2 3 T3 9 T8 13
valid_sources[0x01] 23608 1 T1 2 T2 2 T3 1
valid_sources[0x02] 23403 1 T1 1 T3 4 T8 80
valid_sources[0x03] 23511 1 T2 5 T8 59 T9 38
valid_sources[0x04] 23654 1 T2 9 T8 32 T9 85
valid_sources[0x05] 23476 1 T2 1 T3 6 T8 55
valid_sources[0x06] 23855 1 T2 3 T8 32 T9 29
valid_sources[0x07] 23487 1 T2 2 T3 1 T8 44
valid_sources[0x08] 23855 1 T1 4 T2 4 T3 5
valid_sources[0x09] 24588 1 T2 2 T3 1 T8 37
valid_sources[0x0a] 23783 1 T2 3 T3 1 T8 67
valid_sources[0x0b] 23913 1 T1 15 T2 2 T8 65
valid_sources[0x0c] 23872 1 T3 2 T8 65 T9 15
valid_sources[0x0d] 24074 1 T2 4 T3 4 T8 33
valid_sources[0x0e] 23736 1 T1 23 T2 1 T3 1
valid_sources[0x0f] 23889 1 T2 1 T8 94 T9 44
valid_sources[0x10] 23486 1 T3 2 T8 23 T9 69
valid_sources[0x11] 23045 1 T3 15 T8 32 T9 28
valid_sources[0x12] 24240 1 T1 4 T2 3 T3 3
valid_sources[0x13] 23319 1 T1 1 T2 2 T8 31
valid_sources[0x14] 24059 1 T1 6 T3 2 T8 56
valid_sources[0x15] 24406 1 T1 1 T3 5 T8 29
valid_sources[0x16] 24056 1 T2 1 T8 60 T9 25
valid_sources[0x17] 25259 1 T2 6 T3 4 T8 32
valid_sources[0x18] 23439 1 T1 3 T2 1 T8 49
valid_sources[0x19] 23758 1 T2 1 T3 3 T8 23
valid_sources[0x1a] 24381 1 T1 5 T3 2 T8 34
valid_sources[0x1b] 23169 1 T2 3 T8 19 T9 28
valid_sources[0x1c] 24232 1 T2 3 T3 4 T8 78
valid_sources[0x1d] 23825 1 T3 5 T8 67 T9 17
valid_sources[0x1e] 23978 1 T1 17 T8 34 T9 41
valid_sources[0x1f] 24219 1 T1 1 T2 1 T3 3
valid_sources[0x20] 23101 1 T3 6 T8 19 T9 14


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 22621 1 T1 5 T2 1 T3 2
values[0x0] all_enables biggest_size 168177 1 T1 16 T2 22 T3 18
values[0x1] all_enables biggest_size 22637 1 T1 2 T2 2 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1314876 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 208416 1 T1 16 T2 19 T3 16


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 518082 1 T1 31 T2 36 T3 59
values[0x0] 487434 1 T1 43 T2 46 T3 41
values[0x1] 517776 1 T1 35 T2 54 T3 51


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1016859 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 506433 1 T1 36 T2 54 T3 43


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 23559 1 T1 4 T8 26 T9 6
valid_sources[0x01] 23573 1 T1 27 T2 4 T3 10
valid_sources[0x02] 23901 1 T3 7 T8 43 T9 20
valid_sources[0x03] 24283 1 T2 3 T8 30 T9 38
valid_sources[0x04] 24371 1 T2 2 T3 30 T8 36
valid_sources[0x05] 22984 1 T8 33 T9 39 T10 24
valid_sources[0x06] 23623 1 T8 34 T9 42 T10 33
valid_sources[0x07] 23960 1 T2 4 T8 29 T9 54
valid_sources[0x08] 24030 1 T2 1 T8 36 T9 17
valid_sources[0x09] 24290 1 T2 3 T8 52 T9 30
valid_sources[0x0a] 23852 1 T1 11 T2 2 T3 4
valid_sources[0x0b] 23869 1 T2 4 T3 1 T8 28
valid_sources[0x0c] 23708 1 T2 3 T8 37 T9 32
valid_sources[0x0d] 23544 1 T2 2 T8 38 T9 16
valid_sources[0x0e] 24190 1 T1 2 T2 3 T3 6
valid_sources[0x0f] 23397 1 T2 5 T3 10 T8 35
valid_sources[0x10] 23646 1 T2 3 T8 45 T9 74
valid_sources[0x11] 23449 1 T2 4 T3 1 T8 30
valid_sources[0x12] 23729 1 T3 1 T8 54 T9 7
valid_sources[0x13] 23340 1 T2 5 T8 66 T9 5
valid_sources[0x14] 23416 1 T1 3 T8 34 T10 38
valid_sources[0x15] 23986 1 T2 3 T8 30 T9 80
valid_sources[0x16] 23808 1 T2 6 T3 4 T8 41
valid_sources[0x17] 23824 1 T2 5 T8 40 T9 32
valid_sources[0x18] 23367 1 T2 4 T3 3 T8 55
valid_sources[0x19] 23767 1 T8 48 T9 34 T10 43
valid_sources[0x1a] 23869 1 T2 2 T8 51 T10 31
valid_sources[0x1b] 25255 1 T2 2 T3 9 T8 34
valid_sources[0x1c] 23854 1 T2 2 T8 39 T9 21
valid_sources[0x1d] 23878 1 T2 1 T8 38 T9 31
valid_sources[0x1e] 23414 1 T1 30 T2 1 T8 43
valid_sources[0x1f] 24407 1 T2 2 T8 51 T9 38
valid_sources[0x20] 24357 1 T2 5 T8 47 T9 9


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 22237 1 T2 1 T3 2 T8 35
values[0x0] all_enables biggest_size 164216 1 T1 15 T2 17 T3 11
values[0x1] all_enables biggest_size 21963 1 T1 1 T2 1 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%