Unified Coverage Report :: Module :: prim_fifo_async

Module : prim_fifo_async

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	96.43			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_asf_35.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_37.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_39.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_41.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_35.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_37.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_39.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_41.reqfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_asf_35.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_35

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_37.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_37

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_39.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_39

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_41.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_41

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_35.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_35

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_37.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_37

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_39.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_39

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_41.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_41

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_asf_35.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_37.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_39.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_41.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :

SCORE	COND
98.21	92.86

tb.dut.u_asf_35.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_37.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_39.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_41.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_async

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	2147483647	2147483647	0	0
GrayWptr_A	2147483647	2147483647	0	0
ParamCheckDepth_A	7200	7200	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	25291	25105	0	0
T2	31384	30935	0	0
T3	87110	86765	0	0
T7	32155	31951	0	0
T8	124472	124096	0	0
T9	130593	130102	0	0
T10	75152	74714	0	0
T11	61229	60922	0	0
T12	557168	556954	0	0
T13	2999833	2999332	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	25291	25105	0	0
T2	31384	30935	0	0
T3	87110	86765	0	0
T7	32155	31951	0	0
T8	124472	124096	0	0
T9	130593	130102	0	0
T10	75152	74714	0	0
T11	61229	60922	0	0
T12	557168	556954	0	0
T13	2999833	2999332	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7200	7200	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T7	8	8	0	0
T8	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0
T11	8	8	0	0
T12	8	8	0	0
T13	8	8	0	0

Line Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	426211218	426087618	0	0
GrayWptr_A	537872844	537752068	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537872844	537752068	0	0
T1	4760	4725	0	0
T2	2124	2093	0	0
T3	16052	15989	0	0
T7	4939	4908	0	0
T8	17871	17817	0	0
T9	22757	22671	0	0
T10	9122	9068	0	0
T11	15499	15422	0	0
T12	83821	83789	0	0
T13	372847	372785	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	426211218	426087618	0	0
GrayWptr_A	595202208	595078576	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595202208	595078576	0	0
T1	9148	9081	0	0
T2	1770	1744	0	0
T3	12805	12754	0	0
T7	8232	8181	0	0
T8	19753	19694	0	0
T9	23791	23702	0	0
T10	1338	1329	0	0
T11	15117	15042	0	0
T12	31227	31215	0	0
T13	288116	288067	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	426211218	426087618	0	0
GrayWptr_A	556891352	556766728	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556891352	556766728	0	0
T1	1960	1945	0	0
T2	5900	5815	0	0
T3	13346	13294	0	0
T7	1549	1539	0	0
T8	26337	26258	0	0
T9	5430	5409	0	0
T10	9364	9310	0	0
T11	3252	3236	0	0
T12	146276	146221	0	0
T13	372847	372785	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T12
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	426211218	426087618	0	0
GrayWptr_A	558353962	558230090	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558353962	558230090	0	0
T1	2707	2686	0	0
T2	2714	2675	0	0
T3	3787	3772	0	0
T7	3099	3079	0	0
T8	10347	10315	0	0
T9	8275	8244	0	0
T10	10580	10519	0	0
T11	15117	15042	0	0
T12	92040	92005	0	0
T13	451951	451875	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	537872844	537752068	0	0
GrayWptr_A	426211218	426087618	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537872844	537752068	0	0
T1	4760	4725	0	0
T2	2124	2093	0	0
T3	16052	15989	0	0
T7	4939	4908	0	0
T8	17871	17817	0	0
T9	22757	22671	0	0
T10	9122	9068	0	0
T11	15499	15422	0	0
T12	83821	83789	0	0
T13	372847	372785	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	595202208	595078576	0	0
GrayWptr_A	426211218	426087618	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595202208	595078576	0	0
T1	9148	9081	0	0
T2	1770	1744	0	0
T3	12805	12754	0	0
T7	8232	8181	0	0
T8	19753	19694	0	0
T9	23791	23702	0	0
T10	1338	1329	0	0
T11	15117	15042	0	0
T12	31227	31215	0	0
T13	288116	288067	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	556891352	556766728	0	0
GrayWptr_A	426211218	426087618	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556891352	556766728	0	0
T1	1960	1945	0	0
T2	5900	5815	0	0
T3	13346	13294	0	0
T7	1549	1539	0	0
T8	26337	26258	0	0
T9	5430	5409	0	0
T10	9364	9310	0	0
T11	3252	3236	0	0
T12	146276	146221	0	0
T13	372847	372785	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

52                      
53         1/1            assign fifo_incr_wptr = wvalid_i & wready_o;
           Tests:       T1 T2 T3 
54                      
55                        // decimal version
56         1/1            assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
60         1/1                fifo_wptr_q <= '0;
           Tests:       T1 T2 T3 
61         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
62         1/1                fifo_wptr_q <= fifo_wptr_d;
           Tests:       T1 T2 T3 
63                          end
                        MISSING_ELSE
64                        end
65                      
66                        // gray-coded version
67                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
69         1/1                fifo_wptr_gray_q <= '0;
           Tests:       T1 T2 T3 
70         1/1              end else if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
71         1/1                fifo_wptr_gray_q <= fifo_wptr_gray_d;
           Tests:       T1 T2 T3 
72                          end
                        MISSING_ELSE
73                        end
74                      
75                        // sync gray-coded pointer to read clk
76                        prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77                          .clk_i    (clk_rd_i),
78                          .rst_ni   (rst_rd_ni),
79                          .d_i      (fifo_wptr_gray_q),
80                          .q_o      (fifo_wptr_gray_sync));
81                      
82                        //////////////////
83                        // Read Pointer //
84                        //////////////////
85                      
86         1/1            assign fifo_incr_rptr = rvalid_o & rready_i;
           Tests:       T1 T2 T3 
87                      
88                        // decimal version
89         1/1            assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
           Tests:       T1 T2 T3 
90                      
91                        always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92         1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
93         1/1                fifo_rptr_q <= '0;
           Tests:       T1 T2 T3 
94         1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
95         1/1                fifo_rptr_q <= fifo_rptr_d;
           Tests:       T1 T2 T3 
96                          end
                        MISSING_ELSE
97                        end
98                      
99                        // gray-coded version
100                       always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101        1/1              if (!rst_rd_ni) begin
           Tests:       T1 T2 T3 
102        1/1                fifo_rptr_gray_q <= '0;
           Tests:       T1 T2 T3 
103        1/1              end else if (fifo_incr_rptr) begin
           Tests:       T1 T2 T3 
104        1/1                fifo_rptr_gray_q <= fifo_rptr_gray_d;
           Tests:       T1 T2 T3 
105                         end
                        MISSING_ELSE
106                       end
107                     
108                       // sync gray-coded pointer to write clk
109                       prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110                         .clk_i    (clk_wr_i),
111                         .rst_ni   (rst_wr_ni),
112                         .d_i      (fifo_rptr_gray_q),
113                         .q_o      (fifo_rptr_gray_sync));
114                     
115                       // Registered version of synced read pointer
116                       always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117        1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
118        1/1                fifo_rptr_sync_q <= '0;
           Tests:       T1 T2 T3 
119                         end else begin
120        1/1                fifo_rptr_sync_q <= fifo_rptr_sync_combi;
           Tests:       T1 T2 T3 
121                         end
122                       end
123                     
124                       //////////////////
125                       // Empty / Full //
126                       //////////////////
127                     
128                       logic [PTR_WIDTH-1:0] xor_mask;
129                       assign xor_mask   =  PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130        1/1            assign full_wclk  = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
           Tests:       T1 T2 T3 
131        1/1            assign full_rclk  = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
           Tests:       T1 T2 T3 
132        1/1            assign empty_rclk = (fifo_wptr_sync_combi ==  fifo_rptr_q);
           Tests:       T1 T2 T3 
133                     
134                       if (Depth > 1) begin : g_depth_calc
135                     
136                         // Current depth in the write clock side
137                         logic               wptr_msb;
138                         logic               rptr_sync_msb;
139                         logic  [PTRV_W-1:0] wptr_value;
140                         logic  [PTRV_W-1:0] rptr_sync_value;
141                     
142                         assign wptr_msb        = fifo_wptr_q[PTR_WIDTH-1];
143                         assign rptr_sync_msb   = fifo_rptr_sync_q[PTR_WIDTH-1];
144                         assign wptr_value      = fifo_wptr_q[0+:PTRV_W];
145                         assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
146                         assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
147                                           (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148                                           (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149                     
150                         // Current depth in the read clock side
151                         logic               rptr_msb;
152                         logic               wptr_sync_msb;
153                         logic  [PTRV_W-1:0] rptr_value;
154                         logic  [PTRV_W-1:0] wptr_sync_value;
155                     
156                         assign wptr_sync_msb   = fifo_wptr_sync_combi[PTR_WIDTH-1];
157                         assign rptr_msb        = fifo_rptr_q[PTR_WIDTH-1];
158                         assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
159                         assign rptr_value      = fifo_rptr_q[0+:PTRV_W];
160                         assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
161                                           (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162                                           (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163                     
164                       end else begin : g_no_depth_calc
165                     
166        1/1              assign rdepth_o = full_rclk;
           Tests:       T1 T2 T3 
167        1/1              assign wdepth_o = full_wclk;
           Tests:       T1 T2 T3 
168                     
169                       end
170                     
171        1/1            assign wready_o = ~full_wclk;
           Tests:       T1 T2 T3 
172        1/1            assign rvalid_o = ~empty_rclk;
           Tests:       T1 T2 T3 
173                     
174                       /////////////
175                       // Storage //
176                       /////////////
177                     
178                       logic [Width-1:0] rdata_int;
179                       if (Depth > 1) begin : g_storage_mux
180                     
181                         always_ff @(posedge clk_wr_i) begin
182                           if (fifo_incr_wptr) begin
183                             storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
184                           end
185                         end
186                     
187                         assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
188                     
189                       end else begin : g_storage_simple
190                     
191                         always_ff @(posedge clk_wr_i) begin
192        1/1                if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
193        1/1                  storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
194                           end
                        MISSING_ELSE
195                         end
196                     
197        1/1              assign rdata_int = storage[0];
           Tests:       T1 T2 T3 
198                     
199                       end
200                     
201                       // rdata_o is qualified with rvalid_o to avoid CDC error
202                       if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
204                           assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205                         end
206                         else begin : gen_invalid_non_zero
207                           assign rdata_o = empty_rclk ? '0 : rdata_int;
208                         end
209                       end else begin : gen_no_output_zero
210                         if (OutputZeroIfInvalid  == 1'b1) begin : gen_invalid_zero
211        1/1                  assign rdata_o = rvalid_o ? rdata_int : '0;
           Tests:       T1 T2 T3 
212                         end
213                         else begin : gen_invalid_non_zero
214                             assign rdata_o = rdata_int;
215                         end
216                       end
217                     
218                       //////////////////////////////////////
219                       // Decimal <-> Gray-code Conversion //
220                       //////////////////////////////////////
221                     
222                       // This code is all in a generate context to avoid lint errors when Depth <= 2
223                       if (Depth > 2) begin : g_full_gray_conversion
224                     
225                         function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226                           logic [PTR_WIDTH-1:0] decval_sub;
227                           logic [PTR_WIDTH-1:0] decval_in;
228                           logic                 unused_decval_msb;
229                     
230                           decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231                     
232                           decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233                     
234                           // We do not care about the MSB, hence we mask it out
235                           unused_decval_msb = decval_in[PTR_WIDTH-1];
236                           decval_in[PTR_WIDTH-1] = 1'b0;
237                     
238                           // Perform the XOR conversion
239                           dec2gray = decval_in;
240                           dec2gray ^= (decval_in >> 1);
241                     
242                           // Override the MSB
243                           dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244                         endfunction
245                     
246                         // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247                         function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248                           logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249                           logic                 unused_decsub_msb;
250                     
251                           dec_tmp = '0;
252                           for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253                             dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254                           end
255                           dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256                           if (grayval[PTR_WIDTH-1]) begin
257                             gray2dec = dec_tmp_sub;
258                             // Override MSB
259                             gray2dec[PTR_WIDTH-1] = 1'b1;
260                             unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261                           end else begin
262                             gray2dec = dec_tmp;
263                           end
264                         endfunction
265                     
266                         // decimal version of read pointer in write domain
267                         assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268                         // decimal version of write pointer in read domain
269                         assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270                     
271                         assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272                         assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273                     
274                       end else if (Depth == 2) begin : g_simple_gray_conversion
275                     
276                         assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
277                         assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
278                     
279                         assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
280                         assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
281                     
282                       end else begin : g_no_gray_conversion
283                     
284        1/1              assign fifo_rptr_sync_combi = fifo_rptr_gray_sync;
           Tests:       T1 T2 T3 
285        1/1              assign fifo_wptr_sync_combi = fifo_wptr_gray_sync;
           Tests:       T1 T2 T3 
286                     
287        1/1              assign fifo_rptr_gray_d = fifo_rptr_d;
           Tests:       T1 T2 T3 
288        1/1              assign fifo_wptr_gray_d = fifo_wptr_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

211                assign rdata_o = rvalid_o ? rdata_int : '0;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

59             if (!rst_wr_ni) begin
               -1-  
60               fifo_wptr_q <= '0;
                 ==>
61             end else if (fifo_incr_wptr) begin
                        -2-     
62               fifo_wptr_q <= fifo_wptr_d;
                 ==>
63             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

68             if (!rst_wr_ni) begin
               -1-  
69               fifo_wptr_gray_q <= '0;
                 ==>
70             end else if (fifo_incr_wptr) begin
                        -2-     
71               fifo_wptr_gray_q <= fifo_wptr_gray_d;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

92             if (!rst_rd_ni) begin
               -1-  
93               fifo_rptr_q <= '0;
                 ==>
94             end else if (fifo_incr_rptr) begin
                        -2-     
95               fifo_rptr_q <= fifo_rptr_d;
                 ==>
96             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

101            if (!rst_rd_ni) begin
               -1-  
102              fifo_rptr_gray_q <= '0;
                 ==>
103            end else if (fifo_incr_rptr) begin
                        -2-     
104              fifo_rptr_gray_q <= fifo_rptr_gray_d;
                 ==>
105            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

117            if (!rst_wr_ni) begin
               -1-  
118              fifo_rptr_sync_q <= '0;
                 ==>
119            end else begin
120              fifo_rptr_sync_q <= fifo_rptr_sync_combi;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

192              if (fifo_incr_wptr) begin
                 -1-     
193                storage[0] <= wdata_i;
                   ==>
194              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	558353962	558230090	0	0
GrayWptr_A	426211218	426087618	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558353962	558230090	0	0
T1	2707	2686	0	0
T2	2714	2675	0	0
T3	3787	3772	0	0
T7	3099	3079	0	0
T8	10347	10315	0	0
T9	8275	8244	0	0
T10	10580	10519	0	0
T11	15117	15042	0	0
T12	92040	92005	0	0
T13	451951	451875	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426087618	0	0
T1	1679	1667	0	0
T2	4719	4652	0	0
T3	10280	10239	0	0
T7	3584	3561	0	0
T8	12541	12503	0	0
T9	17585	17519	0	0
T10	11187	11122	0	0
T11	3061	3045	0	0
T12	50951	50931	0	0
T13	378518	378455	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0