Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7125909	0	0
GntImpliesValid_A	2147483647	7125909	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7125909	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	456455373	0	0
ReadyAndValidImplyGrant_A	2147483647	7125909	0	0
ReqAndReadyImplyGrant_A	2147483647	7125909	0	0
ReqImpliesValid_A	2147483647	31682713	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	39886	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7125909	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	40296	40032	0	0
T2	113256	111672	0	0
T3	246720	245760	0	0
T7	86016	85488	0	0
T8	300984	300096	0	0
T9	422040	420480	0	0
T10	268488	266952	0	0
T11	73464	73104	0	0
T12	1222824	1222368	0	0
T13	9084432	9082944	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	40296	40032	0	0
T2	113256	111672	0	0
T3	246720	245760	0	0
T7	86016	85488	0	0
T8	300984	300096	0	0
T9	422040	420480	0	0
T10	268488	266952	0	0
T11	73464	73104	0	0
T12	1222824	1222368	0	0
T13	9084432	9082944	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	40296	40032	0	0
T2	113256	111672	0	0
T3	246720	245760	0	0
T7	86016	85488	0	0
T8	300984	300096	0	0
T9	422040	420480	0	0
T10	268488	266952	0	0
T11	73464	73104	0	0
T12	1222824	1222368	0	0
T13	9084432	9082944	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	456455373	0	0
T1	40296	462	0	0
T2	113256	6891	0	0
T3	246720	11999	0	0
T7	86016	4627	0	0
T8	300984	8649	0	0
T9	422040	8859	0	0
T10	268488	899	0	0
T11	73464	1317	0	0
T12	1222824	82332	0	0
T13	9084432	469867	0	0
T14	0	122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31682713	0	0
T1	40296	486	0	0
T2	113256	1053	0	0
T3	246720	988	0	0
T7	86016	501	0	0
T8	300984	9172	0	0
T9	422040	5932	0	0
T10	268488	12618	0	0
T11	73464	1432	0	0
T12	1222824	13528	0	0
T13	9084432	19057	0	0
T14	0	195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39886	0	21600
T7	7168	0	0	2
T8	25082	38	0	2
T9	35170	25	0	2
T10	22374	0	0	2
T11	6122	2	0	2
T12	101902	2	0	2
T13	757036	0	0	2
T14	3150	0	0	2
T15	9224	11	0	2
T16	0	10	0	0
T17	0	2	0	0
T18	0	22	0	0
T19	0	61	0	0
T20	0	8	0	0
T21	0	13	0	0
T22	0	31	0	0
T23	0	1	0	0
T24	4016	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	40296	40032	0	0
T2	113256	111672	0	0
T3	246720	245760	0	0
T7	86016	85488	0	0
T8	300984	300096	0	0
T9	422040	420480	0	0
T10	268488	266952	0	0
T11	73464	73104	0	0
T12	1222824	1222368	0	0
T13	9084432	9082944	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7125909	0	0
T1	40296	445	0	0
T2	113256	421	0	0
T3	246720	432	0	0
T7	86016	220	0	0
T8	300984	8021	0	0
T9	422040	5698	0	0
T10	268488	6069	0	0
T11	73464	1300	0	0
T12	1222824	5894	0	0
T13	9084432	389	0	0
T14	0	182	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	795199	0	0
GntImpliesValid_A	426211218	795199	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	795199	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	11534392	0	0
ReadyAndValidImplyGrant_A	426211218	795199	0	0
ReqAndReadyImplyGrant_A	426211218	795199	0	0
ReqImpliesValid_A	426211218	2309353	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	795199	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	11534392	0	0
T1	1679	41	0	0
T2	4719	384	0	0
T3	10280	414	0	0
T7	3584	109	0	0
T8	12541	684	0	0
T9	17585	671	0	0
T10	11187	351	0	0
T11	3061	121	0	0
T12	50951	4240	0	0
T13	378518	11276	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2309353	0	0
T1	1679	48	0	0
T2	4719	118	0	0
T3	10280	108	0	0
T7	3584	19	0	0
T8	12541	1193	0	0
T9	17585	710	0	0
T10	11187	628	0	0
T11	3061	166	0	0
T12	50951	1057	0	0
T13	378518	506	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795199	0	0
T1	1679	44	0	0
T2	4719	59	0	0
T3	10280	55	0	0
T7	3584	17	0	0
T8	12541	938	0	0
T9	17585	690	0	0
T10	11187	489	0	0
T11	3061	143	0	0
T12	50951	583	0	0
T13	378518	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	795112	0	0
GntImpliesValid_A	426211218	795112	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	795112	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	11383190	0	0
ReadyAndValidImplyGrant_A	426211218	795112	0	0
ReqAndReadyImplyGrant_A	426211218	795112	0	0
ReqImpliesValid_A	426211218	2268652	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	795112	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	11383190	0	0
T1	1679	58	0	0
T2	4719	297	0	0
T3	10280	334	0	0
T7	3584	140	0	0
T8	12541	657	0	0
T9	17585	633	0	0
T10	11187	340	0	0
T11	3061	125	0	0
T12	50951	4628	0	0
T13	378518	13425	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2268652	0	0
T1	1679	93	0	0
T2	4719	89	0	0
T3	10280	44	0	0
T7	3584	40	0	0
T8	12541	1134	0	0
T9	17585	654	0	0
T10	11187	637	0	0
T11	3061	182	0	0
T12	50951	1315	0	0
T13	378518	820	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	795112	0	0
T1	1679	75	0	0
T2	4719	49	0	0
T3	10280	42	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	643	0	0
T10	11187	488	0	0
T11	3061	153	0	0
T12	50951	671	0	0
T13	378518	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	199732	0	0
GntImpliesValid_A	426211218	199732	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	199732	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2867902	0	0
ReadyAndValidImplyGrant_A	426211218	199732	0	0
ReqAndReadyImplyGrant_A	426211218	199732	0	0
ReqImpliesValid_A	426211218	537418	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	199732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2867902	0	0
T1	1679	7	0	0
T2	4719	55	0	0
T3	10280	47	0	0
T7	3584	59	0	0
T8	12541	208	0	0
T9	17585	165	0	0
T10	11187	1	0	0
T11	3061	42	0	0
T12	50951	1405	0	0
T13	378518	2900	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	537418	0	0
T1	1679	6	0	0
T2	4719	27	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	235	0	0
T9	17585	168	0	0
T10	11187	0	0	0
T11	3061	45	0	0
T12	50951	263	0	0
T13	378518	10	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	199732	0	0
T1	1679	6	0	0
T2	4719	9	0	0
T3	10280	9	0	0
T7	3584	8	0	0
T8	12541	221	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	186	0	0
T13	378518	10	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	192301	0	0
GntImpliesValid_A	426211218	192301	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	192301	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2851717	0	0
ReadyAndValidImplyGrant_A	426211218	192301	0	0
ReqAndReadyImplyGrant_A	426211218	192301	0	0
ReqImpliesValid_A	426211218	546955	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	192301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2851717	0	0
T1	1679	13	0	0
T2	4719	102	0	0
T3	10280	160	0	0
T7	3584	73	0	0
T8	12541	206	0	0
T9	17585	142	0	0
T10	11187	70	0	0
T11	3061	36	0	0
T12	50951	1300	0	0
T13	378518	3215	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	546955	0	0
T1	1679	14	0	0
T2	4719	17	0	0
T3	10280	39	0	0
T7	3584	10	0	0
T8	12541	233	0	0
T9	17585	141	0	0
T10	11187	923	0	0
T11	3061	37	0	0
T12	50951	236	0	0
T13	378518	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	192301	0	0
T1	1679	13	0	0
T2	4719	14	0	0
T3	10280	18	0	0
T7	3584	10	0	0
T8	12541	219	0	0
T9	17585	141	0	0
T10	11187	496	0	0
T11	3061	36	0	0
T12	50951	173	0	0
T13	378518	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	189640	0	0
GntImpliesValid_A	426211218	189640	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	189640	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	4692832	0	0
ReadyAndValidImplyGrant_A	426211218	189640	0	0
ReqAndReadyImplyGrant_A	426211218	189640	0	0
ReqImpliesValid_A	426211218	936473	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	189640	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	4692832	0	0
T1	1679	49	0	0
T2	4719	297	0	0
T3	10280	107	0	0
T7	3584	58	0	0
T8	12541	959	0	0
T9	17585	777	0	0
T10	11187	0	0	0
T11	3061	118	0	0
T12	50951	1419	0	0
T13	378518	4866	0	0
T14	0	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	936473	0	0
T1	1679	12	0	0
T2	4719	28	0	0
T3	10280	30	0	0
T7	3584	6	0	0
T8	12541	309	0	0
T9	17585	178	0	0
T10	11187	0	0	0
T11	3061	56	0	0
T12	50951	273	0	0
T13	378518	13	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189640	0	0
T1	1679	12	0	0
T2	4719	14	0	0
T3	10280	14	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	156	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	179	0	0
T13	378518	13	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	204001	0	0
GntImpliesValid_A	426211218	204001	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	204001	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	4952974	0	0
ReadyAndValidImplyGrant_A	426211218	204001	0	0
ReqAndReadyImplyGrant_A	426211218	204001	0	0
ReqImpliesValid_A	426211218	1151224	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	204001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	4952974	0	0
T1	1679	31	0	0
T2	4719	287	0	0
T3	10280	180	0	0
T7	3584	16	0	0
T8	12541	869	0	0
T9	17585	742	0	0
T10	11187	0	0	0
T11	3061	83	0	0
T12	50951	3319	0	0
T13	378518	5180	0	0
T14	0	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	1151224	0	0
T1	1679	9	0	0
T2	4719	16	0	0
T3	10280	35	0	0
T7	3584	2	0	0
T8	12541	295	0	0
T9	17585	204	0	0
T10	11187	0	0	0
T11	3061	30	0	0
T12	50951	497	0	0
T13	378518	97	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	204001	0	0
T1	1679	9	0	0
T2	4719	11	0	0
T3	10280	21	0	0
T7	3584	2	0	0
T8	12541	197	0	0
T9	17585	155	0	0
T10	11187	0	0	0
T11	3061	25	0	0
T12	50951	187	0	0
T13	378518	11	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	187115	0	0
GntImpliesValid_A	426211218	187115	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	187115	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	4525320	0	0
ReadyAndValidImplyGrant_A	426211218	187115	0	0
ReqAndReadyImplyGrant_A	426211218	187115	0	0
ReqImpliesValid_A	426211218	931664	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	187115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	4525320	0	0
T1	1679	43	0	0
T2	4719	87	0	0
T3	10280	104	0	0
T7	3584	232	0	0
T8	12541	871	0	0
T9	17585	2120	0	0
T10	11187	0	0	0
T11	3061	160	0	0
T12	50951	896	0	0
T13	378518	3262	0	0
T14	0	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	931664	0	0
T1	1679	8	0	0
T2	4719	24	0	0
T3	10280	9	0	0
T7	3584	26	0	0
T8	12541	295	0	0
T9	17585	255	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	188	0	0
T13	378518	10	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	187115	0	0
T1	1679	8	0	0
T2	4719	8	0	0
T3	10280	9	0	0
T7	3584	9	0	0
T8	12541	214	0	0
T9	17585	175	0	0
T10	11187	0	0	0
T11	3061	29	0	0
T12	50951	151	0	0
T13	378518	10	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	195884	0	0
GntImpliesValid_A	426211218	195884	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	195884	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	4641472	0	0
ReadyAndValidImplyGrant_A	426211218	195884	0	0
ReqAndReadyImplyGrant_A	426211218	195884	0	0
ReqImpliesValid_A	426211218	1062234	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	195884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	4641472	0	0
T1	1679	55	0	0
T2	4719	236	0	0
T3	10280	148	0	0
T7	3584	45	0	0
T8	12541	1301	0	0
T9	17585	1445	0	0
T10	11187	42	0	0
T11	3061	124	0	0
T12	50951	1313	0	0
T13	378518	3037	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	1062234	0	0
T1	1679	22	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	8	0	0
T8	12541	379	0	0
T9	17585	195	0	0
T10	11187	3154	0	0
T11	3061	58	0	0
T12	50951	214	0	0
T13	378518	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	195884	0	0
T1	1679	13	0	0
T2	4719	13	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	221	0	0
T9	17585	160	0	0
T10	11187	448	0	0
T11	3061	41	0	0
T12	50951	161	0	0
T13	378518	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	205614	0	0
GntImpliesValid_A	426211218	205614	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	205614	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2826291	0	0
ReadyAndValidImplyGrant_A	426211218	205614	0	0
ReqAndReadyImplyGrant_A	426211218	205614	0	0
ReqImpliesValid_A	426211218	542320	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	205614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2826291	0	0
T1	1679	12	0	0
T2	4719	68	0	0
T3	10280	47	0	0
T7	3584	79	0	0
T8	12541	209	0	0
T9	17585	169	0	0
T10	11187	1	0	0
T11	3061	36	0	0
T12	50951	1436	0	0
T13	378518	3139	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	542320	0	0
T1	1679	11	0	0
T2	4719	11	0	0
T3	10280	25	0	0
T7	3584	7	0	0
T8	12541	236	0	0
T9	17585	170	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	271	0	0
T13	378518	513	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	205614	0	0
T1	1679	11	0	0
T2	4719	10	0	0
T3	10280	6	0	0
T7	3584	7	0	0
T8	12541	222	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	35	0	0
T12	50951	202	0	0
T13	378518	8	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	196266	0	0
GntImpliesValid_A	426211218	196266	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	196266	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2834518	0	0
ReadyAndValidImplyGrant_A	426211218	196266	0	0
ReqAndReadyImplyGrant_A	426211218	196266	0	0
ReqImpliesValid_A	426211218	521236	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	196266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2834518	0	0
T1	1679	14	0	0
T2	4719	64	0	0
T3	10280	99	0	0
T7	3584	22	0	0
T8	12541	184	0	0
T9	17585	170	0	0
T10	11187	1	0	0
T11	3061	24	0	0
T12	50951	1399	0	0
T13	378518	4118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	521236	0	0
T1	1679	15	0	0
T2	4719	19	0	0
T3	10280	30	0	0
T7	3584	3	0	0
T8	12541	213	0	0
T9	17585	173	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	303	0	0
T13	378518	76	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196266	0	0
T1	1679	14	0	0
T2	4719	11	0	0
T3	10280	12	0	0
T7	3584	3	0	0
T8	12541	198	0	0
T9	17585	171	0	0
T10	11187	0	0	0
T11	3061	27	0	0
T12	50951	176	0	0
T13	378518	15	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	196564	0	0
GntImpliesValid_A	426211218	196564	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	196564	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2759798	0	0
ReadyAndValidImplyGrant_A	426211218	196564	0	0
ReqAndReadyImplyGrant_A	426211218	196564	0	0
ReqImpliesValid_A	426211218	516995	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	196564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2759798	0	0
T1	1679	7	0	0
T2	4719	101	0	0
T3	10280	89	0	0
T7	3584	69	0	0
T8	12541	176	0	0
T9	17585	137	0	0
T10	11187	1	0	0
T11	3061	31	0	0
T12	50951	1264	0	0
T13	378518	3557	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	516995	0	0
T1	1679	8	0	0
T2	4719	10	0	0
T3	10280	30	0	0
T7	3584	11	0	0
T8	12541	189	0	0
T9	17585	138	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	265	0	0
T13	378518	96	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	196564	0	0
T1	1679	7	0	0
T2	4719	10	0	0
T3	10280	12	0	0
T7	3584	11	0	0
T8	12541	182	0	0
T9	17585	137	0	0
T10	11187	0	0	0
T11	3061	31	0	0
T12	50951	167	0	0
T13	378518	12	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	198059	0	0
GntImpliesValid_A	426211218	198059	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	198059	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2868091	0	0
ReadyAndValidImplyGrant_A	426211218	198059	0	0
ReqAndReadyImplyGrant_A	426211218	198059	0	0
ReqImpliesValid_A	426211218	518366	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	198059	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2868091	0	0
T1	1679	12	0	0
T2	4719	23	0	0
T3	10280	54	0	0
T7	3584	52	0	0
T8	12541	256	0	0
T9	17585	156	0	0
T10	11187	6	0	0
T11	3061	32	0	0
T12	50951	1231	0	0
T13	378518	4480	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	518366	0	0
T1	1679	13	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	273	0	0
T9	17585	157	0	0
T10	11187	2117	0	0
T11	3061	33	0	0
T12	50951	249	0	0
T13	378518	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198059	0	0
T1	1679	12	0	0
T2	4719	3	0	0
T3	10280	7	0	0
T7	3584	5	0	0
T8	12541	264	0	0
T9	17585	156	0	0
T10	11187	1061	0	0
T11	3061	32	0	0
T12	50951	175	0	0
T13	378518	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	206791	0	0
GntImpliesValid_A	426211218	206791	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	206791	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2907438	0	0
ReadyAndValidImplyGrant_A	426211218	206791	0	0
ReqAndReadyImplyGrant_A	426211218	206791	0	0
ReqImpliesValid_A	426211218	575244	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	206791	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2907438	0	0
T1	1679	13	0	0
T2	4719	91	0	0
T3	10280	49	0	0
T7	3584	30	0	0
T8	12541	200	0	0
T9	17585	130	0	0
T10	11187	1	0	0
T11	3061	42	0	0
T12	50951	1103	0	0
T13	378518	2061	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	575244	0	0
T1	1679	18	0	0
T2	4719	47	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	229	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	192	0	0
T13	378518	8	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206791	0	0
T1	1679	15	0	0
T2	4719	13	0	0
T3	10280	10	0	0
T7	3584	2	0	0
T8	12541	214	0	0
T9	17585	131	0	0
T10	11187	0	0	0
T11	3061	44	0	0
T12	50951	149	0	0
T13	378518	8	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T11 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T11,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T11,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T11,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	206802	0	0
GntImpliesValid_A	426211218	206802	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	206802	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2853392	0	0
ReadyAndValidImplyGrant_A	426211218	206802	0	0
ReqAndReadyImplyGrant_A	426211218	206802	0	0
ReqImpliesValid_A	426211218	570040	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	206802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2853392	0	0
T1	1679	11	0	0
T2	4719	42	0	0
T3	10280	82	0	0
T7	3584	66	0	0
T8	12541	197	0	0
T9	17585	137	0	0
T10	11187	1	0	0
T11	3061	39	0	0
T12	50951	1378	0	0
T13	378518	3859	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	570040	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	10	0	0
T8	12541	216	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	221	0	0
T13	378518	165	0	0
T14	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	206802	0	0
T1	1679	10	0	0
T2	4719	10	0	0
T3	10280	13	0	0
T7	3584	8	0	0
T8	12541	206	0	0
T9	17585	136	0	0
T10	11187	0	0	0
T11	3061	39	0	0
T12	50951	174	0	0
T13	378518	12	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	186350	0	0
GntImpliesValid_A	426211218	186350	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	186350	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2773767	0	0
ReadyAndValidImplyGrant_A	426211218	186350	0	0
ReqAndReadyImplyGrant_A	426211218	186350	0	0
ReqImpliesValid_A	426211218	459457	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	186350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2773767	0	0
T1	1679	11	0	0
T2	4719	57	0	0
T3	10280	108	0	0
T7	3584	42	0	0
T8	12541	197	0	0
T9	17585	165	0	0
T10	11187	1	0	0
T11	3061	32	0	0
T12	50951	1351	0	0
T13	378518	2957	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	459457	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	26	0	0
T7	3584	6	0	0
T8	12541	224	0	0
T9	17585	166	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	243	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186350	0	0
T1	1679	10	0	0
T2	4719	8	0	0
T3	10280	17	0	0
T7	3584	6	0	0
T8	12541	210	0	0
T9	17585	165	0	0
T10	11187	0	0	0
T11	3061	34	0	0
T12	50951	175	0	0
T13	378518	9	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T9 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	189465	0	0
GntImpliesValid_A	426211218	189465	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	189465	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2824558	0	0
ReadyAndValidImplyGrant_A	426211218	189465	0	0
ReqAndReadyImplyGrant_A	426211218	189465	0	0
ReqImpliesValid_A	426211218	500542	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	189465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2824558	0	0
T1	1679	13	0	0
T2	4719	44	0	0
T3	10280	63	0	0
T7	3584	27	0	0
T8	12541	173	0	0
T9	17585	139	0	0
T10	11187	1	0	0
T11	3061	38	0	0
T12	50951	1201	0	0
T13	378518	3978	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	500542	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	204	0	0
T9	17585	142	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	213	0	0
T13	378518	13	0	0
T14	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	189465	0	0
T1	1679	12	0	0
T2	4719	8	0	0
T3	10280	8	0	0
T7	3584	4	0	0
T8	12541	188	0	0
T9	17585	140	0	0
T10	11187	0	0	0
T11	3061	37	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	222637	0	0
GntImpliesValid_A	426211218	222637	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	222637	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2931271	0	0
ReadyAndValidImplyGrant_A	426211218	222637	0	0
ReqAndReadyImplyGrant_A	426211218	222637	0	0
ReqImpliesValid_A	426211218	585092	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	222637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2931271	0	0
T1	1679	6	0	0
T2	4719	116	0	0
T3	10280	67	0	0
T7	3584	86	0	0
T8	12541	208	0	0
T9	17585	168	0	0
T10	11187	75	0	0
T11	3061	50	0	0
T12	50951	1189	0	0
T13	378518	3799	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	585092	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	14	0	0
T7	3584	27	0	0
T8	12541	229	0	0
T9	17585	169	0	0
T10	11187	4218	0	0
T11	3061	57	0	0
T12	50951	227	0	0
T13	378518	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	222637	0	0
T1	1679	5	0	0
T2	4719	12	0	0
T3	10280	6	0	0
T7	3584	13	0	0
T8	12541	218	0	0
T9	17585	168	0	0
T10	11187	2146	0	0
T11	3061	53	0	0
T12	50951	155	0	0
T13	378518	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	198605	0	0
GntImpliesValid_A	426211218	198605	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	198605	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2828212	0	0
ReadyAndValidImplyGrant_A	426211218	198605	0	0
ReqAndReadyImplyGrant_A	426211218	198605	0	0
ReqImpliesValid_A	426211218	522940	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	198605	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2828212	0	0
T1	1679	9	0	0
T2	4719	40	0	0
T3	10280	116	0	0
T7	3584	61	0	0
T8	12541	232	0	0
T9	17585	158	0	0
T10	11187	1	0	0
T11	3061	41	0	0
T12	50951	1197	0	0
T13	378518	3751	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	522940	0	0
T1	1679	10	0	0
T2	4719	5	0	0
T3	10280	18	0	0
T7	3584	7	0	0
T8	12541	261	0	0
T9	17585	159	0	0
T10	11187	0	0	0
T11	3061	46	0	0
T12	50951	209	0	0
T13	378518	13	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	198605	0	0
T1	1679	9	0	0
T2	4719	5	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	158	0	0
T10	11187	0	0	0
T11	3061	43	0	0
T12	50951	164	0	0
T13	378518	13	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T9 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	186964	0	0
GntImpliesValid_A	426211218	186964	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	186964	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2871863	0	0
ReadyAndValidImplyGrant_A	426211218	186964	0	0
ReqAndReadyImplyGrant_A	426211218	186964	0	0
ReqImpliesValid_A	426211218	513203	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	186964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2871863	0	0
T1	1679	13	0	0
T2	4719	154	0	0
T3	10280	70	0	0
T7	3584	32	0	0
T8	12541	201	0	0
T9	17585	169	0	0
T10	11187	1	0	0
T11	3061	29	0	0
T12	50951	1361	0	0
T13	378518	6461	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	513203	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	232	0	0
T9	17585	170	0	0
T10	11187	0	0	0
T11	3061	36	0	0
T12	50951	207	0	0
T13	378518	19	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	186964	0	0
T1	1679	12	0	0
T2	4719	17	0	0
T3	10280	5	0	0
T7	3584	3	0	0
T8	12541	216	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	32	0	0
T12	50951	166	0	0
T13	378518	19	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	188979	0	0
GntImpliesValid_A	426211218	188979	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	188979	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2764981	0	0
ReadyAndValidImplyGrant_A	426211218	188979	0	0
ReqAndReadyImplyGrant_A	426211218	188979	0	0
ReqImpliesValid_A	426211218	459257	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	188979	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2764981	0	0
T1	1679	16	0	0
T2	4719	85	0	0
T3	10280	69	0	0
T7	3584	70	0	0
T8	12541	219	0	0
T9	17585	170	0	0
T10	11187	1	0	0
T11	3061	45	0	0
T12	50951	1343	0	0
T13	378518	3208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	459257	0	0
T1	1679	15	0	0
T2	4719	27	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	246	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	50	0	0
T12	50951	246	0	0
T13	378518	788	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	188979	0	0
T1	1679	15	0	0
T2	4719	11	0	0
T3	10280	11	0	0
T7	3584	7	0	0
T8	12541	232	0	0
T9	17585	169	0	0
T10	11187	0	0	0
T11	3061	47	0	0
T12	50951	185	0	0
T13	378518	11	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	190538	0	0
GntImpliesValid_A	426211218	190538	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	190538	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2835467	0	0
ReadyAndValidImplyGrant_A	426211218	190538	0	0
ReqAndReadyImplyGrant_A	426211218	190538	0	0
ReqImpliesValid_A	426211218	507122	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	190538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2835467	0	0
T1	1679	11	0	0
T2	4719	114	0	0
T3	10280	86	0	0
T7	3584	19	0	0
T8	12541	213	0	0
T9	17585	134	0	0
T10	11187	1	0	0
T11	3061	40	0	0
T12	50951	1348	0	0
T13	378518	4292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	507122	0	0
T1	1679	10	0	0
T2	4719	23	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	238	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	41	0	0
T12	50951	279	0	0
T13	378518	14	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	190538	0	0
T1	1679	10	0	0
T2	4719	14	0	0
T3	10280	12	0	0
T7	3584	4	0	0
T8	12541	225	0	0
T9	17585	133	0	0
T10	11187	0	0	0
T11	3061	40	0	0
T12	50951	183	0	0
T13	378518	14	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	200051	0	0
GntImpliesValid_A	426211218	200051	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	200051	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	2863164	0	0
ReadyAndValidImplyGrant_A	426211218	200051	0	0
ReqAndReadyImplyGrant_A	426211218	200051	0	0
ReqImpliesValid_A	426211218	518226	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	0	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	200051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2863164	0	0
T1	1679	15	0	0
T2	4719	59	0	0
T3	10280	136	0	0
T7	3584	77	0	0
T8	12541	227	0	0
T9	17585	160	0	0
T10	11187	1	0	0
T11	3061	27	0	0
T12	50951	1288	0	0
T13	378518	4660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	518226	0	0
T1	1679	18	0	0
T2	4719	7	0	0
T3	10280	16	0	0
T7	3584	20	0	0
T8	12541	274	0	0
T9	17585	163	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	214	0	0
T13	378518	9	0	0
T14	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	200051	0	0
T1	1679	16	0	0
T2	4719	7	0	0
T3	10280	15	0	0
T7	3584	10	0	0
T8	12541	250	0	0
T9	17585	161	0	0
T10	11187	0	0	0
T11	3061	26	0	0
T12	50951	163	0	0
T13	378518	9	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	796245	0	0
GntImpliesValid_A	426211218	796245	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	796245	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	10732868	0	0
ReadyAndValidImplyGrant_A	426211218	796245	0	0
ReqAndReadyImplyGrant_A	426211218	796245	0	0
ReqImpliesValid_A	426211218	2096593	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	14439	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	796245	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	10732868	0	0
T1	1679	1	0	0
T2	4719	271	0	0
T3	10280	412	0	0
T7	3584	128	0	0
T8	12541	1	0	0
T9	17585	1	0	0
T10	11187	1	0	0
T11	3061	1	0	0
T12	50951	3851	0	0
T13	378518	12713	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	2096593	0	0
T1	1679	57	0	0
T2	4719	47	0	0
T3	10280	103	0	0
T7	3584	35	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	1073	0	0
T13	378518	1279	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	14439	0	900
T7	3584	0	0	1
T8	12541	21	0	1
T9	17585	13	0	1
T10	11187	0	0	1
T11	3061	0	0	1
T12	50951	0	0	1
T13	378518	0	0	1
T14	1575	0	0	1
T15	4612	6	0	1
T16	0	6	0	0
T18	0	4	0	0
T19	0	30	0	0
T20	0	5	0	0
T21	0	13	0	0
T22	0	31	0	0
T23	0	1	0	0
T24	2008	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796245	0	0
T1	1679	57	0	0
T2	4719	40	0	0
T3	10280	64	0	0
T7	3584	20	0	0
T8	12541	895	0	0
T9	17585	634	0	0
T10	11187	472	0	0
T11	3061	159	0	0
T12	50951	617	0	0
T13	378518	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426211218	426089575	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426211218	796995	0	0
GntImpliesValid_A	426211218	796995	0	0
GrantKnown_A	426211218	426089575	0	0
IdxKnown_A	426211218	426089575	0	0
IndexIsCorrect_A	426211218	796995	0	0
LockArbDecision_A	426211218	0	0	0
NoReadyValidNoGrant_A	426211218	358529895	0	0
ReadyAndValidImplyGrant_A	426211218	796995	0	0
ReqAndReadyImplyGrant_A	426211218	796995	0	0
ReqImpliesValid_A	426211218	12532107	0	0
ReqStaysHighUntilGranted0_M	426211218	0	0	0
RoundRobin_A	426211218	25447	0	900
ValidKnown_A	426211218	426089575	0	0
gen_data_port_assertion.DataFlow_A	426211218	796995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	358529895	0	0
T1	1679	1	0	0
T2	4719	3817	0	0
T3	10280	8958	0	0
T7	3584	3035	0	0
T8	12541	1	0	0
T9	17585	1	0	0
T10	11187	1	0	0
T11	3061	1	0	0
T12	50951	41872	0	0
T13	378518	355673	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	12532107	0	0
T1	1679	50	0	0
T2	4719	467	0	0
T3	10280	379	0	0
T7	3584	231	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	5073	0	0
T13	378518	14556	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	25447	0	900
T7	3584	0	0	1
T8	12541	17	0	1
T9	17585	12	0	1
T10	11187	0	0	1
T11	3061	2	0	1
T12	50951	2	0	1
T13	378518	0	0	1
T14	1575	0	0	1
T15	4612	5	0	1
T16	0	4	0	0
T17	0	2	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	3	0	0
T24	2008	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	426089575	0	0
T1	1679	1668	0	0
T2	4719	4653	0	0
T3	10280	10240	0	0
T7	3584	3562	0	0
T8	12541	12504	0	0
T9	17585	17520	0	0
T10	11187	11123	0	0
T11	3061	3046	0	0
T12	50951	50932	0	0
T13	378518	378456	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426211218	796995	0	0
T1	1679	50	0	0
T2	4719	65	0	0
T3	10280	48	0	0
T7	3584	33	0	0
T8	12541	940	0	0
T9	17585	615	0	0
T10	11187	469	0	0
T11	3061	112	0	0
T12	50951	588	0	0
T13	378518	44	0	0