Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.70 100.00 100.00 98.80 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 99.26 88.94 98.80 95.88 99.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tlul_assert_device_aes 100.00 100.00 100.00 100.00
tlul_assert_device_csrng 100.00 100.00 100.00 100.00
tlul_assert_device_edn0 100.00 100.00 100.00 100.00
tlul_assert_device_edn1 100.00 100.00 100.00 100.00
tlul_assert_device_entropy_src 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__core 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__mem 100.00 100.00 100.00 100.00
tlul_assert_device_flash_ctrl__prim 100.00 100.00 100.00 100.00
tlul_assert_device_hmac 100.00 100.00 100.00 100.00
tlul_assert_device_keymgr 100.00 100.00 100.00 100.00
tlul_assert_device_kmac 100.00 100.00 100.00 100.00
tlul_assert_device_otbn 100.00 100.00 100.00 100.00
tlul_assert_device_peri 100.00 100.00 100.00 100.00
tlul_assert_device_rom_ctrl__regs 100.00 100.00 100.00 100.00
tlul_assert_device_rom_ctrl__rom 100.00 100.00 100.00 100.00
tlul_assert_device_rv_core_ibex__cfg 100.00 100.00 100.00 100.00
tlul_assert_device_rv_dm__mem 100.00 100.00 100.00 100.00
tlul_assert_device_rv_dm__regs 100.00 100.00 100.00 100.00
tlul_assert_device_rv_plic 100.00 100.00 100.00 100.00
tlul_assert_device_spi_host0 100.00 100.00 100.00 100.00
tlul_assert_device_spi_host1 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_main__ram 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_main__regs 100.00 100.00 100.00 100.00
tlul_assert_device_usbdev 100.00 100.00 100.00 100.00
tlul_assert_host_rv_core_ibex__cored 100.00 100.00 100.00 100.00
tlul_assert_host_rv_core_ibex__corei 100.00 100.00 100.00 100.00
tlul_assert_host_rv_dm__sba 100.00 100.00 100.00 100.00
u_asf_35 99.11 100.00 96.43 100.00 100.00
u_asf_37 99.11 100.00 96.43 100.00 100.00
u_asf_39 99.11 100.00 96.43 100.00 100.00
u_asf_41 99.11 100.00 96.43 100.00 100.00
u_s1n_27 99.75 100.00 99.02 100.00 100.00
u_s1n_32 99.17 100.00 96.68 100.00 100.00
u_s1n_57 97.34 99.68 91.70 97.97 100.00
u_sm1_28 93.51 98.68 85.92 92.73 96.72
u_sm1_29 92.86 98.68 85.07 92.59 95.08
u_sm1_30 98.78 100.00 98.39 100.00 96.72
u_sm1_31 92.86 98.68 85.07 92.59 95.08
u_sm1_33 92.43 98.54 84.87 92.31 94.00
u_sm1_34 92.43 98.54 84.87 92.31 94.00
u_sm1_36 96.90 100.00 93.62 100.00 94.00
u_sm1_38 96.90 100.00 93.62 100.00 94.00
u_sm1_40 96.90 100.00 93.62 100.00 94.00
u_sm1_42 96.90 100.00 93.62 100.00 94.00
u_sm1_43 92.43 98.54 84.87 92.31 94.00
u_sm1_44 92.43 98.54 84.87 92.31 94.00
u_sm1_45 92.43 98.54 84.87 92.31 94.00
u_sm1_46 92.43 98.54 84.87 92.31 94.00
u_sm1_47 92.43 98.54 84.87 92.31 94.00
u_sm1_48 92.43 98.54 84.87 92.31 94.00
u_sm1_49 92.43 98.54 84.87 92.31 94.00
u_sm1_50 92.43 98.54 84.87 92.31 94.00
u_sm1_51 92.43 98.54 84.87 92.31 94.00
u_sm1_52 92.43 98.54 84.87 92.31 94.00
u_sm1_53 92.43 98.54 84.87 92.31 94.00
u_sm1_54 92.43 98.54 84.87 92.31 94.00
u_sm1_55 92.43 98.54 84.87 92.31 94.00
u_sm1_56 92.43 98.54 84.87 92.31 94.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : xbar_main
Line No.TotalCoveredPercent
TOTAL273273100.00
CONT_ASSIGN20700
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ALWAYS68099100.00
ALWAYS7014949100.00
ALWAYS8044949100.00

206 logic unused_scanmode; 207 excluded assign unused_scanmode = ^scanmode_i; 208 209 tl_h2d_t tl_s1n_27_us_h2d ; 210 tl_d2h_t tl_s1n_27_us_d2h ; 211 212 213 tl_h2d_t tl_s1n_27_ds_h2d [4]; 214 tl_d2h_t tl_s1n_27_ds_d2h [4]; 215 216 // Create steering signal 217 logic [2:0] dev_sel_s1n_27; 218 219 220 tl_h2d_t tl_sm1_28_us_h2d [3]; 221 tl_d2h_t tl_sm1_28_us_d2h [3]; 222 223 tl_h2d_t tl_sm1_28_ds_h2d ; 224 tl_d2h_t tl_sm1_28_ds_d2h ; 225 226 227 tl_h2d_t tl_sm1_29_us_h2d [3]; 228 tl_d2h_t tl_sm1_29_us_d2h [3]; 229 230 tl_h2d_t tl_sm1_29_ds_h2d ; 231 tl_d2h_t tl_sm1_29_ds_d2h ; 232 233 234 tl_h2d_t tl_sm1_30_us_h2d [3]; 235 tl_d2h_t tl_sm1_30_us_d2h [3]; 236 237 tl_h2d_t tl_sm1_30_ds_h2d ; 238 tl_d2h_t tl_sm1_30_ds_d2h ; 239 240 241 tl_h2d_t tl_sm1_31_us_h2d [3]; 242 tl_d2h_t tl_sm1_31_us_d2h [3]; 243 244 tl_h2d_t tl_sm1_31_ds_h2d ; 245 tl_d2h_t tl_sm1_31_ds_d2h ; 246 247 tl_h2d_t tl_s1n_32_us_h2d ; 248 tl_d2h_t tl_s1n_32_us_d2h ; 249 250 251 tl_h2d_t tl_s1n_32_ds_h2d [24]; 252 tl_d2h_t tl_s1n_32_ds_d2h [24]; 253 254 // Create steering signal 255 logic [4:0] dev_sel_s1n_32; 256 257 258 tl_h2d_t tl_sm1_33_us_h2d [2]; 259 tl_d2h_t tl_sm1_33_us_d2h [2]; 260 261 tl_h2d_t tl_sm1_33_ds_h2d ; 262 tl_d2h_t tl_sm1_33_ds_d2h ; 263 264 265 tl_h2d_t tl_sm1_34_us_h2d [2]; 266 tl_d2h_t tl_sm1_34_us_d2h [2]; 267 268 tl_h2d_t tl_sm1_34_ds_h2d ; 269 tl_d2h_t tl_sm1_34_ds_d2h ; 270 271 tl_h2d_t tl_asf_35_us_h2d ; 272 tl_d2h_t tl_asf_35_us_d2h ; 273 tl_h2d_t tl_asf_35_ds_h2d ; 274 tl_d2h_t tl_asf_35_ds_d2h ; 275 276 277 tl_h2d_t tl_sm1_36_us_h2d [2]; 278 tl_d2h_t tl_sm1_36_us_d2h [2]; 279 280 tl_h2d_t tl_sm1_36_ds_h2d ; 281 tl_d2h_t tl_sm1_36_ds_d2h ; 282 283 tl_h2d_t tl_asf_37_us_h2d ; 284 tl_d2h_t tl_asf_37_us_d2h ; 285 tl_h2d_t tl_asf_37_ds_h2d ; 286 tl_d2h_t tl_asf_37_ds_d2h ; 287 288 289 tl_h2d_t tl_sm1_38_us_h2d [2]; 290 tl_d2h_t tl_sm1_38_us_d2h [2]; 291 292 tl_h2d_t tl_sm1_38_ds_h2d ; 293 tl_d2h_t tl_sm1_38_ds_d2h ; 294 295 tl_h2d_t tl_asf_39_us_h2d ; 296 tl_d2h_t tl_asf_39_us_d2h ; 297 tl_h2d_t tl_asf_39_ds_h2d ; 298 tl_d2h_t tl_asf_39_ds_d2h ; 299 300 301 tl_h2d_t tl_sm1_40_us_h2d [2]; 302 tl_d2h_t tl_sm1_40_us_d2h [2]; 303 304 tl_h2d_t tl_sm1_40_ds_h2d ; 305 tl_d2h_t tl_sm1_40_ds_d2h ; 306 307 tl_h2d_t tl_asf_41_us_h2d ; 308 tl_d2h_t tl_asf_41_us_d2h ; 309 tl_h2d_t tl_asf_41_ds_h2d ; 310 tl_d2h_t tl_asf_41_ds_d2h ; 311 312 313 tl_h2d_t tl_sm1_42_us_h2d [2]; 314 tl_d2h_t tl_sm1_42_us_d2h [2]; 315 316 tl_h2d_t tl_sm1_42_ds_h2d ; 317 tl_d2h_t tl_sm1_42_ds_d2h ; 318 319 320 tl_h2d_t tl_sm1_43_us_h2d [2]; 321 tl_d2h_t tl_sm1_43_us_d2h [2]; 322 323 tl_h2d_t tl_sm1_43_ds_h2d ; 324 tl_d2h_t tl_sm1_43_ds_d2h ; 325 326 327 tl_h2d_t tl_sm1_44_us_h2d [2]; 328 tl_d2h_t tl_sm1_44_us_d2h [2]; 329 330 tl_h2d_t tl_sm1_44_ds_h2d ; 331 tl_d2h_t tl_sm1_44_ds_d2h ; 332 333 334 tl_h2d_t tl_sm1_45_us_h2d [2]; 335 tl_d2h_t tl_sm1_45_us_d2h [2]; 336 337 tl_h2d_t tl_sm1_45_ds_h2d ; 338 tl_d2h_t tl_sm1_45_ds_d2h ; 339 340 341 tl_h2d_t tl_sm1_46_us_h2d [2]; 342 tl_d2h_t tl_sm1_46_us_d2h [2]; 343 344 tl_h2d_t tl_sm1_46_ds_h2d ; 345 tl_d2h_t tl_sm1_46_ds_d2h ; 346 347 348 tl_h2d_t tl_sm1_47_us_h2d [2]; 349 tl_d2h_t tl_sm1_47_us_d2h [2]; 350 351 tl_h2d_t tl_sm1_47_ds_h2d ; 352 tl_d2h_t tl_sm1_47_ds_d2h ; 353 354 355 tl_h2d_t tl_sm1_48_us_h2d [2]; 356 tl_d2h_t tl_sm1_48_us_d2h [2]; 357 358 tl_h2d_t tl_sm1_48_ds_h2d ; 359 tl_d2h_t tl_sm1_48_ds_d2h ; 360 361 362 tl_h2d_t tl_sm1_49_us_h2d [2]; 363 tl_d2h_t tl_sm1_49_us_d2h [2]; 364 365 tl_h2d_t tl_sm1_49_ds_h2d ; 366 tl_d2h_t tl_sm1_49_ds_d2h ; 367 368 369 tl_h2d_t tl_sm1_50_us_h2d [2]; 370 tl_d2h_t tl_sm1_50_us_d2h [2]; 371 372 tl_h2d_t tl_sm1_50_ds_h2d ; 373 tl_d2h_t tl_sm1_50_ds_d2h ; 374 375 376 tl_h2d_t tl_sm1_51_us_h2d [2]; 377 tl_d2h_t tl_sm1_51_us_d2h [2]; 378 379 tl_h2d_t tl_sm1_51_ds_h2d ; 380 tl_d2h_t tl_sm1_51_ds_d2h ; 381 382 383 tl_h2d_t tl_sm1_52_us_h2d [2]; 384 tl_d2h_t tl_sm1_52_us_d2h [2]; 385 386 tl_h2d_t tl_sm1_52_ds_h2d ; 387 tl_d2h_t tl_sm1_52_ds_d2h ; 388 389 390 tl_h2d_t tl_sm1_53_us_h2d [2]; 391 tl_d2h_t tl_sm1_53_us_d2h [2]; 392 393 tl_h2d_t tl_sm1_53_ds_h2d ; 394 tl_d2h_t tl_sm1_53_ds_d2h ; 395 396 397 tl_h2d_t tl_sm1_54_us_h2d [2]; 398 tl_d2h_t tl_sm1_54_us_d2h [2]; 399 400 tl_h2d_t tl_sm1_54_ds_h2d ; 401 tl_d2h_t tl_sm1_54_ds_d2h ; 402 403 404 tl_h2d_t tl_sm1_55_us_h2d [2]; 405 tl_d2h_t tl_sm1_55_us_d2h [2]; 406 407 tl_h2d_t tl_sm1_55_ds_h2d ; 408 tl_d2h_t tl_sm1_55_ds_d2h ; 409 410 411 tl_h2d_t tl_sm1_56_us_h2d [2]; 412 tl_d2h_t tl_sm1_56_us_d2h [2]; 413 414 tl_h2d_t tl_sm1_56_ds_h2d ; 415 tl_d2h_t tl_sm1_56_ds_d2h ; 416 417 tl_h2d_t tl_s1n_57_us_h2d ; 418 tl_d2h_t tl_s1n_57_us_d2h ; 419 420 421 tl_h2d_t tl_s1n_57_ds_h2d [24]; 422 tl_d2h_t tl_s1n_57_ds_d2h [24]; 423 424 // Create steering signal 425 logic [4:0] dev_sel_s1n_57; 426 427 428 429 1/1 assign tl_sm1_28_us_h2d[0] = tl_s1n_27_ds_h2d[0]; Tests: T1 T2 T3  430 1/1 assign tl_s1n_27_ds_d2h[0] = tl_sm1_28_us_d2h[0]; Tests: T1 T2 T3  431 432 1/1 assign tl_sm1_29_us_h2d[0] = tl_s1n_27_ds_h2d[1]; Tests: T1 T2 T3  433 1/1 assign tl_s1n_27_ds_d2h[1] = tl_sm1_29_us_d2h[0]; Tests: T1 T2 T3  434 435 1/1 assign tl_sm1_30_us_h2d[0] = tl_s1n_27_ds_h2d[2]; Tests: T1 T2 T3  436 1/1 assign tl_s1n_27_ds_d2h[2] = tl_sm1_30_us_d2h[0]; Tests: T1 T2 T3  437 438 1/1 assign tl_sm1_31_us_h2d[0] = tl_s1n_27_ds_h2d[3]; Tests: T1 T2 T3  439 1/1 assign tl_s1n_27_ds_d2h[3] = tl_sm1_31_us_d2h[0]; Tests: T1 T2 T3  440 441 1/1 assign tl_sm1_28_us_h2d[1] = tl_s1n_32_ds_h2d[0]; Tests: T1 T2 T3  442 1/1 assign tl_s1n_32_ds_d2h[0] = tl_sm1_28_us_d2h[1]; Tests: T1 T2 T3  443 444 1/1 assign tl_sm1_33_us_h2d[0] = tl_s1n_32_ds_h2d[1]; Tests: T1 T2 T3  445 1/1 assign tl_s1n_32_ds_d2h[1] = tl_sm1_33_us_d2h[0]; Tests: T1 T2 T3  446 447 1/1 assign tl_sm1_29_us_h2d[1] = tl_s1n_32_ds_h2d[2]; Tests: T1 T2 T3  448 1/1 assign tl_s1n_32_ds_d2h[2] = tl_sm1_29_us_d2h[1]; Tests: T1 T2 T3  449 450 1/1 assign tl_sm1_34_us_h2d[0] = tl_s1n_32_ds_h2d[3]; Tests: T1 T2 T3  451 1/1 assign tl_s1n_32_ds_d2h[3] = tl_sm1_34_us_d2h[0]; Tests: T1 T2 T3  452 453 1/1 assign tl_sm1_30_us_h2d[1] = tl_s1n_32_ds_h2d[4]; Tests: T1 T2 T3  454 1/1 assign tl_s1n_32_ds_d2h[4] = tl_sm1_30_us_d2h[1]; Tests: T1 T2 T3  455 456 1/1 assign tl_sm1_36_us_h2d[0] = tl_s1n_32_ds_h2d[5]; Tests: T1 T2 T3  457 1/1 assign tl_s1n_32_ds_d2h[5] = tl_sm1_36_us_d2h[0]; Tests: T1 T2 T3  458 459 1/1 assign tl_sm1_38_us_h2d[0] = tl_s1n_32_ds_h2d[6]; Tests: T1 T2 T3  460 1/1 assign tl_s1n_32_ds_d2h[6] = tl_sm1_38_us_d2h[0]; Tests: T1 T2 T3  461 462 1/1 assign tl_sm1_40_us_h2d[0] = tl_s1n_32_ds_h2d[7]; Tests: T1 T2 T3  463 1/1 assign tl_s1n_32_ds_d2h[7] = tl_sm1_40_us_d2h[0]; Tests: T1 T2 T3  464 465 1/1 assign tl_sm1_42_us_h2d[0] = tl_s1n_32_ds_h2d[8]; Tests: T1 T2 T3  466 1/1 assign tl_s1n_32_ds_d2h[8] = tl_sm1_42_us_d2h[0]; Tests: T1 T2 T3  467 468 1/1 assign tl_sm1_43_us_h2d[0] = tl_s1n_32_ds_h2d[9]; Tests: T1 T2 T3  469 1/1 assign tl_s1n_32_ds_d2h[9] = tl_sm1_43_us_d2h[0]; Tests: T1 T2 T3  470 471 1/1 assign tl_sm1_44_us_h2d[0] = tl_s1n_32_ds_h2d[10]; Tests: T1 T2 T3  472 1/1 assign tl_s1n_32_ds_d2h[10] = tl_sm1_44_us_d2h[0]; Tests: T1 T2 T3  473 474 1/1 assign tl_sm1_31_us_h2d[1] = tl_s1n_32_ds_h2d[11]; Tests: T1 T2 T3  475 1/1 assign tl_s1n_32_ds_d2h[11] = tl_sm1_31_us_d2h[1]; Tests: T1 T2 T3  476 477 1/1 assign tl_sm1_45_us_h2d[0] = tl_s1n_32_ds_h2d[12]; Tests: T1 T2 T3  478 1/1 assign tl_s1n_32_ds_d2h[12] = tl_sm1_45_us_d2h[0]; Tests: T1 T2 T3  479 480 1/1 assign tl_sm1_46_us_h2d[0] = tl_s1n_32_ds_h2d[13]; Tests: T1 T2 T3  481 1/1 assign tl_s1n_32_ds_d2h[13] = tl_sm1_46_us_d2h[0]; Tests: T1 T2 T3  482 483 1/1 assign tl_sm1_47_us_h2d[0] = tl_s1n_32_ds_h2d[14]; Tests: T1 T2 T3  484 1/1 assign tl_s1n_32_ds_d2h[14] = tl_sm1_47_us_d2h[0]; Tests: T1 T2 T3  485 486 1/1 assign tl_sm1_48_us_h2d[0] = tl_s1n_32_ds_h2d[15]; Tests: T1 T2 T3  487 1/1 assign tl_s1n_32_ds_d2h[15] = tl_sm1_48_us_d2h[0]; Tests: T1 T2 T3  488 489 1/1 assign tl_sm1_49_us_h2d[0] = tl_s1n_32_ds_h2d[16]; Tests: T1 T2 T3  490 1/1 assign tl_s1n_32_ds_d2h[16] = tl_sm1_49_us_d2h[0]; Tests: T1 T2 T3  491 492 1/1 assign tl_sm1_50_us_h2d[0] = tl_s1n_32_ds_h2d[17]; Tests: T1 T2 T3  493 1/1 assign tl_s1n_32_ds_d2h[17] = tl_sm1_50_us_d2h[0]; Tests: T1 T2 T3  494 495 1/1 assign tl_sm1_51_us_h2d[0] = tl_s1n_32_ds_h2d[18]; Tests: T1 T2 T3  496 1/1 assign tl_s1n_32_ds_d2h[18] = tl_sm1_51_us_d2h[0]; Tests: T1 T2 T3  497 498 1/1 assign tl_sm1_52_us_h2d[0] = tl_s1n_32_ds_h2d[19]; Tests: T1 T2 T3  499 1/1 assign tl_s1n_32_ds_d2h[19] = tl_sm1_52_us_d2h[0]; Tests: T1 T2 T3  500 501 1/1 assign tl_sm1_53_us_h2d[0] = tl_s1n_32_ds_h2d[20]; Tests: T1 T2 T3  502 1/1 assign tl_s1n_32_ds_d2h[20] = tl_sm1_53_us_d2h[0]; Tests: T1 T2 T3  503 504 1/1 assign tl_sm1_54_us_h2d[0] = tl_s1n_32_ds_h2d[21]; Tests: T1 T2 T3  505 1/1 assign tl_s1n_32_ds_d2h[21] = tl_sm1_54_us_d2h[0]; Tests: T1 T2 T3  506 507 1/1 assign tl_sm1_55_us_h2d[0] = tl_s1n_32_ds_h2d[22]; Tests: T1 T2 T3  508 1/1 assign tl_s1n_32_ds_d2h[22] = tl_sm1_55_us_d2h[0]; Tests: T1 T2 T3  509 510 1/1 assign tl_sm1_56_us_h2d[0] = tl_s1n_32_ds_h2d[23]; Tests: T1 T2 T3  511 1/1 assign tl_s1n_32_ds_d2h[23] = tl_sm1_56_us_d2h[0]; Tests: T1 T2 T3  512 513 1/1 assign tl_sm1_28_us_h2d[2] = tl_s1n_57_ds_h2d[0]; Tests: T1 T2 T3  514 1/1 assign tl_s1n_57_ds_d2h[0] = tl_sm1_28_us_d2h[2]; Tests: T1 T2 T3  515 516 1/1 assign tl_sm1_33_us_h2d[1] = tl_s1n_57_ds_h2d[1]; Tests: T1 T2 T3  517 1/1 assign tl_s1n_57_ds_d2h[1] = tl_sm1_33_us_d2h[1]; Tests: T1 T2 T3  518 519 1/1 assign tl_sm1_29_us_h2d[2] = tl_s1n_57_ds_h2d[2]; Tests: T1 T2 T3  520 1/1 assign tl_s1n_57_ds_d2h[2] = tl_sm1_29_us_d2h[2]; Tests: T1 T2 T3  521 522 1/1 assign tl_sm1_34_us_h2d[1] = tl_s1n_57_ds_h2d[3]; Tests: T1 T2 T3  523 1/1 assign tl_s1n_57_ds_d2h[3] = tl_sm1_34_us_d2h[1]; Tests: T1 T2 T3  524 525 1/1 assign tl_sm1_30_us_h2d[2] = tl_s1n_57_ds_h2d[4]; Tests: T1 T2 T3  526 1/1 assign tl_s1n_57_ds_d2h[4] = tl_sm1_30_us_d2h[2]; Tests: T1 T2 T3  527 528 1/1 assign tl_sm1_36_us_h2d[1] = tl_s1n_57_ds_h2d[5]; Tests: T1 T2 T3  529 1/1 assign tl_s1n_57_ds_d2h[5] = tl_sm1_36_us_d2h[1]; Tests: T1 T2 T3  530 531 1/1 assign tl_sm1_38_us_h2d[1] = tl_s1n_57_ds_h2d[6]; Tests: T1 T2 T3  532 1/1 assign tl_s1n_57_ds_d2h[6] = tl_sm1_38_us_d2h[1]; Tests: T1 T2 T3  533 534 1/1 assign tl_sm1_40_us_h2d[1] = tl_s1n_57_ds_h2d[7]; Tests: T1 T2 T3  535 1/1 assign tl_s1n_57_ds_d2h[7] = tl_sm1_40_us_d2h[1]; Tests: T1 T2 T3  536 537 1/1 assign tl_sm1_42_us_h2d[1] = tl_s1n_57_ds_h2d[8]; Tests: T1 T2 T3  538 1/1 assign tl_s1n_57_ds_d2h[8] = tl_sm1_42_us_d2h[1]; Tests: T1 T2 T3  539 540 1/1 assign tl_sm1_43_us_h2d[1] = tl_s1n_57_ds_h2d[9]; Tests: T1 T2 T3  541 1/1 assign tl_s1n_57_ds_d2h[9] = tl_sm1_43_us_d2h[1]; Tests: T1 T2 T3  542 543 1/1 assign tl_sm1_44_us_h2d[1] = tl_s1n_57_ds_h2d[10]; Tests: T1 T2 T3  544 1/1 assign tl_s1n_57_ds_d2h[10] = tl_sm1_44_us_d2h[1]; Tests: T1 T2 T3  545 546 1/1 assign tl_sm1_31_us_h2d[2] = tl_s1n_57_ds_h2d[11]; Tests: T1 T2 T3  547 1/1 assign tl_s1n_57_ds_d2h[11] = tl_sm1_31_us_d2h[2]; Tests: T1 T2 T3  548 549 1/1 assign tl_sm1_45_us_h2d[1] = tl_s1n_57_ds_h2d[12]; Tests: T1 T2 T3  550 1/1 assign tl_s1n_57_ds_d2h[12] = tl_sm1_45_us_d2h[1]; Tests: T1 T2 T3  551 552 1/1 assign tl_sm1_46_us_h2d[1] = tl_s1n_57_ds_h2d[13]; Tests: T1 T2 T3  553 1/1 assign tl_s1n_57_ds_d2h[13] = tl_sm1_46_us_d2h[1]; Tests: T1 T2 T3  554 555 1/1 assign tl_sm1_47_us_h2d[1] = tl_s1n_57_ds_h2d[14]; Tests: T1 T2 T3  556 1/1 assign tl_s1n_57_ds_d2h[14] = tl_sm1_47_us_d2h[1]; Tests: T1 T2 T3  557 558 1/1 assign tl_sm1_48_us_h2d[1] = tl_s1n_57_ds_h2d[15]; Tests: T1 T2 T3  559 1/1 assign tl_s1n_57_ds_d2h[15] = tl_sm1_48_us_d2h[1]; Tests: T1 T2 T3  560 561 1/1 assign tl_sm1_49_us_h2d[1] = tl_s1n_57_ds_h2d[16]; Tests: T1 T2 T3  562 1/1 assign tl_s1n_57_ds_d2h[16] = tl_sm1_49_us_d2h[1]; Tests: T1 T2 T3  563 564 1/1 assign tl_sm1_50_us_h2d[1] = tl_s1n_57_ds_h2d[17]; Tests: T1 T2 T3  565 1/1 assign tl_s1n_57_ds_d2h[17] = tl_sm1_50_us_d2h[1]; Tests: T1 T2 T3  566 567 1/1 assign tl_sm1_51_us_h2d[1] = tl_s1n_57_ds_h2d[18]; Tests: T1 T2 T3  568 1/1 assign tl_s1n_57_ds_d2h[18] = tl_sm1_51_us_d2h[1]; Tests: T1 T2 T3  569 570 1/1 assign tl_sm1_52_us_h2d[1] = tl_s1n_57_ds_h2d[19]; Tests: T1 T2 T3  571 1/1 assign tl_s1n_57_ds_d2h[19] = tl_sm1_52_us_d2h[1]; Tests: T1 T2 T3  572 573 1/1 assign tl_sm1_53_us_h2d[1] = tl_s1n_57_ds_h2d[20]; Tests: T1 T2 T3  574 1/1 assign tl_s1n_57_ds_d2h[20] = tl_sm1_53_us_d2h[1]; Tests: T1 T2 T3  575 576 1/1 assign tl_sm1_54_us_h2d[1] = tl_s1n_57_ds_h2d[21]; Tests: T1 T2 T3  577 1/1 assign tl_s1n_57_ds_d2h[21] = tl_sm1_54_us_d2h[1]; Tests: T1 T2 T3  578 579 1/1 assign tl_sm1_55_us_h2d[1] = tl_s1n_57_ds_h2d[22]; Tests: T1 T2 T3  580 1/1 assign tl_s1n_57_ds_d2h[22] = tl_sm1_55_us_d2h[1]; Tests: T1 T2 T3  581 582 1/1 assign tl_sm1_56_us_h2d[1] = tl_s1n_57_ds_h2d[23]; Tests: T1 T2 T3  583 1/1 assign tl_s1n_57_ds_d2h[23] = tl_sm1_56_us_d2h[1]; Tests: T1 T2 T3  584 585 1/1 assign tl_s1n_27_us_h2d = tl_rv_core_ibex__corei_i; Tests: T1 T2 T3  586 1/1 assign tl_rv_core_ibex__corei_o = tl_s1n_27_us_d2h; Tests: T1 T2 T3  587 588 1/1 assign tl_rom_ctrl__rom_o = tl_sm1_28_ds_h2d; Tests: T1 T2 T3  589 1/1 assign tl_sm1_28_ds_d2h = tl_rom_ctrl__rom_i; Tests: T1 T2 T3  590 591 1/1 assign tl_rv_dm__mem_o = tl_sm1_29_ds_h2d; Tests: T1 T2 T3  592 1/1 assign tl_sm1_29_ds_d2h = tl_rv_dm__mem_i; Tests: T1 T2 T3  593 594 1/1 assign tl_sram_ctrl_main__ram_o = tl_sm1_30_ds_h2d; Tests: T1 T2 T3  595 1/1 assign tl_sm1_30_ds_d2h = tl_sram_ctrl_main__ram_i; Tests: T1 T2 T3  596 597 1/1 assign tl_flash_ctrl__mem_o = tl_sm1_31_ds_h2d; Tests: T1 T2 T3  598 1/1 assign tl_sm1_31_ds_d2h = tl_flash_ctrl__mem_i; Tests: T1 T2 T3  599 600 1/1 assign tl_s1n_32_us_h2d = tl_rv_core_ibex__cored_i; Tests: T1 T2 T3  601 1/1 assign tl_rv_core_ibex__cored_o = tl_s1n_32_us_d2h; Tests: T1 T2 T3  602 603 1/1 assign tl_rom_ctrl__regs_o = tl_sm1_33_ds_h2d; Tests: T1 T2 T3  604 1/1 assign tl_sm1_33_ds_d2h = tl_rom_ctrl__regs_i; Tests: T1 T2 T3  605 606 1/1 assign tl_rv_dm__regs_o = tl_sm1_34_ds_h2d; Tests: T1 T2 T3  607 1/1 assign tl_sm1_34_ds_d2h = tl_rv_dm__regs_i; Tests: T1 T2 T3  608 609 1/1 assign tl_peri_o = tl_asf_35_ds_h2d; Tests: T1 T2 T3  610 1/1 assign tl_asf_35_ds_d2h = tl_peri_i; Tests: T1 T2 T3  611 612 1/1 assign tl_asf_35_us_h2d = tl_sm1_36_ds_h2d; Tests: T1 T2 T3  613 1/1 assign tl_sm1_36_ds_d2h = tl_asf_35_us_d2h; Tests: T1 T2 T3  614 615 1/1 assign tl_spi_host0_o = tl_asf_37_ds_h2d; Tests: T1 T2 T3  616 1/1 assign tl_asf_37_ds_d2h = tl_spi_host0_i; Tests: T1 T2 T3  617 618 1/1 assign tl_asf_37_us_h2d = tl_sm1_38_ds_h2d; Tests: T1 T2 T3  619 1/1 assign tl_sm1_38_ds_d2h = tl_asf_37_us_d2h; Tests: T1 T2 T3  620 621 1/1 assign tl_spi_host1_o = tl_asf_39_ds_h2d; Tests: T1 T2 T3  622 1/1 assign tl_asf_39_ds_d2h = tl_spi_host1_i; Tests: T1 T2 T3  623 624 1/1 assign tl_asf_39_us_h2d = tl_sm1_40_ds_h2d; Tests: T1 T2 T3  625 1/1 assign tl_sm1_40_ds_d2h = tl_asf_39_us_d2h; Tests: T1 T2 T3  626 627 1/1 assign tl_usbdev_o = tl_asf_41_ds_h2d; Tests: T1 T2 T3  628 1/1 assign tl_asf_41_ds_d2h = tl_usbdev_i; Tests: T1 T2 T3  629 630 1/1 assign tl_asf_41_us_h2d = tl_sm1_42_ds_h2d; Tests: T1 T2 T3  631 1/1 assign tl_sm1_42_ds_d2h = tl_asf_41_us_d2h; Tests: T1 T2 T3  632 633 1/1 assign tl_flash_ctrl__core_o = tl_sm1_43_ds_h2d; Tests: T1 T2 T3  634 1/1 assign tl_sm1_43_ds_d2h = tl_flash_ctrl__core_i; Tests: T1 T2 T3  635 636 1/1 assign tl_flash_ctrl__prim_o = tl_sm1_44_ds_h2d; Tests: T1 T2 T3  637 1/1 assign tl_sm1_44_ds_d2h = tl_flash_ctrl__prim_i; Tests: T1 T2 T3  638 639 1/1 assign tl_aes_o = tl_sm1_45_ds_h2d; Tests: T1 T2 T3  640 1/1 assign tl_sm1_45_ds_d2h = tl_aes_i; Tests: T1 T2 T3  641 642 1/1 assign tl_entropy_src_o = tl_sm1_46_ds_h2d; Tests: T1 T2 T3  643 1/1 assign tl_sm1_46_ds_d2h = tl_entropy_src_i; Tests: T1 T2 T3  644 645 1/1 assign tl_csrng_o = tl_sm1_47_ds_h2d; Tests: T1 T2 T3  646 1/1 assign tl_sm1_47_ds_d2h = tl_csrng_i; Tests: T1 T2 T3  647 648 1/1 assign tl_edn0_o = tl_sm1_48_ds_h2d; Tests: T1 T2 T3  649 1/1 assign tl_sm1_48_ds_d2h = tl_edn0_i; Tests: T1 T2 T3  650 651 1/1 assign tl_edn1_o = tl_sm1_49_ds_h2d; Tests: T1 T2 T3  652 1/1 assign tl_sm1_49_ds_d2h = tl_edn1_i; Tests: T1 T2 T3  653 654 1/1 assign tl_hmac_o = tl_sm1_50_ds_h2d; Tests: T1 T2 T3  655 1/1 assign tl_sm1_50_ds_d2h = tl_hmac_i; Tests: T1 T2 T3  656 657 1/1 assign tl_rv_plic_o = tl_sm1_51_ds_h2d; Tests: T1 T2 T3  658 1/1 assign tl_sm1_51_ds_d2h = tl_rv_plic_i; Tests: T1 T2 T3  659 660 1/1 assign tl_otbn_o = tl_sm1_52_ds_h2d; Tests: T1 T2 T3  661 1/1 assign tl_sm1_52_ds_d2h = tl_otbn_i; Tests: T1 T2 T3  662 663 1/1 assign tl_keymgr_o = tl_sm1_53_ds_h2d; Tests: T1 T2 T3  664 1/1 assign tl_sm1_53_ds_d2h = tl_keymgr_i; Tests: T1 T2 T3  665 666 1/1 assign tl_kmac_o = tl_sm1_54_ds_h2d; Tests: T1 T2 T3  667 1/1 assign tl_sm1_54_ds_d2h = tl_kmac_i; Tests: T1 T2 T3  668 669 1/1 assign tl_sram_ctrl_main__regs_o = tl_sm1_55_ds_h2d; Tests: T1 T2 T3  670 1/1 assign tl_sm1_55_ds_d2h = tl_sram_ctrl_main__regs_i; Tests: T1 T2 T3  671 672 1/1 assign tl_rv_core_ibex__cfg_o = tl_sm1_56_ds_h2d; Tests: T1 T2 T3  673 1/1 assign tl_sm1_56_ds_d2h = tl_rv_core_ibex__cfg_i; Tests: T1 T2 T3  674 675 1/1 assign tl_s1n_57_us_h2d = tl_rv_dm__sba_i; Tests: T1 T2 T3  676 1/1 assign tl_rv_dm__sba_o = tl_s1n_57_us_d2h; Tests: T1 T2 T3  677 678 always_comb begin 679 // default steering to generate error response if address is not within the range 680 1/1 dev_sel_s1n_27 = 3'd4; Tests: T1 T2 T3  681 1/1 if ((tl_s1n_27_us_h2d.a_address & Tests: T1 T2 T3  682 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 683 1/1 dev_sel_s1n_27 = 3'd0; Tests: T1 T2 T3  684 685 1/1 end else if ((tl_s1n_27_us_h2d.a_address & Tests: T1 T2 T3  686 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 687 1/1 dev_sel_s1n_27 = 3'd1; Tests: T1 T2 T3  688 689 1/1 end else if ((tl_s1n_27_us_h2d.a_address & Tests: T1 T2 T3  690 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 691 1/1 dev_sel_s1n_27 = 3'd2; Tests: T1 T2 T3  692 693 1/1 end else if ((tl_s1n_27_us_h2d.a_address & Tests: T1 T2 T3  694 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 695 1/1 dev_sel_s1n_27 = 3'd3; Tests: T1 T2 T3  696 end MISSING_ELSE 697 end 698 699 always_comb begin 700 // default steering to generate error response if address is not within the range 701 1/1 dev_sel_s1n_32 = 5'd24; Tests: T1 T2 T3  702 1/1 if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  703 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 704 1/1 dev_sel_s1n_32 = 5'd0; Tests: T1 T2 T3  705 706 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  707 ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin 708 1/1 dev_sel_s1n_32 = 5'd1; Tests: T1 T2 T3  709 710 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  711 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 712 1/1 dev_sel_s1n_32 = 5'd2; Tests: T1 T2 T3  713 714 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  715 ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin 716 1/1 dev_sel_s1n_32 = 5'd3; Tests: T1 T2 T3  717 718 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  719 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 720 1/1 dev_sel_s1n_32 = 5'd4; Tests: T1 T2 T3  721 722 1/1 end else if ( Tests: T1 T2 T3  723 ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || 724 ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) 725 ) begin 726 1/1 dev_sel_s1n_32 = 5'd5; Tests: T1 T2 T3  727 728 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  729 ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin 730 1/1 dev_sel_s1n_32 = 5'd6; Tests: T1 T2 T3  731 732 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  733 ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin 734 1/1 dev_sel_s1n_32 = 5'd7; Tests: T1 T2 T3  735 736 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  737 ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin 738 1/1 dev_sel_s1n_32 = 5'd8; Tests: T1 T2 T3  739 740 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  741 ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin 742 1/1 dev_sel_s1n_32 = 5'd9; Tests: T1 T2 T3  743 744 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  745 ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin 746 1/1 dev_sel_s1n_32 = 5'd10; Tests: T1 T2 T3  747 748 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  749 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 750 1/1 dev_sel_s1n_32 = 5'd11; Tests: T1 T2 T3  751 752 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  753 ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin 754 1/1 dev_sel_s1n_32 = 5'd12; Tests: T1 T2 T3  755 756 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  757 ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin 758 1/1 dev_sel_s1n_32 = 5'd13; Tests: T1 T2 T3  759 760 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  761 ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin 762 1/1 dev_sel_s1n_32 = 5'd14; Tests: T1 T2 T3  763 764 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  765 ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin 766 1/1 dev_sel_s1n_32 = 5'd15; Tests: T1 T2 T3  767 768 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  769 ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin 770 1/1 dev_sel_s1n_32 = 5'd16; Tests: T1 T2 T3  771 772 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  773 ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin 774 1/1 dev_sel_s1n_32 = 5'd17; Tests: T1 T2 T3  775 776 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  777 ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin 778 1/1 dev_sel_s1n_32 = 5'd18; Tests: T1 T2 T3  779 780 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  781 ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin 782 1/1 dev_sel_s1n_32 = 5'd19; Tests: T1 T2 T3  783 784 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  785 ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin 786 1/1 dev_sel_s1n_32 = 5'd20; Tests: T1 T2 T3  787 788 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  789 ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin 790 1/1 dev_sel_s1n_32 = 5'd21; Tests: T1 T2 T3  791 792 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  793 ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin 794 1/1 dev_sel_s1n_32 = 5'd22; Tests: T1 T2 T3  795 796 1/1 end else if ((tl_s1n_32_us_h2d.a_address & Tests: T1 T2 T3  797 ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin 798 1/1 dev_sel_s1n_32 = 5'd23; Tests: T1 T2 T3  799 end MISSING_ELSE 800 end 801 802 always_comb begin 803 // default steering to generate error response if address is not within the range 804 1/1 dev_sel_s1n_57 = 5'd24; Tests: T1 T2 T3  805 1/1 if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  806 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 807 1/1 dev_sel_s1n_57 = 5'd0; Tests: T1 T2 T3  808 809 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  810 ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin 811 1/1 dev_sel_s1n_57 = 5'd1; Tests: T1 T2 T3  812 813 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  814 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 815 1/1 dev_sel_s1n_57 = 5'd2; Tests: T1 T2 T3  816 817 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  818 ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin 819 1/1 dev_sel_s1n_57 = 5'd3; Tests: T1 T2 T3  820 821 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  822 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 823 1/1 dev_sel_s1n_57 = 5'd4; Tests: T1 T2 T3  824 825 1/1 end else if ( Tests: T1 T2 T3  826 ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || 827 ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) 828 ) begin 829 1/1 dev_sel_s1n_57 = 5'd5; Tests: T1 T2 T3  830 831 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  832 ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin 833 1/1 dev_sel_s1n_57 = 5'd6; Tests: T1 T2 T3  834 835 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  836 ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin 837 1/1 dev_sel_s1n_57 = 5'd7; Tests: T1 T2 T3  838 839 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  840 ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin 841 1/1 dev_sel_s1n_57 = 5'd8; Tests: T1 T2 T3  842 843 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  844 ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin 845 1/1 dev_sel_s1n_57 = 5'd9; Tests: T1 T2 T3  846 847 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  848 ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin 849 1/1 dev_sel_s1n_57 = 5'd10; Tests: T1 T2 T3  850 851 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  852 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 853 1/1 dev_sel_s1n_57 = 5'd11; Tests: T1 T2 T3  854 855 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  856 ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin 857 1/1 dev_sel_s1n_57 = 5'd12; Tests: T1 T2 T3  858 859 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  860 ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin 861 1/1 dev_sel_s1n_57 = 5'd13; Tests: T1 T2 T3  862 863 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  864 ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin 865 1/1 dev_sel_s1n_57 = 5'd14; Tests: T1 T2 T3  866 867 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  868 ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin 869 1/1 dev_sel_s1n_57 = 5'd15; Tests: T1 T2 T3  870 871 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  872 ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin 873 1/1 dev_sel_s1n_57 = 5'd16; Tests: T1 T2 T3  874 875 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  876 ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin 877 1/1 dev_sel_s1n_57 = 5'd17; Tests: T1 T2 T3  878 879 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  880 ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin 881 1/1 dev_sel_s1n_57 = 5'd18; Tests: T1 T2 T3  882 883 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  884 ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin 885 1/1 dev_sel_s1n_57 = 5'd19; Tests: T1 T2 T3  886 887 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  888 ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin 889 1/1 dev_sel_s1n_57 = 5'd20; Tests: T1 T2 T3  890 891 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  892 ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin 893 1/1 dev_sel_s1n_57 = 5'd21; Tests: T1 T2 T3  894 895 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  896 ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin 897 1/1 dev_sel_s1n_57 = 5'd22; Tests: T1 T2 T3  898 899 1/1 end else if ((tl_s1n_57_us_h2d.a_address & Tests: T1 T2 T3  900 ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin 901 1/1 dev_sel_s1n_57 = 5'd23; Tests: T1 T2 T3  902 end MISSING_ELSE

Cond Coverage for Module : xbar_main
TotalCoveredPercent
Conditions114114100.00
Logical114114100.00
Non-Logical00
Event00

 LINE       681
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       685
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       689
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       693
 EXPRESSION ((tl_s1n_27_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       702
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       706
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       710
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       714
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       718
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       722
 EXPRESSION 
 Number  Term
      1  ((tl_s1n_32_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || 
      2  ((tl_s1n_32_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T8
10CoveredT1,T2,T3

 LINE       722
 SUB-EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       722
 SUB-EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

 LINE       728
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       732
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       736
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       740
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       744
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       748
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       752
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       756
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       760
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       764
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       768
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       772
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       776
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       780
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       784
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       788
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       792
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)
            ---------------------------------------------------------------1---------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       796
 EXPRESSION ((tl_s1n_32_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG)
            ------------------------------------------------------------1------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       805
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__ROM)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__ROM)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       809
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ROM_CTRL__REGS)) == tl_main_pkg::ADDR_SPACE_ROM_CTRL__REGS)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       813
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__MEM)) == tl_main_pkg::ADDR_SPACE_RV_DM__MEM)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       817
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_DM__REGS)) == tl_main_pkg::ADDR_SPACE_RV_DM__REGS)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       821
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__RAM)
            --------------------------------------------------------------1--------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       825
 EXPRESSION 
 Number  Term
      1  ((tl_s1n_57_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000) || 
      2  ((tl_s1n_57_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T8

 LINE       825
 SUB-EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~32'b00000000000111111111111111111111)) == 32'b01000000000000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T8

 LINE       825
 SUB-EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~32'b00000000001111111111111111111111)) == 32'b01000000010000000000000000000000)
                --------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       831
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST0)) == tl_main_pkg::ADDR_SPACE_SPI_HOST0)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       835
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SPI_HOST1)) == tl_main_pkg::ADDR_SPACE_SPI_HOST1)
            ----------------------------------------------------1----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       839
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_USBDEV)) == tl_main_pkg::ADDR_SPACE_USBDEV)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       843
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__CORE)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__CORE)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       847
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__PRIM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__PRIM)
            -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       851
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_FLASH_CTRL__MEM)) == tl_main_pkg::ADDR_SPACE_FLASH_CTRL__MEM)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       855
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_AES)) == tl_main_pkg::ADDR_SPACE_AES)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       859
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_ENTROPY_SRC)) == tl_main_pkg::ADDR_SPACE_ENTROPY_SRC)
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       863
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_CSRNG)) == tl_main_pkg::ADDR_SPACE_CSRNG)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       867
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN0)) == tl_main_pkg::ADDR_SPACE_EDN0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       871
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_EDN1)) == tl_main_pkg::ADDR_SPACE_EDN1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       875
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_HMAC)) == tl_main_pkg::ADDR_SPACE_HMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       879
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_PLIC)) == tl_main_pkg::ADDR_SPACE_RV_PLIC)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       883
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_OTBN)) == tl_main_pkg::ADDR_SPACE_OTBN)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       887
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KEYMGR)) == tl_main_pkg::ADDR_SPACE_KEYMGR)
            -------------------------------------------------1-------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       891
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_KMAC)) == tl_main_pkg::ADDR_SPACE_KMAC)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       895
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == tl_main_pkg::ADDR_SPACE_SRAM_CTRL_MAIN__REGS)
            ---------------------------------------------------------------1---------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       899
 EXPRESSION ((tl_s1n_57_us_h2d.a_address & (~tl_main_pkg::ADDR_MASK_RV_CORE_IBEX__CFG)) == tl_main_pkg::ADDR_SPACE_RV_CORE_IBEX__CFG)
            ------------------------------------------------------------1------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 604 580 96.03
Total Bits 7984 7888 98.80
Total Bits 0->1 3992 3944 98.80
Total Bits 1->0 3992 3944 98.80

Ports 604 580 96.03
Port Bits 7984 7888 98.80
Port Bits 0->1 3992 3944 98.80
Port Bits 1->0 3992 3944 98.80

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T19,T22,T56 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T19,T22,T56 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T19,T22,T56 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T19,T22,T56 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T19,T22,T56 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] Yes Yes T1,T10,T11 Yes T10,T11,T7 INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Yes Yes T1,T10,T11 Yes T1,T10,T11 INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0] Yes Yes T1,T3,T10 Yes T1,T3,T10 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Yes Yes T3,T10,T11 Yes T3,T10,T11 INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[20:4] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[21] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[23:22] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[15:12] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_address[31:17] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:16] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[20:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T8 Yes T2,T3,T8 INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T2,T3,T8 Yes T2,T3,T8 INPUT
tl_rom_ctrl__regs_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_peri_o.a_user.rsvd[4:3] No No No OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[22:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:3] No No No OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[19:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_source[5:0] Yes Yes T2,T3,T8 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T2,*T3,*T8 Yes T2,T3,T8 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:3] No No No OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[19:17] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_error Yes Yes T1,T3,T8 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_usbdev_o.a_user.rsvd[4:3] No No No OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[11:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_usbdev_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[21:20] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[29:22] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[1:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[1:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[8:0] Yes Yes T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[23:9] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[5:0] Yes Yes T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T3,T8 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_sink Yes Yes T1,T3,T8 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[14:7] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[15] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[23:16] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:3] No No No OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[19:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[28:20] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_address[29] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:30] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_hmac_o.a_user.rsvd[4:3] No No No OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[12:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_hmac_o.a_address[15:13] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[19:17] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_hmac_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_hmac_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_hmac_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T1,*T2,*T8 Yes T1,T2,T3 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_kmac_o.a_user.rsvd[4:3] No No No OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_kmac_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_kmac_i.d_error Yes Yes T2,T3,T8 Yes T2,T3,T8 INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_aes_o.a_user.rsvd[4:3] No No No OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
tl_aes_o.a_address[7:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_aes_o.a_address[19:8] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[2:0] Yes Yes T2,T3,T8 Yes T2,T3,T8 OUTPUT
tl_aes_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aes_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_aes_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:3] No No No OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_entropy_src_o.a_address[7:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_entropy_src_o.a_address[16:8] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[5:0] Yes Yes T1,*T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[2:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error Yes Yes T1,T2,T8 Yes T1,T3,T8 INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T8 INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_csrng_o.a_user.rsvd[4:3] No No No OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_source[5:0] Yes Yes T2,T3,T8 Yes T1,T2,T3 INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_edn0_o.a_user.rsvd[4:3] No No No OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[5:0] Yes Yes *T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_edn1_o.a_user.rsvd[4:3] No No No OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[18:7] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[20:19] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn1_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_edn1_i.d_error Yes Yes T1,T3,T8 Yes T1,T2,T3 INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T3,T8 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T2,T3,T8 Yes T2,T3,T8 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
tl_rv_plic_o.a_address[27:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_address[29:28] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_otbn_o.a_user.rsvd[4:3] No No No OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_address[17:0] Yes Yes *T2,T3,T8 Yes T2,T3,T8 OUTPUT
tl_otbn_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[2:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 OUTPUT
tl_otbn_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otbn_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_otbn_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T8 INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_keymgr_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_keymgr_o.a_user.rsvd[4:3] No No No OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_address[7:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
tl_keymgr_o.a_address[17:8] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[5:0] Yes Yes T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_keymgr_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_error Yes Yes T1,T2,T8 Yes T1,T2,T8 INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_source[5:0] Yes Yes T2,T8,T9 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T8 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:3] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[15:8] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[20:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T1,T2,T8 Yes T1,T2,T8 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:3] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[17:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[23:21] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[29:25] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0] Yes Yes T2,T3,T8 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[2:0] Yes Yes T7,T12,T26 Yes T7,T12,T26 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:3] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[16:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[27:17] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:29] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T2,T3,T7 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : xbar_main
Line No.TotalCoveredPercent
Branches 55 55 100.00
IF 681 5 5 100.00
IF 702 25 25 100.00
IF 805 25 25 100.00


681 if ((tl_s1n_27_us_h2d.a_address & -1- 682 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 683 dev_sel_s1n_27 = 3'd0; ==> 684 685 end else if ((tl_s1n_27_us_h2d.a_address & -2- 686 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 687 dev_sel_s1n_27 = 3'd1; ==> 688 689 end else if ((tl_s1n_27_us_h2d.a_address & -3- 690 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 691 dev_sel_s1n_27 = 3'd2; ==> 692 693 end else if ((tl_s1n_27_us_h2d.a_address & -4- 694 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 695 dev_sel_s1n_27 = 3'd3; ==> 696 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


702 if ((tl_s1n_32_us_h2d.a_address & -1- 703 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 704 dev_sel_s1n_32 = 5'd0; ==> 705 706 end else if ((tl_s1n_32_us_h2d.a_address & -2- 707 ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin 708 dev_sel_s1n_32 = 5'd1; ==> 709 710 end else if ((tl_s1n_32_us_h2d.a_address & -3- 711 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 712 dev_sel_s1n_32 = 5'd2; ==> 713 714 end else if ((tl_s1n_32_us_h2d.a_address & -4- 715 ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin 716 dev_sel_s1n_32 = 5'd3; ==> 717 718 end else if ((tl_s1n_32_us_h2d.a_address & -5- 719 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 720 dev_sel_s1n_32 = 5'd4; ==> 721 722 end else if ( -6- 723 ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || 724 ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) 725 ) begin 726 dev_sel_s1n_32 = 5'd5; ==> 727 728 end else if ((tl_s1n_32_us_h2d.a_address & -7- 729 ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin 730 dev_sel_s1n_32 = 5'd6; ==> 731 732 end else if ((tl_s1n_32_us_h2d.a_address & -8- 733 ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin 734 dev_sel_s1n_32 = 5'd7; ==> 735 736 end else if ((tl_s1n_32_us_h2d.a_address & -9- 737 ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin 738 dev_sel_s1n_32 = 5'd8; ==> 739 740 end else if ((tl_s1n_32_us_h2d.a_address & -10- 741 ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin 742 dev_sel_s1n_32 = 5'd9; ==> 743 744 end else if ((tl_s1n_32_us_h2d.a_address & -11- 745 ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin 746 dev_sel_s1n_32 = 5'd10; ==> 747 748 end else if ((tl_s1n_32_us_h2d.a_address & -12- 749 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 750 dev_sel_s1n_32 = 5'd11; ==> 751 752 end else if ((tl_s1n_32_us_h2d.a_address & -13- 753 ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin 754 dev_sel_s1n_32 = 5'd12; ==> 755 756 end else if ((tl_s1n_32_us_h2d.a_address & -14- 757 ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin 758 dev_sel_s1n_32 = 5'd13; ==> 759 760 end else if ((tl_s1n_32_us_h2d.a_address & -15- 761 ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin 762 dev_sel_s1n_32 = 5'd14; ==> 763 764 end else if ((tl_s1n_32_us_h2d.a_address & -16- 765 ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin 766 dev_sel_s1n_32 = 5'd15; ==> 767 768 end else if ((tl_s1n_32_us_h2d.a_address & -17- 769 ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin 770 dev_sel_s1n_32 = 5'd16; ==> 771 772 end else if ((tl_s1n_32_us_h2d.a_address & -18- 773 ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin 774 dev_sel_s1n_32 = 5'd17; ==> 775 776 end else if ((tl_s1n_32_us_h2d.a_address & -19- 777 ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin 778 dev_sel_s1n_32 = 5'd18; ==> 779 780 end else if ((tl_s1n_32_us_h2d.a_address & -20- 781 ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin 782 dev_sel_s1n_32 = 5'd19; ==> 783 784 end else if ((tl_s1n_32_us_h2d.a_address & -21- 785 ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin 786 dev_sel_s1n_32 = 5'd20; ==> 787 788 end else if ((tl_s1n_32_us_h2d.a_address & -22- 789 ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin 790 dev_sel_s1n_32 = 5'd21; ==> 791 792 end else if ((tl_s1n_32_us_h2d.a_address & -23- 793 ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin 794 dev_sel_s1n_32 = 5'd22; ==> 795 796 end else if ((tl_s1n_32_us_h2d.a_address & -24- 797 ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin 798 dev_sel_s1n_32 = 5'd23; ==> 799 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3


805 if ((tl_s1n_57_us_h2d.a_address & -1- 806 ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin 807 dev_sel_s1n_57 = 5'd0; ==> 808 809 end else if ((tl_s1n_57_us_h2d.a_address & -2- 810 ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin 811 dev_sel_s1n_57 = 5'd1; ==> 812 813 end else if ((tl_s1n_57_us_h2d.a_address & -3- 814 ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin 815 dev_sel_s1n_57 = 5'd2; ==> 816 817 end else if ((tl_s1n_57_us_h2d.a_address & -4- 818 ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin 819 dev_sel_s1n_57 = 5'd3; ==> 820 821 end else if ((tl_s1n_57_us_h2d.a_address & -5- 822 ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin 823 dev_sel_s1n_57 = 5'd4; ==> 824 825 end else if ( -6- 826 ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || 827 ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) 828 ) begin 829 dev_sel_s1n_57 = 5'd5; ==> 830 831 end else if ((tl_s1n_57_us_h2d.a_address & -7- 832 ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin 833 dev_sel_s1n_57 = 5'd6; ==> 834 835 end else if ((tl_s1n_57_us_h2d.a_address & -8- 836 ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin 837 dev_sel_s1n_57 = 5'd7; ==> 838 839 end else if ((tl_s1n_57_us_h2d.a_address & -9- 840 ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin 841 dev_sel_s1n_57 = 5'd8; ==> 842 843 end else if ((tl_s1n_57_us_h2d.a_address & -10- 844 ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin 845 dev_sel_s1n_57 = 5'd9; ==> 846 847 end else if ((tl_s1n_57_us_h2d.a_address & -11- 848 ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin 849 dev_sel_s1n_57 = 5'd10; ==> 850 851 end else if ((tl_s1n_57_us_h2d.a_address & -12- 852 ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin 853 dev_sel_s1n_57 = 5'd11; ==> 854 855 end else if ((tl_s1n_57_us_h2d.a_address & -13- 856 ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin 857 dev_sel_s1n_57 = 5'd12; ==> 858 859 end else if ((tl_s1n_57_us_h2d.a_address & -14- 860 ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin 861 dev_sel_s1n_57 = 5'd13; ==> 862 863 end else if ((tl_s1n_57_us_h2d.a_address & -15- 864 ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin 865 dev_sel_s1n_57 = 5'd14; ==> 866 867 end else if ((tl_s1n_57_us_h2d.a_address & -16- 868 ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin 869 dev_sel_s1n_57 = 5'd15; ==> 870 871 end else if ((tl_s1n_57_us_h2d.a_address & -17- 872 ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin 873 dev_sel_s1n_57 = 5'd16; ==> 874 875 end else if ((tl_s1n_57_us_h2d.a_address & -18- 876 ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin 877 dev_sel_s1n_57 = 5'd17; ==> 878 879 end else if ((tl_s1n_57_us_h2d.a_address & -19- 880 ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin 881 dev_sel_s1n_57 = 5'd18; ==> 882 883 end else if ((tl_s1n_57_us_h2d.a_address & -20- 884 ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin 885 dev_sel_s1n_57 = 5'd19; ==> 886 887 end else if ((tl_s1n_57_us_h2d.a_address & -21- 888 ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin 889 dev_sel_s1n_57 = 5'd20; ==> 890 891 end else if ((tl_s1n_57_us_h2d.a_address & -22- 892 ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin 893 dev_sel_s1n_57 = 5'd21; ==> 894 895 end else if ((tl_s1n_57_us_h2d.a_address & -23- 896 ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin 897 dev_sel_s1n_57 = 5'd22; ==> 898 899 end else if ((tl_s1n_57_us_h2d.a_address & -24- 900 ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin 901 dev_sel_s1n_57 = 5'd23; ==> 902 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3

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