Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2142866 1 T1 111 T2 104 T3 368
values[2] 150289 1 T1 3 T2 3 T3 33
values[3] 33484 1 T7 2 T8 5 T11 5
values[4] 20642 1 T15 131 T86 2 T109 1
values[5] 14852 1 T15 94 T86 1 T109 1
values[6] 11469 1 T15 62 T86 1 T82 216
values[7] 9541 1 T15 59 T86 1 T82 196
values[8] 8176 1 T15 80 T86 1 T82 177
values[9] 7270 1 T15 71 T86 1 T82 126
values[10] 6430 1 T15 48 T86 1 T82 136
values[11] 5478 1 T15 44 T86 1 T82 98
values[12] 5072 1 T15 37 T86 1 T82 81
values[13] 4738 1 T15 36 T86 1 T82 58
values[14] 4182 1 T15 40 T86 1 T82 43
values[15] 3774 1 T15 20 T86 1 T82 50
values[16] 3362 1 T15 22 T86 1 T82 40
values[17] 3095 1 T15 11 T86 1 T82 19
values[18] 2969 1 T15 21 T86 1 T82 21
values[19] 2882 1 T15 13 T86 1 T82 19
values[20] 2708 1 T15 21 T86 1 T82 18
values[21] 2493 1 T15 27 T86 1 T82 8
values[22] 2478 1 T15 27 T86 1 T82 10
values[23] 2252 1 T15 15 T86 1 T82 5
values[24] 2257 1 T15 27 T86 1 T82 8
values[25] 2277 1 T15 23 T86 1 T82 10
values[26] 2104 1 T15 17 T86 1 T82 17
values[27] 2078 1 T15 11 T86 1 T82 9
values[28] 2030 1 T15 12 T86 1 T82 3
values[29] 2056 1 T15 15 T86 1 T82 4
values[30] 1915 1 T15 11 T86 1 T82 8
values[31] 1836 1 T15 13 T86 1 T82 11
values[32] 1749 1 T15 18 T86 1 T82 8
values[33] 1637 1 T15 14 T86 1 T82 13
values[34] 1718 1 T15 10 T86 1 T82 6
values[35] 1576 1 T15 17 T86 1 T33 15
values[36] 1608 1 T15 19 T86 1 T33 23
values[37] 1537 1 T15 14 T86 1 T33 12
values[38] 1454 1 T15 18 T86 1 T33 15
values[39] 1404 1 T15 15 T86 1 T33 23
values[40] 1353 1 T15 11 T86 1 T33 23
values[41] 1314 1 T15 13 T86 1 T33 32
values[42] 1338 1 T15 12 T86 1 T33 23
values[43] 1424 1 T15 23 T86 1 T33 25
values[44] 1363 1 T15 8 T86 1 T33 30
values[45] 1341 1 T15 6 T86 1 T33 13
values[46] 1337 1 T15 4 T86 1 T33 20
values[47] 1337 1 T15 12 T86 1 T33 12
values[48] 1276 1 T15 18 T86 1 T33 20
values[49] 1273 1 T15 11 T86 1 T33 18
values[50] 1234 1 T15 9 T86 1 T33 19
values[51] 1232 1 T15 7 T86 1 T33 18
values[52] 1240 1 T15 12 T86 1 T33 17
values[53] 1228 1 T15 14 T86 1 T33 21
values[54] 1229 1 T15 12 T86 1 T33 19
values[55] 1199 1 T15 6 T86 1 T33 17
values[56] 1204 1 T15 11 T86 1 T33 24
values[57] 1245 1 T15 14 T86 1 T33 21
values[58] 1197 1 T15 13 T86 1 T33 18
values[59] 1217 1 T15 13 T86 1 T33 16
values[60] 1274 1 T15 18 T86 1 T33 10
values[61] 1415 1 T15 14 T86 1 T33 21
values[62] 2510 1 T15 42 T86 1 T33 37
values[63] 7188 1 T15 118 T86 3 T33 178
values[64] 109094 1 T15 176 T86 208 T33 431


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2179237 1 T1 73 T2 104 T3 348
values[2] 369219 1 T1 26 T2 31 T3 83
values[3] 39061 1 T1 3 T2 1 T3 1
values[4] 8035 1 T3 1 T7 2 T8 4
values[5] 3670 1 T7 1 T15 4 T86 3
values[6] 2537 1 T15 8 T86 1 T59 1
values[7] 1979 1 T15 21 T41 1 T33 18
values[8] 1693 1 T15 19 T33 17 T87 1
values[9] 1446 1 T15 11 T33 22 T87 6
values[10] 1385 1 T15 6 T33 30 T87 3
values[11] 1217 1 T15 18 T33 26 T87 3
values[12] 1067 1 T15 13 T33 31 T87 2
values[13] 1035 1 T15 22 T33 31 T87 2
values[14] 961 1 T15 14 T33 32 T87 3
values[15] 980 1 T15 13 T33 30 T87 4
values[16] 884 1 T15 5 T33 21 T87 2
values[17] 823 1 T15 2 T33 25 T87 1
values[18] 765 1 T15 5 T33 15 T87 1
values[19] 789 1 T15 5 T33 12 T87 2
values[20] 744 1 T15 4 T33 12 T87 1
values[21] 738 1 T15 8 T33 22 T87 1
values[22] 711 1 T15 2 T33 18 T87 2
values[23] 664 1 T15 3 T33 15 T87 3
values[24] 643 1 T15 2 T33 8 T87 2
values[25] 560 1 T15 1 T33 5 T87 2
values[26] 579 1 T15 2 T33 3 T87 3
values[27] 543 1 T15 1 T33 6 T87 1
values[28] 482 1 T15 1 T33 11 T87 3
values[29] 484 1 T15 2 T33 6 T87 6
values[30] 458 1 T15 1 T33 7 T87 5
values[31] 469 1 T15 3 T33 7 T87 4
values[32] 470 1 T15 6 T33 4 T87 3
values[33] 455 1 T15 16 T33 4 T87 2
values[34] 437 1 T15 8 T33 5 T87 1
values[35] 416 1 T15 5 T33 8 T87 1
values[36] 397 1 T15 1 T33 7 T87 2
values[37] 396 1 T15 2 T33 4 T87 2
values[38] 361 1 T15 3 T33 5 T87 1
values[39] 365 1 T15 1 T33 7 T87 1
values[40] 380 1 T15 2 T33 5 T87 2
values[41] 355 1 T15 2 T33 5 T87 2
values[42] 342 1 T15 3 T33 3 T87 3
values[43] 342 1 T33 2 T87 5 T223 1
values[44] 346 1 T33 4 T87 4 T223 1
values[45] 361 1 T33 3 T87 2 T223 1
values[46] 361 1 T33 3 T87 6 T223 1
values[47] 347 1 T33 3 T87 3 T223 1
values[48] 318 1 T33 5 T87 6 T223 1
values[49] 326 1 T33 5 T87 7 T223 1
values[50] 322 1 T33 7 T87 1 T223 1
values[51] 332 1 T33 15 T87 1 T223 1
values[52] 332 1 T33 7 T87 2 T223 1
values[53] 324 1 T33 4 T87 1 T223 1
values[54] 324 1 T33 6 T87 2 T223 1
values[55] 318 1 T33 5 T87 2 T223 1
values[56] 299 1 T33 8 T87 1 T223 1
values[57] 298 1 T33 2 T87 1 T223 1
values[58] 272 1 T33 5 T87 1 T223 1
values[59] 285 1 T33 3 T87 2 T223 1
values[60] 324 1 T33 4 T87 5 T223 1
values[61] 325 1 T33 6 T87 5 T223 1
values[62] 486 1 T33 16 T87 5 T223 1
values[63] 1774 1 T33 32 T87 24 T223 1
values[64] 23450 1 T33 88 T87 59 T223 213


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 284670 1 T1 1 T2 1 T3 3
values[2] 1481619 1 T1 149 T2 158 T3 380
values[3] 475283 1 T1 8 T2 37 T3 29
values[4] 45074 1 T7 6 T8 5 T11 12
values[5] 28539 1 T15 110 T86 1 T59 1
values[6] 21680 1 T15 103 T86 1 T82 296
values[7] 17498 1 T15 123 T86 1 T82 262
values[8] 15040 1 T15 82 T86 1 T82 224
values[9] 12837 1 T15 74 T86 1 T82 210
values[10] 10672 1 T15 70 T86 1 T82 208
values[11] 9443 1 T15 65 T86 1 T82 224
values[12] 8113 1 T15 64 T86 1 T82 188
values[13] 7272 1 T15 78 T86 1 T82 144
values[14] 6492 1 T15 51 T86 1 T82 112
values[15] 5724 1 T15 48 T86 1 T82 52
values[16] 5430 1 T15 55 T86 1 T82 34
values[17] 4964 1 T15 25 T86 1 T82 27
values[18] 4370 1 T15 27 T86 1 T82 29
values[19] 3998 1 T15 25 T86 1 T82 9
values[20] 3742 1 T15 18 T86 1 T82 12
values[21] 3361 1 T15 17 T86 1 T82 17
values[22] 3182 1 T15 18 T86 1 T82 15
values[23] 3033 1 T15 13 T86 1 T82 23
values[24] 2828 1 T15 15 T86 1 T82 33
values[25] 2605 1 T15 14 T86 1 T82 16
values[26] 2440 1 T15 14 T86 1 T82 13
values[27] 2278 1 T15 17 T86 1 T82 16
values[28] 2273 1 T15 18 T86 1 T82 11
values[29] 2004 1 T15 16 T86 1 T82 8
values[30] 1996 1 T15 10 T86 1 T82 16
values[31] 1950 1 T15 12 T86 1 T82 10
values[32] 1848 1 T15 17 T86 1 T82 1
values[33] 1697 1 T15 11 T86 1 T82 3
values[34] 1658 1 T15 18 T86 1 T82 5
values[35] 1611 1 T15 9 T86 1 T82 6
values[36] 1579 1 T15 6 T86 1 T82 5
values[37] 1485 1 T15 11 T86 1 T82 1
values[38] 1516 1 T15 8 T86 1 T82 5
values[39] 1553 1 T15 13 T86 1 T82 3
values[40] 1468 1 T15 11 T86 1 T82 2
values[41] 1494 1 T15 8 T86 1 T82 1
values[42] 1383 1 T15 8 T86 1 T82 1
values[43] 1397 1 T15 19 T86 1 T82 4
values[44] 1374 1 T15 11 T86 1 T82 6
values[45] 1365 1 T15 14 T86 1 T82 13
values[46] 1360 1 T15 16 T86 1 T82 8
values[47] 1309 1 T15 11 T86 1 T82 4
values[48] 1257 1 T15 14 T86 1 T82 2
values[49] 1220 1 T15 9 T86 1 T33 15
values[50] 1234 1 T15 7 T86 1 T33 18
values[51] 1261 1 T15 11 T86 1 T33 16
values[52] 1264 1 T15 5 T86 1 T33 16
values[53] 1252 1 T15 5 T86 1 T33 20
values[54] 1219 1 T15 15 T86 1 T33 15
values[55] 1232 1 T15 11 T86 1 T33 24
values[56] 1199 1 T15 13 T86 1 T33 20
values[57] 1223 1 T15 10 T86 1 T33 15
values[58] 1251 1 T15 17 T86 1 T33 20
values[59] 1225 1 T15 16 T86 1 T33 25
values[60] 1295 1 T15 13 T86 1 T33 32
values[61] 1363 1 T15 6 T86 1 T33 31
values[62] 2122 1 T15 30 T86 1 T33 52
values[63] 6238 1 T15 116 T86 2 T33 124
values[64] 107069 1 T15 215 T86 167 T33 269

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%