Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1326528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

210565

1

T1

19

T2

18

T3

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	522274	1			T1	32		T2	35		T3	142
values[0x0]	492207	1			T1	39		T2	36		T3	133
values[0x1]	522612	1			T1	43		T2	36		T3	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1025168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

511925

1

T1

37

T2

37

T3

142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23786	1			T1	1		T3	10		T7	1
valid_sources[0x01]	24096	1			T1	1		T3	12		T7	1
valid_sources[0x02]	23752	1			T1	4		T3	9		T7	2
valid_sources[0x03]	23689	1			T3	1		T7	4		T8	48
valid_sources[0x04]	24922	1			T3	6		T8	36		T9	3
valid_sources[0x05]	24190	1			T1	2		T3	15		T7	3
valid_sources[0x06]	23931	1			T1	1		T3	4		T7	2
valid_sources[0x07]	24436	1			T1	6		T3	1		T7	3
valid_sources[0x08]	23517	1			T1	2		T2	3		T3	5
valid_sources[0x09]	23945	1			T1	4		T3	7		T7	1
valid_sources[0x0a]	24065	1			T1	1		T3	7		T7	1
valid_sources[0x0b]	24540	1			T3	4		T7	1		T8	35
valid_sources[0x0c]	24149	1			T1	1		T3	3		T8	27
valid_sources[0x0d]	24717	1			T1	3		T3	16		T7	1
valid_sources[0x0e]	23513	1			T1	1		T3	9		T8	30
valid_sources[0x0f]	23420	1			T1	3		T7	2		T8	21
valid_sources[0x10]	23580	1			T1	3		T3	5		T8	42
valid_sources[0x11]	24501	1			T1	1		T3	2		T8	40
valid_sources[0x12]	23252	1			T1	1		T3	1		T7	2
valid_sources[0x13]	23636	1			T1	3		T3	10		T7	4
valid_sources[0x14]	23940	1			T1	1		T3	7		T7	1
valid_sources[0x15]	23281	1			T1	3		T3	11		T7	2
valid_sources[0x16]	24842	1			T1	1		T2	13		T3	10
valid_sources[0x17]	23843	1			T1	1		T3	3		T7	2
valid_sources[0x18]	24306	1			T1	1		T3	9		T7	4
valid_sources[0x19]	24564	1			T1	6		T3	3		T8	27
valid_sources[0x1a]	24333	1			T3	4		T7	3		T8	34
valid_sources[0x1b]	23738	1			T3	4		T7	3		T8	37
valid_sources[0x1c]	24794	1			T1	1		T3	3		T7	3
valid_sources[0x1d]	24254	1			T1	2		T3	3		T7	1
valid_sources[0x1e]	23862	1			T3	3		T7	2		T8	30
valid_sources[0x1f]	24003	1			T1	1		T3	5		T7	3
valid_sources[0x20]	24141	1			T1	3		T3	3		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21929

1

T1

2

T2

1

T3

5

values[0x0]

all_enables

biggest_size

166453

1

T1

14

T2

16

T3

46

values[0x1]

all_enables

biggest_size

22183

1

T1

3

T2

1

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1332049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

216382

1

T1

10

T2

15

T3

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	530518	1			T1	29		T2	42		T3	138
values[0x0]	487699	1			T1	32		T2	45		T3	146
values[0x1]	530214	1			T1	41		T2	49		T3	149

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1022002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

526429

1

T1

25

T2

44

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24753	1			T1	5		T3	8		T8	38
valid_sources[0x01]	24507	1			T1	22		T3	5		T8	31
valid_sources[0x02]	24814	1			T3	17		T7	3		T8	24
valid_sources[0x03]	24293	1			T2	12		T3	9		T7	4
valid_sources[0x04]	25214	1			T2	16		T3	5		T8	44
valid_sources[0x05]	24272	1			T3	3		T8	32		T9	1
valid_sources[0x06]	24278	1			T1	15		T3	3		T8	20
valid_sources[0x07]	24097	1			T1	2		T8	22		T9	7
valid_sources[0x08]	23717	1			T3	19		T7	2		T8	18
valid_sources[0x09]	24341	1			T1	16		T3	5		T7	1
valid_sources[0x0a]	24702	1			T3	7		T7	2		T8	35
valid_sources[0x0b]	23840	1			T1	9		T2	14		T3	8
valid_sources[0x0c]	24669	1			T3	7		T7	4		T8	27
valid_sources[0x0d]	24214	1			T3	6		T7	1		T8	27
valid_sources[0x0e]	23505	1			T3	21		T7	1		T8	34
valid_sources[0x0f]	24482	1			T1	1		T2	2		T3	5
valid_sources[0x10]	24196	1			T3	19		T7	6		T8	15
valid_sources[0x11]	24379	1			T3	3		T8	36		T10	1
valid_sources[0x12]	23925	1			T3	4		T7	1		T8	25
valid_sources[0x13]	24493	1			T3	10		T7	1		T8	27
valid_sources[0x14]	24165	1			T3	4		T8	39		T10	1
valid_sources[0x15]	23919	1			T1	8		T3	19		T8	28
valid_sources[0x16]	24167	1			T3	8		T7	3		T8	26
valid_sources[0x17]	24592	1			T2	1		T3	2		T8	23
valid_sources[0x18]	23853	1			T1	1		T3	2		T8	15
valid_sources[0x19]	24431	1			T3	13		T8	42		T9	3
valid_sources[0x1a]	23992	1			T1	1		T7	1		T8	49
valid_sources[0x1b]	24227	1			T1	4		T3	10		T7	2
valid_sources[0x1c]	25044	1			T1	3		T2	7		T3	5
valid_sources[0x1d]	24441	1			T1	1		T8	40		T10	2
valid_sources[0x1e]	23313	1			T3	8		T8	25		T10	2
valid_sources[0x1f]	23303	1			T2	5		T3	5		T7	3
valid_sources[0x20]	24066	1			T3	3		T7	10		T8	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22864

1

T1

1

T2

3

T3

6

values[0x0]

all_enables

biggest_size

170519

1

T1

7

T2

11

T3

53

values[0x1]

all_enables

biggest_size

22999

1

T1

2

T2

1

T3

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1330531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

211164

1

T1

29

T2

20

T3

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	523881	1			T1	45		T2	57		T3	138
values[0x0]	493879	1			T1	65		T2	64		T3	140
values[0x1]	523935	1			T1	48		T2	75		T3	134

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1028003	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

513692

1

T1

49

T2

64

T3

139

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23886	1			T1	28		T2	1		T3	10
valid_sources[0x01]	24490	1			T1	4		T2	4		T3	6
valid_sources[0x02]	25042	1			T2	4		T3	6		T8	36
valid_sources[0x03]	24102	1			T3	3		T8	31		T9	2
valid_sources[0x04]	24005	1			T2	3		T3	5		T8	29
valid_sources[0x05]	23890	1			T2	5		T3	9		T8	38
valid_sources[0x06]	23896	1			T3	1		T8	32		T9	1
valid_sources[0x07]	24213	1			T3	5		T8	40		T9	4
valid_sources[0x08]	24050	1			T3	2		T8	37		T11	3
valid_sources[0x09]	24207	1			T3	4		T8	34		T9	3
valid_sources[0x0a]	24562	1			T3	7		T8	33		T9	3
valid_sources[0x0b]	23899	1			T3	4		T7	13		T8	35
valid_sources[0x0c]	24349	1			T2	8		T3	7		T7	13
valid_sources[0x0d]	24213	1			T2	1		T3	7		T8	35
valid_sources[0x0e]	23602	1			T2	12		T3	3		T8	35
valid_sources[0x0f]	23933	1			T3	6		T8	28		T9	4
valid_sources[0x10]	23716	1			T1	6		T3	1		T8	41
valid_sources[0x11]	24596	1			T2	4		T8	35		T9	1
valid_sources[0x12]	24118	1			T2	3		T3	8		T8	31
valid_sources[0x13]	23857	1			T3	4		T8	33		T9	4
valid_sources[0x14]	23579	1			T2	5		T3	6		T8	36
valid_sources[0x15]	23530	1			T2	34		T3	3		T8	29
valid_sources[0x16]	23993	1			T2	1		T3	4		T8	33
valid_sources[0x17]	24518	1			T2	1		T3	8		T7	1
valid_sources[0x18]	24720	1			T2	10		T3	8		T8	32
valid_sources[0x19]	24345	1			T2	6		T3	6		T8	31
valid_sources[0x1a]	23776	1			T2	5		T3	4		T7	1
valid_sources[0x1b]	24596	1			T3	3		T8	39		T9	3
valid_sources[0x1c]	23976	1			T1	7		T2	4		T3	3
valid_sources[0x1d]	24058	1			T2	5		T3	10		T8	30
valid_sources[0x1e]	24454	1			T1	53		T2	1		T3	13
valid_sources[0x1f]	23562	1			T3	13		T7	3		T8	39
valid_sources[0x20]	24170	1			T3	7		T7	7		T8	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22295

1

T1

2

T2

1

T3

6

values[0x0]

all_enables

biggest_size

166643

1

T1

24

T2

16

T3

50

values[0x1]

all_enables

biggest_size

22226

1

T1

3

T2

3

T3

6