Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7127053	0	0
GntImpliesValid_A	2147483647	7127053	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7127053	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	459879342	0	0
ReadyAndValidImplyGrant_A	2147483647	7127053	0	0
ReqAndReadyImplyGrant_A	2147483647	7127053	0	0
ReqImpliesValid_A	2147483647	33717983	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	39164	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7127053	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	34848	34440	0	0
T2	206712	206448	0	0
T3	62856	61896	0	0
T7	5455368	5453904	0	0
T8	1583760	1583112	0	0
T9	47928	46824	0	0
T10	56712	55176	0	0
T11	1112736	1111224	0	0
T12	10687824	10686840	0	0
T13	204528	203904	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	34848	34440	0	0
T2	206712	206448	0	0
T3	62856	61896	0	0
T7	5455368	5453904	0	0
T8	1583760	1583112	0	0
T9	47928	46824	0	0
T10	56712	55176	0	0
T11	1112736	1111224	0	0
T12	10687824	10686840	0	0
T13	204528	203904	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	34848	34440	0	0
T2	206712	206448	0	0
T3	62856	61896	0	0
T7	5455368	5453904	0	0
T8	1583760	1583112	0	0
T9	47928	46824	0	0
T10	56712	55176	0	0
T11	1112736	1111224	0	0
T12	10687824	10686840	0	0
T13	204528	203904	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	459879342	0	0
T1	34848	376	0	0
T2	206712	10398	0	0
T3	62856	1628	0	0
T7	5455368	191276	0	0
T8	1583760	101771	0	0
T9	47928	516	0	0
T10	56712	642	0	0
T11	1112736	73245	0	0
T12	10687824	536839	0	0
T13	204528	4599	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33717983	0	0
T1	34848	397	0	0
T2	206712	814	0	0
T3	62856	1422	0	0
T7	5455368	730	0	0
T8	1583760	15148	0	0
T9	47928	513	0	0
T10	56712	554	0	0
T11	1112736	11446	0	0
T12	10687824	32080	0	0
T13	204528	3628	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39164	0	21600
T3	5238	6	0	2
T7	454614	0	0	2
T8	131980	1	0	2
T9	3994	0	0	2
T10	4726	0	0	2
T11	92728	3	0	2
T12	890652	0	0	2
T13	17044	5	0	2
T14	106848	2	0	2
T15	0	17	0	0
T16	0	13	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	0	4	0	0
T20	0	24	0	0
T21	0	8	0	0
T22	0	4	0	0
T23	40322	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	34848	34440	0	0
T2	206712	206448	0	0
T3	62856	61896	0	0
T7	5455368	5453904	0	0
T8	1583760	1583112	0	0
T9	47928	46824	0	0
T10	56712	55176	0	0
T11	1112736	1111224	0	0
T12	10687824	10686840	0	0
T13	204528	203904	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7127053	0	0
T1	34848	374	0	0
T2	206712	439	0	0
T3	62856	1246	0	0
T7	5455368	401	0	0
T8	1583760	6375	0	0
T9	47928	458	0	0
T10	56712	476	0	0
T11	1112736	4834	0	0
T12	10687824	430	0	0
T13	204528	3236	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	800182	0	0
GntImpliesValid_A	418665934	800182	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	800182	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	12564344	0	0
ReadyAndValidImplyGrant_A	418665934	800182	0	0
ReqAndReadyImplyGrant_A	418665934	800182	0	0
ReqImpliesValid_A	418665934	2428987	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	800182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	12564344	0	0
T1	1452	20	0	0
T2	8613	333	0	0
T3	2619	87	0	0
T7	227307	183	0	0
T8	65990	4778	0	0
T9	1997	47	0	0
T10	2363	43	0	0
T11	46364	4094	0	0
T12	445326	20327	0	0
T13	8522	325	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	2428987	0	0
T1	1452	25	0	0
T2	8613	93	0	0
T3	2619	152	0	0
T7	227307	61	0	0
T8	65990	1160	0	0
T9	1997	64	0	0
T10	2363	64	0	0
T11	46364	1127	0	0
T12	445326	3751	0	0
T13	8522	460	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	800182	0	0
T1	1452	22	0	0
T2	8613	44	0	0
T3	2619	119	0	0
T7	227307	47	0	0
T8	65990	667	0	0
T9	1997	55	0	0
T10	2363	53	0	0
T11	46364	569	0	0
T12	445326	73	0	0
T13	8522	392	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	788057	0	0
GntImpliesValid_A	418665934	788057	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	788057	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	12468663	0	0
ReadyAndValidImplyGrant_A	418665934	788057	0	0
ReqAndReadyImplyGrant_A	418665934	788057	0	0
ReqImpliesValid_A	418665934	2426272	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	788057	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	12468663	0	0
T1	1452	31	0	0
T2	8613	370	0	0
T3	2619	103	0	0
T7	227307	145	0	0
T8	65990	5527	0	0
T9	1997	40	0	0
T10	2363	47	0	0
T11	46364	3990	0	0
T12	445326	16397	0	0
T13	8522	314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	2426272	0	0
T1	1452	48	0	0
T2	8613	56	0	0
T3	2619	168	0	0
T7	227307	57	0	0
T8	65990	1371	0	0
T9	1997	53	0	0
T10	2363	66	0	0
T11	46364	972	0	0
T12	445326	1436	0	0
T13	8522	443	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	788057	0	0
T1	1452	39	0	0
T2	8613	49	0	0
T3	2619	135	0	0
T7	227307	33	0	0
T8	65990	747	0	0
T9	1997	46	0	0
T10	2363	56	0	0
T11	46364	533	0	0
T12	445326	55	0	0
T13	8522	378	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	208256	0	0
GntImpliesValid_A	418665934	208256	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	208256	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3088864	0	0
ReadyAndValidImplyGrant_A	418665934	208256	0	0
ReqAndReadyImplyGrant_A	418665934	208256	0	0
ReqImpliesValid_A	418665934	565334	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	208256	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3088864	0	0
T1	1452	14	0	0
T2	8613	108	0	0
T3	2619	22	0	0
T7	227307	40	0	0
T8	65990	1533	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	886	0	0
T12	445326	3122	0	0
T13	8522	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	565334	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	27	0	0
T7	227307	21	0	0
T8	65990	274	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	188	0	0
T12	445326	318	0	0
T13	8522	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	208256	0	0
T1	1452	13	0	0
T2	8613	10	0	0
T3	2619	24	0	0
T7	227307	11	0	0
T8	65990	185	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	130	0	0
T12	445326	8	0	0
T13	8522	70	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	201972	0	0
GntImpliesValid_A	418665934	201972	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	201972	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3100964	0	0
ReadyAndValidImplyGrant_A	418665934	201972	0	0
ReqAndReadyImplyGrant_A	418665934	201972	0	0
ReqImpliesValid_A	418665934	547984	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	201972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3100964	0	0
T1	1452	15	0	0
T2	8613	43	0	0
T3	2619	34	0	0
T7	227307	55	0	0
T8	65990	1330	0	0
T9	1997	10	0	0
T10	2363	14	0	0
T11	46364	1156	0	0
T12	445326	2743	0	0
T13	8522	82	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	547984	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	33	0	0
T7	227307	19	0	0
T8	65990	231	0	0
T9	1997	9	0	0
T10	2363	15	0	0
T11	46364	185	0	0
T12	445326	8	0	0
T13	8522	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	201972	0	0
T1	1452	14	0	0
T2	8613	8	0	0
T3	2619	33	0	0
T7	227307	14	0	0
T8	65990	168	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	143	0	0
T12	445326	8	0	0
T13	8522	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	198894	0	0
GntImpliesValid_A	418665934	198894	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	198894	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	5186984	0	0
ReadyAndValidImplyGrant_A	418665934	198894	0	0
ReqAndReadyImplyGrant_A	418665934	198894	0	0
ReqImpliesValid_A	418665934	1071137	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	198894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	5186984	0	0
T1	1452	12	0	0
T2	8613	66	0	0
T3	2619	235	0	0
T7	227307	179	0	0
T8	65990	4106	0	0
T9	1997	54	0	0
T10	2363	81	0	0
T11	46364	2293	0	0
T12	445326	2260	0	0
T13	8522	1334	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	1071137	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	60	0	0
T7	227307	20	0	0
T8	65990	576	0	0
T9	1997	22	0	0
T10	2363	19	0	0
T11	46364	285	0	0
T12	445326	8	0	0
T13	8522	202	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198894	0	0
T1	1452	4	0	0
T2	8613	13	0	0
T3	2619	31	0	0
T7	227307	16	0	0
T8	65990	178	0	0
T9	1997	13	0	0
T10	2363	14	0	0
T11	46364	149	0	0
T12	445326	8	0	0
T13	8522	92	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	188580	0	0
GntImpliesValid_A	418665934	188580	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	188580	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	4842555	0	0
ReadyAndValidImplyGrant_A	418665934	188580	0	0
ReqAndReadyImplyGrant_A	418665934	188580	0	0
ReqImpliesValid_A	418665934	1068437	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	188580	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	4842555	0	0
T1	1452	28	0	0
T2	8613	69	0	0
T3	2619	176	0	0
T7	227307	111	0	0
T8	65990	1490	0	0
T9	1997	53	0	0
T10	2363	106	0	0
T11	46364	1266	0	0
T12	445326	2944	0	0
T13	8522	547	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	1068437	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	41	0	0
T7	227307	15	0	0
T8	65990	227	0	0
T9	1997	21	0	0
T10	2363	31	0	0
T11	46364	204	0	0
T12	445326	7	0	0
T13	8522	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	188580	0	0
T1	1452	5	0	0
T2	8613	9	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	179	0	0
T9	1997	11	0	0
T10	2363	17	0	0
T11	46364	117	0	0
T12	445326	7	0	0
T13	8522	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	200423	0	0
GntImpliesValid_A	418665934	200423	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	200423	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	5127809	0	0
ReadyAndValidImplyGrant_A	418665934	200423	0	0
ReqAndReadyImplyGrant_A	418665934	200423	0	0
ReqImpliesValid_A	418665934	1170188	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	200423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	5127809	0	0
T1	1452	52	0	0
T2	8613	195	0	0
T3	2619	299	0	0
T7	227307	416	0	0
T8	65990	2048	0	0
T9	1997	51	0	0
T10	2363	130	0	0
T11	46364	2100	0	0
T12	445326	3117	0	0
T13	8522	389	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	1170188	0	0
T1	1452	26	0	0
T2	8613	22	0	0
T3	2619	51	0	0
T7	227307	75	0	0
T8	65990	250	0	0
T9	1997	15	0	0
T10	2363	46	0	0
T11	46364	343	0	0
T12	445326	166	0	0
T13	8522	109	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200423	0	0
T1	1452	18	0	0
T2	8613	22	0	0
T3	2619	34	0	0
T7	227307	16	0	0
T8	65990	147	0	0
T9	1997	12	0	0
T10	2363	20	0	0
T11	46364	140	0	0
T12	445326	11	0	0
T13	8522	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	192774	0	0
GntImpliesValid_A	418665934	192774	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	192774	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	5102206	0	0
ReadyAndValidImplyGrant_A	418665934	192774	0	0
ReqAndReadyImplyGrant_A	418665934	192774	0	0
ReqImpliesValid_A	418665934	1040519	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	192774	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	5102206	0	0
T1	1452	36	0	0
T2	8613	88	0	0
T3	2619	197	0	0
T7	227307	178	0	0
T8	65990	3177	0	0
T9	1997	69	0	0
T10	2363	43	0	0
T11	46364	1543	0	0
T12	445326	3075	0	0
T13	8522	358	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	1040519	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	61	0	0
T7	227307	24	0	0
T8	65990	539	0	0
T9	1997	24	0	0
T10	2363	12	0	0
T11	46364	171	0	0
T12	445326	13	0	0
T13	8522	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	192774	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	37	0	0
T7	227307	12	0	0
T8	65990	202	0	0
T9	1997	14	0	0
T10	2363	9	0	0
T11	46364	121	0	0
T12	445326	13	0	0
T13	8522	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	194859	0	0
GntImpliesValid_A	418665934	194859	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	194859	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3059633	0	0
ReadyAndValidImplyGrant_A	418665934	194859	0	0
ReqAndReadyImplyGrant_A	418665934	194859	0	0
ReqImpliesValid_A	418665934	548504	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	194859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3059633	0	0
T1	1452	13	0	0
T2	8613	84	0	0
T3	2619	30	0	0
T7	227307	29	0	0
T8	65990	1301	0	0
T9	1997	17	0	0
T10	2363	13	0	0
T11	46364	904	0	0
T12	445326	2671	0	0
T13	8522	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	548504	0	0
T1	1452	16	0	0
T2	8613	15	0	0
T3	2619	33	0	0
T7	227307	7	0	0
T8	65990	215	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	181	0	0
T12	445326	11	0	0
T13	8522	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	194859	0	0
T1	1452	14	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	7	0	0
T8	65990	179	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	128	0	0
T12	445326	11	0	0
T13	8522	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	195036	0	0
GntImpliesValid_A	418665934	195036	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	195036	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3110487	0	0
ReadyAndValidImplyGrant_A	418665934	195036	0	0
ReqAndReadyImplyGrant_A	418665934	195036	0	0
ReqImpliesValid_A	418665934	537056	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	195036	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3110487	0	0
T1	1452	11	0	0
T2	8613	115	0	0
T3	2619	32	0	0
T7	227307	37	0	0
T8	65990	1275	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	937	0	0
T12	445326	2766	0	0
T13	8522	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	537056	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	35	0	0
T7	227307	14	0	0
T8	65990	281	0	0
T9	1997	14	0	0
T10	2363	14	0	0
T11	46364	178	0	0
T12	445326	8	0	0
T13	8522	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195036	0	0
T1	1452	10	0	0
T2	8613	16	0	0
T3	2619	33	0	0
T7	227307	11	0	0
T8	65990	180	0	0
T9	1997	13	0	0
T10	2363	13	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	193753	0	0
GntImpliesValid_A	418665934	193753	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	193753	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3146472	0	0
ReadyAndValidImplyGrant_A	418665934	193753	0	0
ReqAndReadyImplyGrant_A	418665934	193753	0	0
ReqImpliesValid_A	418665934	545798	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	193753	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3146472	0	0
T1	1452	16	0	0
T2	8613	89	0	0
T3	2619	32	0	0
T7	227307	59	0	0
T8	65990	1342	0	0
T9	1997	8	0	0
T10	2363	15	0	0
T11	46364	903	0	0
T12	445326	2416	0	0
T13	8522	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	545798	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	17	0	0
T8	65990	242	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	170	0	0
T12	445326	7	0	0
T13	8522	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	193753	0	0
T1	1452	15	0	0
T2	8613	12	0	0
T3	2619	31	0	0
T7	227307	12	0	0
T8	65990	187	0	0
T9	1997	7	0	0
T10	2363	14	0	0
T11	46364	128	0	0
T12	445326	7	0	0
T13	8522	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	199838	0	0
GntImpliesValid_A	418665934	199838	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	199838	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3076631	0	0
ReadyAndValidImplyGrant_A	418665934	199838	0	0
ReqAndReadyImplyGrant_A	418665934	199838	0	0
ReqImpliesValid_A	418665934	522403	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	199838	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3076631	0	0
T1	1452	12	0	0
T2	8613	123	0	0
T3	2619	28	0	0
T7	227307	57	0	0
T8	65990	1415	0	0
T9	1997	10	0	0
T10	2363	14	0	0
T11	46364	1077	0	0
T12	445326	4591	0	0
T13	8522	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	522403	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	31	0	0
T7	227307	10	0	0
T8	65990	271	0	0
T9	1997	9	0	0
T10	2363	15	0	0
T11	46364	213	0	0
T12	445326	12	0	0
T13	8522	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	199838	0	0
T1	1452	11	0	0
T2	8613	15	0	0
T3	2619	29	0	0
T7	227307	10	0	0
T8	65990	186	0	0
T9	1997	9	0	0
T10	2363	14	0	0
T11	46364	147	0	0
T12	445326	12	0	0
T13	8522	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	189467	0	0
GntImpliesValid_A	418665934	189467	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	189467	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3102898	0	0
ReadyAndValidImplyGrant_A	418665934	189467	0	0
ReqAndReadyImplyGrant_A	418665934	189467	0	0
ReqImpliesValid_A	418665934	495836	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	189467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3102898	0	0
T1	1452	14	0	0
T2	8613	115	0	0
T3	2619	37	0	0
T7	227307	61	0	0
T8	65990	1141	0	0
T9	1997	6	0	0
T10	2363	6	0	0
T11	46364	1198	0	0
T12	445326	5257	0	0
T13	8522	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	495836	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	44	0	0
T7	227307	14	0	0
T8	65990	179	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	212	0	0
T12	445326	332	0	0
T13	8522	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	189467	0	0
T1	1452	13	0	0
T2	8613	15	0	0
T3	2619	40	0	0
T7	227307	13	0	0
T8	65990	153	0	0
T9	1997	5	0	0
T10	2363	5	0	0
T11	46364	155	0	0
T12	445326	15	0	0
T13	8522	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	195352	0	0
GntImpliesValid_A	418665934	195352	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	195352	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3136042	0	0
ReadyAndValidImplyGrant_A	418665934	195352	0	0
ReqAndReadyImplyGrant_A	418665934	195352	0	0
ReqImpliesValid_A	418665934	509550	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	195352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3136042	0	0
T1	1452	12	0	0
T2	8613	88	0	0
T3	2619	32	0	0
T7	227307	11	0	0
T8	65990	1363	0	0
T9	1997	17	0	0
T10	2363	11	0	0
T11	46364	1097	0	0
T12	445326	1821	0	0
T13	8522	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	509550	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	33	0	0
T7	227307	9	0	0
T8	65990	281	0	0
T9	1997	18	0	0
T10	2363	10	0	0
T11	46364	195	0	0
T12	445326	7	0	0
T13	8522	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	195352	0	0
T1	1452	11	0	0
T2	8613	11	0	0
T3	2619	32	0	0
T7	227307	3	0	0
T8	65990	186	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	148	0	0
T12	445326	7	0	0
T13	8522	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	197594	0	0
GntImpliesValid_A	418665934	197594	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	197594	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3095069	0	0
ReadyAndValidImplyGrant_A	418665934	197594	0	0
ReqAndReadyImplyGrant_A	418665934	197594	0	0
ReqImpliesValid_A	418665934	521650	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	197594	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3095069	0	0
T1	1452	7	0	0
T2	8613	90	0	0
T3	2619	22	0	0
T7	227307	55	0	0
T8	65990	1481	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	1128	0	0
T12	445326	2093	0	0
T13	8522	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	521650	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	23	0	0
T7	227307	17	0	0
T8	65990	297	0	0
T9	1997	11	0	0
T10	2363	12	0	0
T11	46364	200	0	0
T12	445326	6	0	0
T13	8522	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197594	0	0
T1	1452	6	0	0
T2	8613	13	0	0
T3	2619	22	0	0
T7	227307	14	0	0
T8	65990	206	0	0
T9	1997	11	0	0
T10	2363	11	0	0
T11	46364	135	0	0
T12	445326	6	0	0
T13	8522	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	204521	0	0
GntImpliesValid_A	418665934	204521	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	204521	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3175674	0	0
ReadyAndValidImplyGrant_A	418665934	204521	0	0
ReqAndReadyImplyGrant_A	418665934	204521	0	0
ReqImpliesValid_A	418665934	585681	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	204521	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3175674	0	0
T1	1452	14	0	0
T2	8613	41	0	0
T3	2619	38	0	0
T7	227307	42	0	0
T8	65990	1266	0	0
T9	1997	16	0	0
T10	2363	14	0	0
T11	46364	921	0	0
T12	445326	5159	0	0
T13	8522	71	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	585681	0	0
T1	1452	13	0	0
T2	8613	9	0	0
T3	2619	39	0	0
T7	227307	12	0	0
T8	65990	221	0	0
T9	1997	17	0	0
T10	2363	17	0	0
T11	46364	170	0	0
T12	445326	13	0	0
T13	8522	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	204521	0	0
T1	1452	13	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	12	0	0
T8	65990	161	0	0
T9	1997	16	0	0
T10	2363	15	0	0
T11	46364	118	0	0
T12	445326	13	0	0
T13	8522	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	217926	0	0
GntImpliesValid_A	418665934	217926	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	217926	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3250357	0	0
ReadyAndValidImplyGrant_A	418665934	217926	0	0
ReqAndReadyImplyGrant_A	418665934	217926	0	0
ReqImpliesValid_A	418665934	576429	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	217926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3250357	0	0
T1	1452	10	0	0
T2	8613	170	0	0
T3	2619	37	0	0
T7	227307	56	0	0
T8	65990	1282	0	0
T9	1997	11	0	0
T10	2363	9	0	0
T11	46364	949	0	0
T12	445326	3944	0	0
T13	8522	133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	576429	0	0
T1	1452	9	0	0
T2	8613	35	0	0
T3	2619	38	0	0
T7	227307	15	0	0
T8	65990	219	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	146	0	0
T12	445326	13	0	0
T13	8522	140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	217926	0	0
T1	1452	9	0	0
T2	8613	22	0	0
T3	2619	37	0	0
T7	227307	14	0	0
T8	65990	172	0	0
T9	1997	10	0	0
T10	2363	8	0	0
T11	46364	116	0	0
T12	445326	12	0	0
T13	8522	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	198377	0	0
GntImpliesValid_A	418665934	198377	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	198377	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3069455	0	0
ReadyAndValidImplyGrant_A	418665934	198377	0	0
ReqAndReadyImplyGrant_A	418665934	198377	0	0
ReqImpliesValid_A	418665934	535674	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	198377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3069455	0	0
T1	1452	9	0	0
T2	8613	85	0	0
T3	2619	34	0	0
T7	227307	23	0	0
T8	65990	1397	0	0
T9	1997	17	0	0
T10	2363	10	0	0
T11	46364	927	0	0
T12	445326	2969	0	0
T13	8522	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	535674	0	0
T1	1452	8	0	0
T2	8613	25	0	0
T3	2619	43	0	0
T7	227307	8	0	0
T8	65990	294	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	148	0	0
T12	445326	11	0	0
T13	8522	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	198377	0	0
T1	1452	8	0	0
T2	8613	12	0	0
T3	2619	38	0	0
T7	227307	7	0	0
T8	65990	188	0	0
T9	1997	16	0	0
T10	2363	9	0	0
T11	46364	124	0	0
T12	445326	11	0	0
T13	8522	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	197583	0	0
GntImpliesValid_A	418665934	197583	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	197583	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3081237	0	0
ReadyAndValidImplyGrant_A	418665934	197583	0	0
ReqAndReadyImplyGrant_A	418665934	197583	0	0
ReqImpliesValid_A	418665934	547031	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	197583	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3081237	0	0
T1	1452	14	0	0
T2	8613	129	0	0
T3	2619	38	0	0
T7	227307	61	0	0
T8	65990	1091	0	0
T9	1997	16	0	0
T10	2363	12	0	0
T11	46364	925	0	0
T12	445326	3193	0	0
T13	8522	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	547031	0	0
T1	1452	15	0	0
T2	8613	14	0	0
T3	2619	41	0	0
T7	227307	20	0	0
T8	65990	230	0	0
T9	1997	17	0	0
T10	2363	11	0	0
T11	46364	125	0	0
T12	445326	151	0	0
T13	8522	96	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197583	0	0
T1	1452	14	0	0
T2	8613	14	0	0
T3	2619	39	0	0
T7	227307	15	0	0
T8	65990	150	0	0
T9	1997	16	0	0
T10	2363	11	0	0
T11	46364	119	0	0
T12	445326	12	0	0
T13	8522	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	200420	0	0
GntImpliesValid_A	418665934	200420	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	200420	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3116237	0	0
ReadyAndValidImplyGrant_A	418665934	200420	0	0
ReqAndReadyImplyGrant_A	418665934	200420	0	0
ReqImpliesValid_A	418665934	577148	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	200420	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3116237	0	0
T1	1452	14	0	0
T2	8613	83	0	0
T3	2619	42	0	0
T7	227307	53	0	0
T8	65990	1305	0	0
T9	1997	13	0	0
T10	2363	10	0	0
T11	46364	1011	0	0
T12	445326	5558	0	0
T13	8522	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	577148	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	43	0	0
T7	227307	17	0	0
T8	65990	292	0	0
T9	1997	12	0	0
T10	2363	13	0	0
T11	46364	201	0	0
T12	445326	18	0	0
T13	8522	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	200420	0	0
T1	1452	13	0	0
T2	8613	11	0	0
T3	2619	42	0	0
T7	227307	13	0	0
T8	65990	184	0	0
T9	1997	12	0	0
T10	2363	11	0	0
T11	46364	138	0	0
T12	445326	18	0	0
T13	8522	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	197463	0	0
GntImpliesValid_A	418665934	197463	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	197463	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3068206	0	0
ReadyAndValidImplyGrant_A	418665934	197463	0	0
ReqAndReadyImplyGrant_A	418665934	197463	0	0
ReqImpliesValid_A	418665934	527750	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	197463	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3068206	0	0
T1	1452	10	0	0
T2	8613	77	0	0
T3	2619	36	0	0
T7	227307	43	0	0
T8	65990	1306	0	0
T9	1997	12	0	0
T10	2363	12	0	0
T11	46364	948	0	0
T12	445326	2650	0	0
T13	8522	97	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	527750	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	39	0	0
T7	227307	9	0	0
T8	65990	249	0	0
T9	1997	15	0	0
T10	2363	11	0	0
T11	46364	218	0	0
T12	445326	8	0	0
T13	8522	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	197463	0	0
T1	1452	9	0	0
T2	8613	9	0	0
T3	2619	37	0	0
T7	227307	9	0	0
T8	65990	190	0	0
T9	1997	13	0	0
T10	2363	11	0	0
T11	46364	127	0	0
T12	445326	8	0	0
T13	8522	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	187762	0	0
GntImpliesValid_A	418665934	187762	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	187762	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	3083290	0	0
ReadyAndValidImplyGrant_A	418665934	187762	0	0
ReqAndReadyImplyGrant_A	418665934	187762	0	0
ReqImpliesValid_A	418665934	490167	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	0	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	187762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	3083290	0	0
T1	1452	10	0	0
T2	8613	37	0	0
T3	2619	35	0	0
T7	227307	46	0	0
T8	65990	1335	0	0
T9	1997	7	0	0
T10	2363	15	0	0
T11	46364	1017	0	0
T12	445326	2591	0	0
T13	8522	82	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	490167	0	0
T1	1452	9	0	0
T2	8613	14	0	0
T3	2619	42	0	0
T7	227307	9	0	0
T8	65990	255	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	194	0	0
T12	445326	9	0	0
T13	8522	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	187762	0	0
T1	1452	9	0	0
T2	8613	8	0	0
T3	2619	38	0	0
T7	227307	9	0	0
T8	65990	187	0	0
T9	1997	6	0	0
T10	2363	14	0	0
T11	46364	127	0	0
T12	445326	9	0	0
T13	8522	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	792146	0	0
GntImpliesValid_A	418665934	792146	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	792146	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	11892993	0	0
ReadyAndValidImplyGrant_A	418665934	792146	0	0
ReqAndReadyImplyGrant_A	418665934	792146	0	0
ReqImpliesValid_A	418665934	2227063	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	15600	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	792146	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	11892993	0	0
T1	1452	1	0	0
T2	8613	277	0	0
T3	2619	1	0	0
T7	227307	150	0	0
T8	65990	4490	0	0
T9	1997	1	0	0
T10	2363	1	0	0
T11	46364	3749	0	0
T12	445326	15174	0	0
T13	8522	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	2227063	0	0
T1	1452	53	0	0
T2	8613	73	0	0
T3	2619	163	0	0
T7	227307	73	0	0
T8	65990	1341	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	940	0	0
T12	445326	1268	0	0
T13	8522	365	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	15600	0	900
T3	2619	3	0	1
T7	227307	0	0	1
T8	65990	0	0	1
T9	1997	0	0	1
T10	2363	0	0	1
T11	46364	0	0	1
T12	445326	0	0	1
T13	8522	2	0	1
T14	53424	1	0	1
T15	0	17	0	0
T16	0	10	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	0	8	0	0
T21	0	8	0	0
T22	0	4	0	0
T23	20161	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	792146	0	0
T1	1452	53	0	0
T2	8613	48	0	0
T3	2619	163	0	0
T7	227307	49	0	0
T8	65990	700	0	0
T9	1997	67	0	0
T10	2363	71	0	0
T11	46364	547	0	0
T12	445326	45	0	0
T13	8522	365	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418665934	418553828	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418665934	785818	0	0
GntImpliesValid_A	418665934	785818	0	0
GrantKnown_A	418665934	418553828	0	0
IdxKnown_A	418665934	418553828	0	0
IndexIsCorrect_A	418665934	785818	0	0
LockArbDecision_A	418665934	0	0	0
NoReadyValidNoGrant_A	418665934	352932272	0	0
ReadyAndValidImplyGrant_A	418665934	785818	0	0
ReqAndReadyImplyGrant_A	418665934	785818	0	0
ReqImpliesValid_A	418665934	13651385	0	0
ReqStaysHighUntilGranted0_M	418665934	0	0	0
RoundRobin_A	418665934	23564	0	900
ValidKnown_A	418665934	418553828	0	0
gen_data_port_assertion.DataFlow_A	418665934	785818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	352932272	0	0
T1	1452	1	0	0
T2	8613	7523	0	0
T3	2619	1	0	0
T7	227307	189186	0	0
T8	65990	54992	0	0
T9	1997	1	0	0
T10	2363	1	0	0
T11	46364	38226	0	0
T12	445326	420001	0	0
T13	8522	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	13651385	0	0
T1	1452	40	0	0
T2	8613	298	0	0
T3	2619	151	0	0
T7	227307	187	0	0
T8	65990	5653	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	4480	0	0
T12	445326	24499	0	0
T13	8522	368	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	23564	0	900
T3	2619	3	0	1
T7	227307	0	0	1
T8	65990	1	0	1
T9	1997	0	0	1
T10	2363	0	0	1
T11	46364	3	0	1
T12	445326	0	0	1
T13	8522	3	0	1
T14	53424	1	0	1
T16	0	3	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	16	0	0
T23	20161	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	418553828	0	0
T1	1452	1435	0	0
T2	8613	8602	0	0
T3	2619	2579	0	0
T7	227307	227246	0	0
T8	65990	65963	0	0
T9	1997	1951	0	0
T10	2363	2299	0	0
T11	46364	46301	0	0
T12	445326	445285	0	0
T13	8522	8496	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418665934	785818	0	0
T1	1452	40	0	0
T2	8613	44	0	0
T3	2619	151	0	0
T7	227307	43	0	0
T8	65990	693	0	0
T9	1997	49	0	0
T10	2363	53	0	0
T11	46364	548	0	0
T12	445326	53	0	0
T13	8522	368	0	0