Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1408768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

223795

1

T1

18

T2

28

T3

202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	554729	1			T1	46		T2	60		T3	517
values[0x0]	522592	1			T1	51		T2	68		T3	496
values[0x1]	555242	1			T1	60		T2	69		T3	513

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1088371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

544192

1

T1

51

T2

67

T3

482

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24786	1			T1	1		T2	7		T3	32
valid_sources[0x01]	25223	1			T1	10		T2	4		T3	14
valid_sources[0x02]	26698	1			T1	1		T3	27		T9	33
valid_sources[0x03]	25791	1			T3	12		T9	12		T11	51
valid_sources[0x04]	25288	1			T1	2		T2	10		T3	30
valid_sources[0x05]	26146	1			T1	3		T3	26		T9	27
valid_sources[0x06]	24680	1			T1	2		T2	2		T3	18
valid_sources[0x07]	26322	1			T1	3		T3	27		T9	7
valid_sources[0x08]	25317	1			T1	1		T2	6		T3	30
valid_sources[0x09]	25900	1			T1	5		T2	9		T3	19
valid_sources[0x0a]	24777	1			T1	5		T3	16		T9	25
valid_sources[0x0b]	24364	1			T1	2		T3	25		T9	20
valid_sources[0x0c]	25536	1			T1	1		T3	30		T9	35
valid_sources[0x0d]	25136	1			T1	1		T2	3		T3	19
valid_sources[0x0e]	26184	1			T1	4		T2	2		T3	21
valid_sources[0x0f]	25471	1			T1	1		T3	30		T9	19
valid_sources[0x10]	25155	1			T1	2		T3	11		T9	46
valid_sources[0x11]	25478	1			T1	3		T2	3		T3	22
valid_sources[0x12]	25914	1			T1	4		T3	13		T10	1
valid_sources[0x13]	25556	1			T1	2		T3	18		T9	40
valid_sources[0x14]	25193	1			T1	2		T2	1		T3	15
valid_sources[0x15]	25233	1			T1	5		T2	3		T3	28
valid_sources[0x16]	25122	1			T3	33		T9	46		T10	1
valid_sources[0x17]	25365	1			T1	3		T3	15		T9	50
valid_sources[0x18]	24641	1			T3	26		T9	22		T10	1
valid_sources[0x19]	24899	1			T1	2		T2	7		T3	38
valid_sources[0x1a]	25624	1			T1	3		T3	20		T9	83
valid_sources[0x1b]	25826	1			T1	4		T3	23		T9	34
valid_sources[0x1c]	26492	1			T1	3		T3	28		T9	11
valid_sources[0x1d]	25845	1			T1	5		T2	1		T3	20
valid_sources[0x1e]	26036	1			T1	2		T3	27		T9	24
valid_sources[0x1f]	26011	1			T1	3		T3	37		T9	21
valid_sources[0x20]	26527	1			T1	3		T2	3		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23692

1

T1

2

T3

21

T9

25

values[0x0]

all_enables

biggest_size

176448

1

T1

16

T2

24

T3

162

values[0x1]

all_enables

biggest_size

23655

1

T2

4

T3

19

T9

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1422011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231073

1

T1

22

T2

17

T3

191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	566752	1			T1	45		T2	43		T3	525
values[0x0]	518168	1			T1	51		T2	34		T3	473
values[0x1]	568164	1			T1	64		T2	36		T3	481

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1090864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

562220

1

T1

58

T2

42

T3

478

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25732	1			T1	1		T2	8		T3	24
valid_sources[0x01]	25165	1			T1	2		T2	2		T3	22
valid_sources[0x02]	25516	1			T1	5		T3	22		T9	11
valid_sources[0x03]	26286	1			T1	1		T3	14		T9	15
valid_sources[0x04]	25764	1			T1	1		T3	6		T9	17
valid_sources[0x05]	25947	1			T1	2		T2	11		T3	9
valid_sources[0x06]	25842	1			T3	16		T9	31		T10	4
valid_sources[0x07]	25838	1			T1	1		T3	35		T9	42
valid_sources[0x08]	25562	1			T1	4		T3	3		T9	17
valid_sources[0x09]	26265	1			T1	1		T3	23		T9	21
valid_sources[0x0a]	24851	1			T1	2		T3	56		T9	4
valid_sources[0x0b]	25105	1			T1	4		T2	2		T3	18
valid_sources[0x0c]	26146	1			T1	2		T3	3		T9	4
valid_sources[0x0d]	25803	1			T1	3		T3	30		T9	35
valid_sources[0x0e]	25996	1			T1	4		T3	18		T9	28
valid_sources[0x0f]	26143	1			T1	10		T2	2		T3	11
valid_sources[0x10]	26005	1			T1	1		T3	17		T9	23
valid_sources[0x11]	26468	1			T1	2		T3	12		T9	14
valid_sources[0x12]	25796	1			T1	2		T2	13		T3	29
valid_sources[0x13]	25814	1			T1	5		T3	32		T9	25
valid_sources[0x14]	26136	1			T1	1		T3	19		T9	15
valid_sources[0x15]	25581	1			T1	1		T3	33		T9	5
valid_sources[0x16]	25658	1			T1	4		T3	33		T9	31
valid_sources[0x17]	25222	1			T1	5		T3	25		T9	61
valid_sources[0x18]	26183	1			T1	5		T3	37		T9	36
valid_sources[0x19]	25674	1			T1	2		T3	13		T9	48
valid_sources[0x1a]	25354	1			T1	3		T3	11		T9	18
valid_sources[0x1b]	25990	1			T1	1		T2	15		T3	19
valid_sources[0x1c]	25130	1			T1	1		T3	20		T9	5
valid_sources[0x1d]	26077	1			T1	2		T2	10		T3	47
valid_sources[0x1e]	26536	1			T1	2		T3	4		T9	19
valid_sources[0x1f]	26643	1			T1	2		T2	7		T3	34
valid_sources[0x20]	26633	1			T1	2		T2	3		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24401

1

T2

3

T3

23

T9

29

values[0x0]

all_enables

biggest_size

181819

1

T1

20

T2

13

T3

153

values[0x1]

all_enables

biggest_size

24853

1

T1

2

T2

1

T3

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1417113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

224498

1

T1

23

T2

21

T3

248

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	558483	1			T1	60		T2	42		T3	534
values[0x0]	524418	1			T1	40		T2	53		T3	529
values[0x1]	558710	1			T1	61		T2	59		T3	509

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1094640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

546971

1

T1

62

T2

55

T3

521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25837	1			T3	43		T9	29		T10	2
valid_sources[0x01]	24941	1			T3	24		T9	16		T10	1
valid_sources[0x02]	25534	1			T3	30		T9	23		T10	4
valid_sources[0x03]	26559	1			T3	14		T9	32		T10	2
valid_sources[0x04]	25742	1			T3	37		T9	30		T10	5
valid_sources[0x05]	25780	1			T1	21		T3	19		T9	29
valid_sources[0x06]	25201	1			T3	25		T9	23		T10	2
valid_sources[0x07]	24718	1			T3	21		T9	27		T10	2
valid_sources[0x08]	25348	1			T3	12		T9	39		T11	21
valid_sources[0x09]	25972	1			T1	25		T3	19		T9	27
valid_sources[0x0a]	25216	1			T3	18		T9	27		T10	2
valid_sources[0x0b]	25145	1			T2	40		T3	14		T9	20
valid_sources[0x0c]	25891	1			T3	25		T9	33		T11	16
valid_sources[0x0d]	26078	1			T3	29		T9	33		T10	2
valid_sources[0x0e]	26478	1			T2	28		T3	20		T9	24
valid_sources[0x0f]	25994	1			T3	11		T9	21		T10	2
valid_sources[0x10]	26210	1			T2	3		T3	38		T9	44
valid_sources[0x11]	26068	1			T1	1		T3	26		T9	41
valid_sources[0x12]	25408	1			T3	15		T9	41		T10	2
valid_sources[0x13]	25193	1			T1	28		T3	14		T9	28
valid_sources[0x14]	25434	1			T3	30		T9	12		T10	2
valid_sources[0x15]	25371	1			T2	51		T3	18		T9	34
valid_sources[0x16]	25682	1			T3	13		T9	30		T10	1
valid_sources[0x17]	25532	1			T1	16		T3	10		T9	21
valid_sources[0x18]	25419	1			T3	37		T9	24		T10	1
valid_sources[0x19]	25294	1			T3	43		T9	31		T11	42
valid_sources[0x1a]	25641	1			T3	34		T9	39		T10	2
valid_sources[0x1b]	25475	1			T3	16		T9	25		T10	4
valid_sources[0x1c]	25283	1			T3	5		T9	29		T10	1
valid_sources[0x1d]	25588	1			T3	30		T9	29		T10	2
valid_sources[0x1e]	25608	1			T3	14		T9	22		T10	4
valid_sources[0x1f]	26393	1			T3	16		T9	20		T11	52
valid_sources[0x20]	26029	1			T1	13		T3	38		T9	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23929

1

T1

2

T2

2

T3

36

values[0x0]

all_enables

biggest_size

176707

1

T1

18

T2

17

T3

187

values[0x1]

all_enables

biggest_size

23862

1

T1

3

T2

2

T3

25