Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1385946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

220576

1

T1

21

T2

13

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	544880	1			T1	40		T2	33		T3	36
values[0x0]	516628	1			T1	53		T2	34		T3	41
values[0x1]	545014	1			T1	36		T2	40		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1071725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

534797

1

T1

43

T2

40

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25408	1			T2	2		T10	3		T16	7
valid_sources[0x01]	25400	1			T2	3		T10	2		T15	37
valid_sources[0x02]	25226	1			T3	1		T16	6		T17	12
valid_sources[0x03]	25477	1			T2	4		T12	3		T16	6
valid_sources[0x04]	24497	1			T10	1		T12	1		T16	10
valid_sources[0x05]	25636	1			T7	2		T12	4		T16	6
valid_sources[0x06]	24874	1			T2	3		T12	5		T16	6
valid_sources[0x07]	24953	1			T2	2		T12	4		T16	7
valid_sources[0x08]	26045	1			T2	2		T10	2		T12	19
valid_sources[0x09]	24398	1			T2	3		T12	3		T27	22
valid_sources[0x0a]	24873	1			T7	7		T16	5		T17	3
valid_sources[0x0b]	24864	1			T12	6		T13	15		T27	13
valid_sources[0x0c]	25189	1			T16	7		T17	10		T18	18
valid_sources[0x0d]	25722	1			T2	2		T15	14		T27	11
valid_sources[0x0e]	24425	1			T1	25		T12	1		T14	3
valid_sources[0x0f]	25128	1			T2	2		T10	1		T7	16
valid_sources[0x10]	24897	1			T2	4		T27	4		T16	7
valid_sources[0x11]	24715	1			T2	2		T3	1		T12	3
valid_sources[0x12]	26510	1			T2	1		T3	7		T7	21
valid_sources[0x13]	25054	1			T7	2		T16	5		T17	11
valid_sources[0x14]	24886	1			T16	3		T17	14		T18	18
valid_sources[0x15]	24705	1			T2	2		T12	1		T16	6
valid_sources[0x16]	24248	1			T12	1		T16	5		T17	8
valid_sources[0x17]	25401	1			T2	1		T12	1		T27	5
valid_sources[0x18]	25284	1			T2	1		T16	6		T17	20
valid_sources[0x19]	24762	1			T2	1		T3	6		T16	5
valid_sources[0x1a]	24781	1			T2	1		T3	9		T16	13
valid_sources[0x1b]	24992	1			T2	3		T7	32		T12	1
valid_sources[0x1c]	25668	1			T2	2		T3	28		T10	1
valid_sources[0x1d]	24402	1			T2	1		T16	10		T17	18
valid_sources[0x1e]	24811	1			T2	3		T16	1		T17	11
valid_sources[0x1f]	23866	1			T2	3		T7	7		T12	2
valid_sources[0x20]	25478	1			T12	7		T13	16		T16	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23362

1

T1

2

T2

1

T3

2

values[0x0]

all_enables

biggest_size

174160

1

T1

18

T2

8

T3

10

values[0x1]

all_enables

biggest_size

23054

1

T1

1

T2

4

T10

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1395283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

228129

1

T1

15

T2

34

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	554564	1			T1	56		T2	52		T3	48
values[0x0]	511875	1			T1	48		T2	68		T3	42
values[0x1]	556973	1			T1	44		T2	69		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1070767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

552645

1

T1

49

T2

70

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25377	1			T1	6		T2	8		T11	1
valid_sources[0x01]	25902	1			T2	5		T3	3		T7	11
valid_sources[0x02]	25873	1			T1	8		T3	7		T12	1
valid_sources[0x03]	25174	1			T1	11		T3	2		T10	1
valid_sources[0x04]	24916	1			T2	11		T3	4		T7	1
valid_sources[0x05]	25155	1			T3	8		T7	7		T12	1
valid_sources[0x06]	24719	1			T3	5		T7	4		T12	1
valid_sources[0x07]	26067	1			T3	1		T10	1		T13	9
valid_sources[0x08]	25141	1			T1	1		T2	16		T3	1
valid_sources[0x09]	24920	1			T2	1		T10	1		T14	1
valid_sources[0x0a]	25114	1			T1	20		T12	7		T13	7
valid_sources[0x0b]	25671	1			T3	1		T7	5		T12	1
valid_sources[0x0c]	25451	1			T2	26		T3	2		T7	3
valid_sources[0x0d]	25038	1			T3	3		T11	1		T12	2
valid_sources[0x0e]	25522	1			T1	2		T3	1		T7	2
valid_sources[0x0f]	25683	1			T1	5		T2	5		T3	4
valid_sources[0x10]	25363	1			T3	2		T12	3		T27	3
valid_sources[0x11]	26105	1			T1	3		T3	2		T10	1
valid_sources[0x12]	25480	1			T3	4		T7	5		T12	2
valid_sources[0x13]	25110	1			T1	3		T3	2		T10	1
valid_sources[0x14]	25401	1			T7	6		T12	2		T17	19
valid_sources[0x15]	25484	1			T2	6		T3	2		T10	1
valid_sources[0x16]	25521	1			T1	4		T2	17		T13	7
valid_sources[0x17]	25963	1			T3	1		T10	1		T11	1
valid_sources[0x18]	24997	1			T2	3		T3	2		T17	14
valid_sources[0x19]	25366	1			T1	14		T2	7		T3	1
valid_sources[0x1a]	24880	1			T1	2		T2	8		T12	2
valid_sources[0x1b]	25551	1			T3	2		T7	2		T12	1
valid_sources[0x1c]	25629	1			T2	12		T3	3		T10	1
valid_sources[0x1d]	25862	1			T3	3		T10	3		T7	2
valid_sources[0x1e]	26044	1			T3	4		T10	1		T17	24
valid_sources[0x1f]	24968	1			T1	2		T3	1		T12	1
valid_sources[0x20]	25167	1			T2	12		T3	2		T7	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23833

1

T1

1

T2

2

T3

2

values[0x0]

all_enables

biggest_size

180554

1

T1

12

T2

27

T3

18

values[0x1]

all_enables

biggest_size

23742

1

T1

2

T2

5

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1392951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

220909

1

T1

20

T2

30

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	548287	1			T1	41		T2	60		T3	33
values[0x0]	518580	1			T1	44		T2	55		T3	34
values[0x1]	546993	1			T1	43		T2	63		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1076141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

537719

1

T1

44

T2

74

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25275	1			T1	2		T2	3		T3	3
valid_sources[0x01]	25958	1			T2	2		T3	3		T12	2
valid_sources[0x02]	25486	1			T3	3		T12	2		T13	2
valid_sources[0x03]	25286	1			T2	2		T3	4		T7	5
valid_sources[0x04]	25164	1			T3	2		T7	8		T12	5
valid_sources[0x05]	25093	1			T2	3		T12	1		T13	2
valid_sources[0x06]	24974	1			T1	42		T2	3		T3	4
valid_sources[0x07]	25533	1			T2	7		T3	2		T12	5
valid_sources[0x08]	25315	1			T2	10		T3	1		T7	7
valid_sources[0x09]	25279	1			T3	2		T7	2		T12	1
valid_sources[0x0a]	25369	1			T1	16		T2	4		T3	1
valid_sources[0x0b]	24947	1			T3	2		T12	1		T13	9
valid_sources[0x0c]	25495	1			T1	10		T7	5		T12	3
valid_sources[0x0d]	25106	1			T2	1		T3	2		T7	4
valid_sources[0x0e]	25291	1			T2	7		T10	1		T7	2
valid_sources[0x0f]	25438	1			T2	3		T3	1		T12	1
valid_sources[0x10]	24750	1			T1	17		T3	1		T12	1
valid_sources[0x11]	25981	1			T10	3		T13	6		T15	5
valid_sources[0x12]	25078	1			T3	1		T7	2		T12	2
valid_sources[0x13]	24941	1			T3	2		T7	4		T13	4
valid_sources[0x14]	24913	1			T2	7		T3	1		T10	1
valid_sources[0x15]	25005	1			T10	2		T7	7		T12	1
valid_sources[0x16]	25370	1			T2	4		T3	2		T10	6
valid_sources[0x17]	25484	1			T3	3		T7	4		T12	3
valid_sources[0x18]	25406	1			T2	9		T3	1		T12	5
valid_sources[0x19]	24822	1			T2	1		T12	2		T13	7
valid_sources[0x1a]	24764	1			T2	4		T3	1		T12	2
valid_sources[0x1b]	25542	1			T2	3		T12	1		T13	7
valid_sources[0x1c]	25214	1			T1	5		T2	1		T12	2
valid_sources[0x1d]	25803	1			T2	7		T3	3		T7	1
valid_sources[0x1e]	24962	1			T2	1		T3	1		T10	4
valid_sources[0x1f]	25077	1			T2	8		T3	4		T12	5
valid_sources[0x20]	24291	1			T2	2		T3	2		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23134

1

T1

1

T2

5

T10

1

values[0x0]

all_enables

biggest_size

174712

1

T1

17

T2

23

T3

10

values[0x1]

all_enables

biggest_size

23063

1

T1

2

T2

2

T3

3