Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	6978178	0	0
GntImpliesValid_A	2147483647	6978178	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	6978178	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	448244364	0	0
ReadyAndValidImplyGrant_A	2147483647	6978178	0	0
ReqAndReadyImplyGrant_A	2147483647	6978178	0	0
ReqImpliesValid_A	2147483647	33016804	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	33764	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	6978178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44496	43608	0	0
T2	59208	57792	0	0
T3	42792	41976	0	0
T7	232608	232224	0	0
T10	62736	61104	0	0
T11	19176	18264	0	0
T12	34608	34368	0	0
T13	43632	43320	0	0
T14	15384	14784	0	0
T15	56520	55080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0
T14	24	24	0	0
T15	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44496	43608	0	0
T2	59208	57792	0	0
T3	42792	41976	0	0
T7	232608	232224	0	0
T10	62736	61104	0	0
T11	19176	18264	0	0
T12	34608	34368	0	0
T13	43632	43320	0	0
T14	15384	14784	0	0
T15	56520	55080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44496	43608	0	0
T2	59208	57792	0	0
T3	42792	41976	0	0
T7	232608	232224	0	0
T10	62736	61104	0	0
T11	19176	18264	0	0
T12	34608	34368	0	0
T13	43632	43320	0	0
T14	15384	14784	0	0
T15	56520	55080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448244364	0	0
T1	44496	505	0	0
T2	59208	774	0	0
T3	42792	515	0	0
T7	232608	11584	0	0
T10	62736	1205	0	0
T11	19176	283	0	0
T12	34608	396	0	0
T13	43632	489	0	0
T14	15384	234	0	0
T15	56520	728	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33016804	0	0
T1	44496	453	0	0
T2	59208	548	0	0
T3	42792	401	0	0
T7	232608	868	0	0
T10	62736	816	0	0
T11	19176	256	0	0
T12	34608	398	0	0
T13	43632	550	0	0
T14	15384	239	0	0
T15	56520	457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33764	0	21600
T8	8368	0	0	2
T9	36020	0	0	1
T11	799	1	0	1
T12	1442	0	0	1
T13	1818	0	0	1
T14	641	0	0	1
T15	2355	0	0	1
T16	1893	2	0	1
T17	9114	8	0	2
T18	11148	22	0	2
T19	9853	11	0	1
T20	12214	22	0	1
T21	28206	1	0	1
T22	17057	19	0	1
T23	0	34	0	0
T24	0	19	0	0
T25	0	25	0	0
T26	0	24	0	0
T27	2685	0	0	1
T28	9363	0	0	1
T29	3883	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	44496	43608	0	0
T2	59208	57792	0	0
T3	42792	41976	0	0
T7	232608	232224	0	0
T10	62736	61104	0	0
T11	19176	18264	0	0
T12	34608	34368	0	0
T13	43632	43320	0	0
T14	15384	14784	0	0
T15	56520	55080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6978178	0	0
T1	44496	405	0	0
T2	59208	473	0	0
T3	42792	346	0	0
T7	232608	428	0	0
T10	62736	656	0	0
T11	19176	219	0	0
T12	34608	363	0	0
T13	43632	501	0	0
T14	15384	220	0	0
T15	56520	405	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	782426	0	0
GntImpliesValid_A	409747991	782426	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	782426	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	11855625	0	0
ReadyAndValidImplyGrant_A	409747991	782426	0	0
ReqAndReadyImplyGrant_A	409747991	782426	0	0
ReqImpliesValid_A	409747991	2315650	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	782426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	11855625	0	0
T1	1854	40	0	0
T2	2467	49	0	0
T3	1783	29	0	0
T7	9692	351	0	0
T10	2614	64	0	0
T11	799	28	0	0
T12	1442	35	0	0
T13	1818	34	0	0
T14	641	30	0	0
T15	2355	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2315650	0	0
T1	1854	61	0	0
T2	2467	90	0	0
T3	1783	34	0	0
T7	9692	86	0	0
T10	2614	95	0	0
T11	799	49	0	0
T12	1442	54	0	0
T13	1818	67	0	0
T14	641	47	0	0
T15	2355	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	782426	0	0
T1	1854	50	0	0
T2	2467	69	0	0
T3	1783	31	0	0
T7	9692	52	0	0
T10	2614	79	0	0
T11	799	38	0	0
T12	1442	44	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	776389	0	0
GntImpliesValid_A	409747991	776389	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	776389	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	11986706	0	0
ReadyAndValidImplyGrant_A	409747991	776389	0	0
ReqAndReadyImplyGrant_A	409747991	776389	0	0
ReqImpliesValid_A	409747991	2395046	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	776389	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	11986706	0	0
T1	1854	42	0	0
T2	2467	43	0	0
T3	1783	29	0	0
T7	9692	506	0	0
T10	2614	71	0	0
T11	799	21	0	0
T12	1442	24	0	0
T13	1818	38	0	0
T14	641	31	0	0
T15	2355	30	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2395046	0	0
T1	1854	65	0	0
T2	2467	62	0	0
T3	1783	58	0	0
T7	9692	71	0	0
T10	2614	92	0	0
T11	799	30	0	0
T12	1442	29	0	0
T13	1818	63	0	0
T14	641	46	0	0
T15	2355	47	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	776389	0	0
T1	1854	53	0	0
T2	2467	52	0	0
T3	1783	43	0	0
T7	9692	49	0	0
T10	2614	81	0	0
T11	799	25	0	0
T12	1442	26	0	0
T13	1818	50	0	0
T14	641	38	0	0
T15	2355	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	191005	0	0
GntImpliesValid_A	409747991	191005	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	191005	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2954182	0	0
ReadyAndValidImplyGrant_A	409747991	191005	0	0
ReqAndReadyImplyGrant_A	409747991	191005	0	0
ReqImpliesValid_A	409747991	555004	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	191005	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2954182	0	0
T1	1854	12	0	0
T2	2467	9	0	0
T3	1783	9	0	0
T7	9692	89	0	0
T10	2614	13	0	0
T11	799	8	0	0
T12	1442	9	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	555004	0	0
T1	1854	13	0	0
T2	2467	8	0	0
T3	1783	10	0	0
T7	9692	21	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191005	0	0
T1	1854	12	0	0
T2	2467	8	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	12	0	0
T11	799	7	0	0
T12	1442	8	0	0
T13	1818	11	0	0
T14	641	4	0	0
T15	2355	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	198950	0	0
GntImpliesValid_A	409747991	198950	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	198950	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3016048	0	0
ReadyAndValidImplyGrant_A	409747991	198950	0	0
ReqAndReadyImplyGrant_A	409747991	198950	0	0
ReqImpliesValid_A	409747991	559794	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	198950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3016048	0	0
T1	1854	8	0	0
T2	2467	11	0	0
T3	1783	16	0	0
T7	9692	72	0	0
T10	2614	17	0	0
T11	799	4	0	0
T12	1442	9	0	0
T13	1818	16	0	0
T14	641	6	0	0
T15	2355	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	559794	0	0
T1	1854	7	0	0
T2	2467	12	0	0
T3	1783	15	0	0
T7	9692	19	0	0
T10	2614	22	0	0
T11	799	3	0	0
T12	1442	12	0	0
T13	1818	21	0	0
T14	641	7	0	0
T15	2355	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	198950	0	0
T1	1854	7	0	0
T2	2467	11	0	0
T3	1783	15	0	0
T7	9692	9	0	0
T10	2614	19	0	0
T11	799	3	0	0
T12	1442	10	0	0
T13	1818	18	0	0
T14	641	6	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	185563	0	0
GntImpliesValid_A	409747991	185563	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	185563	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	4534218	0	0
ReadyAndValidImplyGrant_A	409747991	185563	0	0
ReqAndReadyImplyGrant_A	409747991	185563	0	0
ReqImpliesValid_A	409747991	941096	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	185563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	4534218	0	0
T1	1854	105	0	0
T2	2467	69	0	0
T3	1783	34	0	0
T7	9692	82	0	0
T10	2614	155	0	0
T11	799	37	0	0
T12	1442	28	0	0
T13	1818	46	0	0
T14	641	14	0	0
T15	2355	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	941096	0	0
T1	1854	22	0	0
T2	2467	10	0	0
T3	1783	14	0	0
T7	9692	15	0	0
T10	2614	37	0	0
T11	799	19	0	0
T12	1442	6	0	0
T13	1818	18	0	0
T14	641	4	0	0
T15	2355	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	185563	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	5	0	0
T7	9692	15	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	6	0	0
T13	1818	13	0	0
T14	641	4	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T10 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	186397	0	0
GntImpliesValid_A	409747991	186397	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	186397	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	5393793	0	0
ReadyAndValidImplyGrant_A	409747991	186397	0	0
ReqAndReadyImplyGrant_A	409747991	186397	0	0
ReqImpliesValid_A	409747991	1162650	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	186397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	5393793	0	0
T1	1854	50	0	0
T2	2467	39	0	0
T3	1783	31	0	0
T7	9692	86	0	0
T10	2614	319	0	0
T11	799	34	0	0
T12	1442	43	0	0
T13	1818	41	0	0
T14	641	19	0	0
T15	2355	112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	1162650	0	0
T1	1854	16	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	61	0	0
T11	799	5	0	0
T12	1442	24	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	186397	0	0
T1	1854	12	0	0
T2	2467	7	0	0
T3	1783	6	0	0
T7	9692	12	0	0
T10	2614	16	0	0
T11	799	5	0	0
T12	1442	14	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	194350	0	0
GntImpliesValid_A	409747991	194350	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	194350	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	4905863	0	0
ReadyAndValidImplyGrant_A	409747991	194350	0	0
ReqAndReadyImplyGrant_A	409747991	194350	0	0
ReqImpliesValid_A	409747991	1208342	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	194350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	4905863	0	0
T1	1854	66	0	0
T2	2467	168	0	0
T3	1783	182	0	0
T7	9692	82	0	0
T10	2614	186	0	0
T11	799	17	0	0
T12	1442	28	0	0
T13	1818	56	0	0
T14	641	10	0	0
T15	2355	173	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	1208342	0	0
T1	1854	18	0	0
T2	2467	10	0	0
T3	1783	29	0	0
T7	9692	9	0	0
T10	2614	55	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	16	0	0
T14	641	2	0	0
T15	2355	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	194350	0	0
T1	1854	12	0	0
T2	2467	10	0	0
T3	1783	13	0	0
T7	9692	9	0	0
T10	2614	18	0	0
T11	799	3	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	2	0	0
T15	2355	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	191556	0	0
GntImpliesValid_A	409747991	191556	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	191556	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	5124816	0	0
ReadyAndValidImplyGrant_A	409747991	191556	0	0
ReqAndReadyImplyGrant_A	409747991	191556	0	0
ReqImpliesValid_A	409747991	1054686	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	191556	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	5124816	0	0
T1	1854	23	0	0
T2	2467	197	0	0
T3	1783	40	0	0
T7	9692	93	0	0
T10	2614	125	0	0
T11	799	42	0	0
T12	1442	42	0	0
T13	1818	42	0	0
T14	641	24	0	0
T15	2355	104	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	1054686	0	0
T1	1854	5	0	0
T2	2467	47	0	0
T3	1783	13	0	0
T7	9692	18	0	0
T10	2614	40	0	0
T11	799	18	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	191556	0	0
T1	1854	5	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	10	0	0
T10	2614	20	0	0
T11	799	10	0	0
T12	1442	9	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	188526	0	0
GntImpliesValid_A	409747991	188526	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	188526	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2919927	0	0
ReadyAndValidImplyGrant_A	409747991	188526	0	0
ReqAndReadyImplyGrant_A	409747991	188526	0	0
ReqImpliesValid_A	409747991	513566	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	188526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2919927	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	60	0	0
T10	2614	22	0	0
T11	799	7	0	0
T12	1442	14	0	0
T13	1818	17	0	0
T14	641	5	0	0
T15	2355	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	513566	0	0
T1	1854	12	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	25	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	18	0	0
T14	641	4	0	0
T15	2355	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	188526	0	0
T1	1854	11	0	0
T2	2467	13	0	0
T3	1783	11	0	0
T7	9692	11	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	13	0	0
T13	1818	17	0	0
T14	641	4	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T10 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T10,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	193845	0	0
GntImpliesValid_A	409747991	193845	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	193845	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2946475	0	0
ReadyAndValidImplyGrant_A	409747991	193845	0	0
ReqAndReadyImplyGrant_A	409747991	193845	0	0
ReqImpliesValid_A	409747991	519181	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	193845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2946475	0	0
T1	1854	15	0	0
T2	2467	15	0	0
T3	1783	13	0	0
T7	9692	110	0	0
T10	2614	17	0	0
T11	799	7	0	0
T12	1442	9	0	0
T13	1818	14	0	0
T14	641	7	0	0
T15	2355	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	519181	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	14	0	0
T7	9692	24	0	0
T10	2614	18	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	193845	0	0
T1	1854	14	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	13	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	8	0	0
T13	1818	13	0	0
T14	641	6	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T7 T27 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T27
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T27

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T27
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	200057	0	0
GntImpliesValid_A	409747991	200057	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	200057	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2985693	0	0
ReadyAndValidImplyGrant_A	409747991	200057	0	0
ReqAndReadyImplyGrant_A	409747991	200057	0	0
ReqImpliesValid_A	409747991	595527	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	200057	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2985693	0	0
T1	1854	13	0	0
T2	2467	16	0	0
T3	1783	8	0	0
T7	9692	110	0	0
T10	2614	20	0	0
T11	799	5	0	0
T12	1442	7	0	0
T13	1818	18	0	0
T14	641	7	0	0
T15	2355	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	595527	0	0
T1	1854	14	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	34	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200057	0	0
T1	1854	13	0	0
T2	2467	15	0	0
T3	1783	7	0	0
T7	9692	12	0	0
T10	2614	19	0	0
T11	799	4	0	0
T12	1442	6	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T11 T27 T16 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T27,T16
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T27,T16

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T27,T16
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	190992	0	0
GntImpliesValid_A	409747991	190992	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	190992	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2992308	0	0
ReadyAndValidImplyGrant_A	409747991	190992	0	0
ReqAndReadyImplyGrant_A	409747991	190992	0	0
ReqImpliesValid_A	409747991	538076	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	190992	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2992308	0	0
T1	1854	13	0	0
T2	2467	16	0	0
T3	1783	11	0	0
T7	9692	66	0	0
T10	2614	13	0	0
T11	799	5	0	0
T12	1442	12	0	0
T13	1818	17	0	0
T14	641	9	0	0
T15	2355	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	538076	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	6	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190992	0	0
T1	1854	12	0	0
T2	2467	15	0	0
T3	1783	10	0	0
T7	9692	8	0	0
T10	2614	12	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	16	0	0
T14	641	8	0	0
T15	2355	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T27 T16 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T16
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T27,T16

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T27,T16
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	202022	0	0
GntImpliesValid_A	409747991	202022	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	202022	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3063759	0	0
ReadyAndValidImplyGrant_A	409747991	202022	0	0
ReqAndReadyImplyGrant_A	409747991	202022	0	0
ReqImpliesValid_A	409747991	583054	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	202022	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3063759	0	0
T1	1854	6	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	122	0	0
T10	2614	14	0	0
T11	799	3	0	0
T12	1442	16	0	0
T13	1818	14	0	0
T14	641	6	0	0
T15	2355	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	583054	0	0
T1	1854	5	0	0
T2	2467	14	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	202022	0	0
T1	1854	5	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	2	0	0
T12	1442	15	0	0
T13	1818	13	0	0
T14	641	5	0	0
T15	2355	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T16 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T16
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T16

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T16
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	190771	0	0
GntImpliesValid_A	409747991	190771	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	190771	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2955239	0	0
ReadyAndValidImplyGrant_A	409747991	190771	0	0
ReqAndReadyImplyGrant_A	409747991	190771	0	0
ReqImpliesValid_A	409747991	556438	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	190771	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2955239	0	0
T1	1854	9	0	0
T2	2467	12	0	0
T3	1783	10	0	0
T7	9692	88	0	0
T10	2614	17	0	0
T11	799	7	0	0
T12	1442	7	0	0
T13	1818	17	0	0
T14	641	6	0	0
T15	2355	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	556438	0	0
T1	1854	8	0	0
T2	2467	13	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	18	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190771	0	0
T1	1854	8	0	0
T2	2467	12	0	0
T3	1783	9	0	0
T7	9692	12	0	0
T10	2614	17	0	0
T11	799	6	0	0
T12	1442	6	0	0
T13	1818	16	0	0
T14	641	5	0	0
T15	2355	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	182958	0	0
GntImpliesValid_A	409747991	182958	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	182958	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3016443	0	0
ReadyAndValidImplyGrant_A	409747991	182958	0	0
ReqAndReadyImplyGrant_A	409747991	182958	0	0
ReqImpliesValid_A	409747991	491106	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	182958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3016443	0	0
T1	1854	16	0	0
T2	2467	15	0	0
T3	1783	9	0	0
T7	9692	92	0	0
T10	2614	19	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	17	0	0
T14	641	5	0	0
T15	2355	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	491106	0	0
T1	1854	15	0	0
T2	2467	20	0	0
T3	1783	10	0	0
T7	9692	14	0	0
T10	2614	18	0	0
T11	799	10	0	0
T12	1442	15	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	182958	0	0
T1	1854	15	0	0
T2	2467	17	0	0
T3	1783	9	0	0
T7	9692	13	0	0
T10	2614	18	0	0
T11	799	9	0	0
T12	1442	14	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T10 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T10,T7
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	192604	0	0
GntImpliesValid_A	409747991	192604	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	192604	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2920505	0	0
ReadyAndValidImplyGrant_A	409747991	192604	0	0
ReqAndReadyImplyGrant_A	409747991	192604	0	0
ReqImpliesValid_A	409747991	568064	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	192604	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2920505	0	0
T1	1854	7	0	0
T2	2467	15	0	0
T3	1783	8	0	0
T7	9692	104	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	11	0	0
T13	1818	15	0	0
T14	641	8	0	0
T15	2355	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	568064	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	9	0	0
T7	9692	11	0	0
T10	2614	18	0	0
T11	799	6	0	0
T12	1442	10	0	0
T13	1818	16	0	0
T14	641	7	0	0
T15	2355	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	192604	0	0
T1	1854	6	0	0
T2	2467	14	0	0
T3	1783	8	0	0
T7	9692	10	0	0
T10	2614	17	0	0
T11	799	5	0	0
T12	1442	10	0	0
T13	1818	15	0	0
T14	641	7	0	0
T15	2355	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T10 T13 T14 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T14
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T13,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T13,T14
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	204770	0	0
GntImpliesValid_A	409747991	204770	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	204770	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3034335	0	0
ReadyAndValidImplyGrant_A	409747991	204770	0	0
ReqAndReadyImplyGrant_A	409747991	204770	0	0
ReqImpliesValid_A	409747991	568552	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	204770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3034335	0	0
T1	1854	11	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	113	0	0
T10	2614	26	0	0
T11	799	9	0	0
T12	1442	7	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	568552	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	33	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	11	0	0
T14	641	11	0	0
T15	2355	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	204770	0	0
T1	1854	10	0	0
T2	2467	13	0	0
T3	1783	10	0	0
T7	9692	15	0	0
T10	2614	29	0	0
T11	799	8	0	0
T12	1442	6	0	0
T13	1818	10	0	0
T14	641	10	0	0
T15	2355	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	183871	0	0
GntImpliesValid_A	409747991	183871	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	183871	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2995426	0	0
ReadyAndValidImplyGrant_A	409747991	183871	0	0
ReqAndReadyImplyGrant_A	409747991	183871	0	0
ReqImpliesValid_A	409747991	531020	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	183871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2995426	0	0
T1	1854	9	0	0
T2	2467	15	0	0
T3	1783	11	0	0
T7	9692	107	0	0
T10	2614	13	0	0
T11	799	4	0	0
T12	1442	15	0	0
T13	1818	12	0	0
T14	641	8	0	0
T15	2355	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	531020	0	0
T1	1854	12	0	0
T2	2467	14	0	0
T3	1783	12	0	0
T7	9692	13	0	0
T10	2614	14	0	0
T11	799	3	0	0
T12	1442	16	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	183871	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	11	0	0
T7	9692	13	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	11	0	0
T14	641	7	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	196402	0	0
GntImpliesValid_A	409747991	196402	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	196402	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3044296	0	0
ReadyAndValidImplyGrant_A	409747991	196402	0	0
ReqAndReadyImplyGrant_A	409747991	196402	0	0
ReqImpliesValid_A	409747991	545577	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	196402	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3044296	0	0
T1	1854	11	0	0
T2	2467	14	0	0
T3	1783	14	0	0
T7	9692	108	0	0
T10	2614	17	0	0
T11	799	8	0	0
T12	1442	15	0	0
T13	1818	7	0	0
T14	641	3	0	0
T15	2355	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	545577	0	0
T1	1854	10	0	0
T2	2467	15	0	0
T3	1783	13	0	0
T7	9692	26	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	16	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	196402	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	13	0	0
T7	9692	17	0	0
T10	2614	16	0	0
T11	799	7	0	0
T12	1442	15	0	0
T13	1818	6	0	0
T14	641	2	0	0
T15	2355	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	187633	0	0
GntImpliesValid_A	409747991	187633	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	187633	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2990221	0	0
ReadyAndValidImplyGrant_A	409747991	187633	0	0
ReqAndReadyImplyGrant_A	409747991	187633	0	0
ReqImpliesValid_A	409747991	503506	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	187633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2990221	0	0
T1	1854	14	0	0
T2	2467	7	0	0
T3	1783	12	0	0
T7	9692	61	0	0
T10	2614	14	0	0
T11	799	4	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	5	0	0
T15	2355	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	503506	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	13	0	0
T7	9692	14	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	16	0	0
T13	1818	16	0	0
T14	641	4	0	0
T15	2355	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	187633	0	0
T1	1854	13	0	0
T2	2467	6	0	0
T3	1783	12	0	0
T7	9692	8	0	0
T10	2614	13	0	0
T11	799	3	0	0
T12	1442	15	0	0
T13	1818	15	0	0
T14	641	4	0	0
T15	2355	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T27 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T27
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T27

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T27
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	190478	0	0
GntImpliesValid_A	409747991	190478	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	190478	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	2921353	0	0
ReadyAndValidImplyGrant_A	409747991	190478	0	0
ReqAndReadyImplyGrant_A	409747991	190478	0	0
ReqImpliesValid_A	409747991	502252	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	190478	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2921353	0	0
T1	1854	11	0	0
T2	2467	10	0	0
T3	1783	11	0	0
T7	9692	129	0	0
T10	2614	20	0	0
T11	799	7	0	0
T12	1442	20	0	0
T13	1818	18	0	0
T14	641	8	0	0
T15	2355	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	502252	0	0
T1	1854	10	0	0
T2	2467	11	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	21	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	190478	0	0
T1	1854	10	0	0
T2	2467	10	0	0
T3	1783	10	0	0
T7	9692	16	0	0
T10	2614	20	0	0
T11	799	6	0	0
T12	1442	19	0	0
T13	1818	17	0	0
T14	641	7	0	0
T15	2355	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T13 T16 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T13,T16

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T13,T16
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	200343	0	0
GntImpliesValid_A	409747991	200343	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	200343	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	3063863	0	0
ReadyAndValidImplyGrant_A	409747991	200343	0	0
ReqAndReadyImplyGrant_A	409747991	200343	0	0
ReqImpliesValid_A	409747991	555266	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	0	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	200343	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	3063863	0	0
T1	1854	11	0	0
T2	2467	12	0	0
T3	1783	5	0	0
T7	9692	124	0	0
T10	2614	24	0	0
T11	799	10	0	0
T12	1442	14	0	0
T13	1818	11	0	0
T14	641	6	0	0
T15	2355	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	555266	0	0
T1	1854	10	0	0
T2	2467	17	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	12	0	0
T14	641	5	0	0
T15	2355	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	200343	0	0
T1	1854	10	0	0
T2	2467	14	0	0
T3	1783	4	0	0
T7	9692	15	0	0
T10	2614	23	0	0
T11	799	9	0	0
T12	1442	13	0	0
T13	1818	11	0	0
T14	641	5	0	0
T15	2355	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	789185	0	0
GntImpliesValid_A	409747991	789185	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	789185	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	11398496	0	0
ReadyAndValidImplyGrant_A	409747991	789185	0	0
ReqAndReadyImplyGrant_A	409747991	789185	0	0
ReqImpliesValid_A	409747991	2267649	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	16185	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	789185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	11398496	0	0
T1	1854	1	0	0
T2	2467	1	0	0
T3	1783	1	0	0
T7	9692	335	0	0
T10	2614	1	0	0
T11	799	1	0	0
T12	1442	1	0	0
T13	1818	1	0	0
T14	641	1	0	0
T15	2355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	2267649	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	55	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	16185	0	900
T8	4184	0	0	1
T11	799	1	0	1
T12	1442	0	0	1
T13	1818	0	0	1
T14	641	0	0	1
T15	2355	0	0	1
T16	1893	2	0	1
T17	4557	5	0	1
T18	5574	11	0	1
T19	0	7	0	0
T20	0	9	0	0
T22	0	13	0	0
T23	0	20	0	0
T24	0	10	0	0
T25	0	16	0	0
T27	2685	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	789185	0	0
T1	1854	42	0	0
T2	2467	53	0	0
T3	1783	41	0	0
T7	9692	42	0	0
T10	2614	72	0	0
T11	799	22	0	0
T12	1442	43	0	0
T13	1818	69	0	0
T14	641	16	0	0
T15	2355	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409747991	409634650	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	409747991	777085	0	0
GntImpliesValid_A	409747991	777085	0	0
GrantKnown_A	409747991	409634650	0	0
IdxKnown_A	409747991	409634650	0	0
IndexIsCorrect_A	409747991	777085	0	0
LockArbDecision_A	409747991	0	0	0
NoReadyValidNoGrant_A	409747991	345224774	0	0
ReadyAndValidImplyGrant_A	409747991	777085	0	0
ReqAndReadyImplyGrant_A	409747991	777085	0	0
ReqImpliesValid_A	409747991	12985702	0	0
ReqStaysHighUntilGranted0_M	409747991	0	0	0
RoundRobin_A	409747991	17579	0	900
ValidKnown_A	409747991	409634650	0	0
gen_data_port_assertion.DataFlow_A	409747991	777085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	345224774	0	0
T1	1854	1	0	0
T2	2467	1	0	0
T3	1783	1	0	0
T7	9692	8494	0	0
T10	2614	1	0	0
T11	799	1	0	0
T12	1442	1	0	0
T13	1818	1	0	0
T14	641	1	0	0
T15	2355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	12985702	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	321	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	17579	0	900
T8	4184	0	0	1
T9	36020	0	0	1
T17	4557	3	0	1
T18	5574	11	0	1
T19	9853	4	0	1
T20	12214	13	0	1
T21	28206	1	0	1
T22	17057	6	0	1
T23	0	14	0	0
T24	0	9	0	0
T25	0	9	0	0
T26	0	24	0	0
T28	9363	0	0	1
T29	3883	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	409634650	0	0
T1	1854	1817	0	0
T2	2467	2408	0	0
T3	1783	1749	0	0
T7	9692	9676	0	0
T10	2614	2546	0	0
T11	799	761	0	0
T12	1442	1432	0	0
T13	1818	1805	0	0
T14	641	616	0	0
T15	2355	2295	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409747991	777085	0	0
T1	1854	53	0	0
T2	2467	54	0	0
T3	1783	38	0	0
T7	9692	39	0	0
T10	2614	73	0	0
T11	799	18	0	0
T12	1442	30	0	0
T13	1818	62	0	0
T14	641	22	0	0
T15	2355	30	0	0