| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.02 | 99.26 | 88.92 | 98.80 | 95.88 | 99.28 | 100.00 |
| T777 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2249060772 | Oct 02 06:50:28 PM UTC 24 | Oct 02 06:50:32 PM UTC 24 | 26590072 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.820333863 | Oct 02 06:49:10 PM UTC 24 | Oct 02 06:50:33 PM UTC 24 | 1992325978 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2277500310 | Oct 02 06:47:45 PM UTC 24 | Oct 02 06:50:34 PM UTC 24 | 34908322169 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1156309630 | Oct 02 06:50:01 PM UTC 24 | Oct 02 06:50:36 PM UTC 24 | 6526216149 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4187787560 | Oct 02 06:49:24 PM UTC 24 | Oct 02 06:50:38 PM UTC 24 | 8136825179 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.474110481 | Oct 02 06:50:23 PM UTC 24 | Oct 02 06:50:39 PM UTC 24 | 132979391 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.904375167 | Oct 02 06:50:06 PM UTC 24 | Oct 02 06:50:42 PM UTC 24 | 1429510153 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2112564773 | Oct 02 06:50:23 PM UTC 24 | Oct 02 06:50:43 PM UTC 24 | 513700698 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.464411242 | Oct 02 06:48:10 PM UTC 24 | Oct 02 06:50:44 PM UTC 24 | 6443896091 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.265608640 | Oct 02 06:50:04 PM UTC 24 | Oct 02 06:50:45 PM UTC 24 | 15072085458 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3336924394 | Oct 02 06:50:46 PM UTC 24 | Oct 02 06:50:58 PM UTC 24 | 121152548 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2135076248 | Oct 02 06:50:47 PM UTC 24 | Oct 02 06:50:59 PM UTC 24 | 151648635 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2846635391 | Oct 02 06:49:14 PM UTC 24 | Oct 02 06:51:00 PM UTC 24 | 9350885503 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3983452217 | Oct 02 06:50:36 PM UTC 24 | Oct 02 06:51:01 PM UTC 24 | 153460382 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2286764985 | Oct 02 06:50:40 PM UTC 24 | Oct 02 06:51:03 PM UTC 24 | 180600544 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1639989410 | Oct 02 06:48:16 PM UTC 24 | Oct 02 06:51:04 PM UTC 24 | 1878991430 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1616386051 | Oct 02 06:50:11 PM UTC 24 | Oct 02 06:51:05 PM UTC 24 | 8413554712 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1012705009 | Oct 02 06:43:25 PM UTC 24 | Oct 02 06:51:07 PM UTC 24 | 91266176659 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.339755376 | Oct 02 06:50:23 PM UTC 24 | Oct 02 06:51:08 PM UTC 24 | 1764900614 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1920647156 | Oct 02 06:51:04 PM UTC 24 | Oct 02 06:51:08 PM UTC 24 | 28612332 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.902168450 | Oct 02 06:41:30 PM UTC 24 | Oct 02 06:51:08 PM UTC 24 | 98327786961 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1119478710 | Oct 02 06:51:05 PM UTC 24 | Oct 02 06:51:09 PM UTC 24 | 31374561 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1802329583 | Oct 02 06:50:43 PM UTC 24 | Oct 02 06:51:10 PM UTC 24 | 1277724020 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3705304146 | Oct 02 06:50:45 PM UTC 24 | Oct 02 06:51:14 PM UTC 24 | 267454948 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.786292108 | Oct 02 06:48:36 PM UTC 24 | Oct 02 06:51:17 PM UTC 24 | 1237807079 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1292961669 | Oct 02 06:44:16 PM UTC 24 | Oct 02 06:51:19 PM UTC 24 | 2355570844 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.208698521 | Oct 02 06:50:29 PM UTC 24 | Oct 02 06:51:19 PM UTC 24 | 6189161364 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.690364348 | Oct 02 06:50:33 PM UTC 24 | Oct 02 06:51:20 PM UTC 24 | 785235863 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1144461917 | Oct 02 06:50:33 PM UTC 24 | Oct 02 06:51:23 PM UTC 24 | 17459030971 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3261022514 | Oct 02 06:47:12 PM UTC 24 | Oct 02 06:51:25 PM UTC 24 | 7482087805 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.826986849 | Oct 02 06:51:11 PM UTC 24 | Oct 02 06:51:25 PM UTC 24 | 146998459 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.612516445 | Oct 02 06:49:10 PM UTC 24 | Oct 02 06:51:26 PM UTC 24 | 521355231 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3724801804 | Oct 02 06:50:25 PM UTC 24 | Oct 02 06:51:26 PM UTC 24 | 72491756 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.403164825 | Oct 02 06:44:16 PM UTC 24 | Oct 02 06:51:27 PM UTC 24 | 1684112289 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2541057737 | Oct 02 06:51:30 PM UTC 24 | Oct 02 06:51:35 PM UTC 24 | 49148265 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1788455230 | Oct 02 06:51:30 PM UTC 24 | Oct 02 06:51:35 PM UTC 24 | 113910443 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2915624298 | Oct 02 06:51:12 PM UTC 24 | Oct 02 06:51:36 PM UTC 24 | 256865860 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3435972729 | Oct 02 06:47:09 PM UTC 24 | Oct 02 06:51:36 PM UTC 24 | 693951831 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.796917167 | Oct 02 06:51:22 PM UTC 24 | Oct 02 06:51:39 PM UTC 24 | 134574356 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1860419061 | Oct 02 06:48:01 PM UTC 24 | Oct 02 06:51:40 PM UTC 24 | 27909941952 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2428448831 | Oct 02 06:51:18 PM UTC 24 | Oct 02 06:51:40 PM UTC 24 | 253983709 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4149140809 | Oct 02 06:51:20 PM UTC 24 | Oct 02 06:51:40 PM UTC 24 | 820951496 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3010217846 | Oct 02 06:51:07 PM UTC 24 | Oct 02 06:51:43 PM UTC 24 | 7145386622 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1749611984 | Oct 02 06:47:22 PM UTC 24 | Oct 02 06:51:45 PM UTC 24 | 53206501141 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2427579884 | Oct 02 06:51:13 PM UTC 24 | Oct 02 06:51:48 PM UTC 24 | 709965752 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2822466182 | Oct 02 06:51:22 PM UTC 24 | Oct 02 06:51:50 PM UTC 24 | 519365056 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4091575279 | Oct 02 06:50:36 PM UTC 24 | Oct 02 06:51:55 PM UTC 24 | 8755417481 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3856555551 | Oct 02 06:51:49 PM UTC 24 | Oct 02 06:51:57 PM UTC 24 | 124802830 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2916816887 | Oct 02 06:48:14 PM UTC 24 | Oct 02 06:51:58 PM UTC 24 | 605799140 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2476075277 | Oct 02 06:50:23 PM UTC 24 | Oct 02 06:52:00 PM UTC 24 | 1499633951 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1474919351 | Oct 02 06:50:26 PM UTC 24 | Oct 02 06:52:01 PM UTC 24 | 750140532 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3141353145 | Oct 02 06:51:45 PM UTC 24 | Oct 02 06:52:06 PM UTC 24 | 603139872 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1656499351 | Oct 02 06:52:03 PM UTC 24 | Oct 02 06:52:08 PM UTC 24 | 21492354 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1854535651 | Oct 02 06:47:22 PM UTC 24 | Oct 02 06:52:08 PM UTC 24 | 46884257858 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.4108643560 | Oct 02 06:51:36 PM UTC 24 | Oct 02 06:52:08 PM UTC 24 | 3472563449 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4024371401 | Oct 02 06:51:39 PM UTC 24 | Oct 02 06:52:08 PM UTC 24 | 226082269 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.635960244 | Oct 02 06:51:52 PM UTC 24 | Oct 02 06:52:09 PM UTC 24 | 1119438841 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1611858240 | Oct 02 06:48:41 PM UTC 24 | Oct 02 06:52:10 PM UTC 24 | 16831944853 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1874179038 | Oct 02 06:52:07 PM UTC 24 | Oct 02 06:52:11 PM UTC 24 | 59221466 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.340153163 | Oct 02 06:51:24 PM UTC 24 | Oct 02 06:52:13 PM UTC 24 | 1399540775 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3738158441 | Oct 02 06:51:08 PM UTC 24 | Oct 02 06:52:13 PM UTC 24 | 20100656798 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4213783155 | Oct 02 06:51:39 PM UTC 24 | Oct 02 06:52:16 PM UTC 24 | 236869371 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.71755907 | Oct 02 06:51:46 PM UTC 24 | Oct 02 06:52:17 PM UTC 24 | 2827532892 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2774053125 | Oct 02 06:47:50 PM UTC 24 | Oct 02 06:52:19 PM UTC 24 | 33321057470 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.604032157 | Oct 02 06:48:26 PM UTC 24 | Oct 02 06:52:20 PM UTC 24 | 85740389631 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1610427736 | Oct 02 06:47:34 PM UTC 24 | Oct 02 06:52:23 PM UTC 24 | 2353183090 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3302606598 | Oct 02 06:42:52 PM UTC 24 | Oct 02 06:52:24 PM UTC 24 | 81078598840 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2446009925 | Oct 02 06:52:16 PM UTC 24 | Oct 02 06:52:25 PM UTC 24 | 264319152 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1398100644 | Oct 02 06:50:17 PM UTC 24 | Oct 02 06:52:25 PM UTC 24 | 21216398457 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.31139359 | Oct 02 06:46:31 PM UTC 24 | Oct 02 06:52:26 PM UTC 24 | 733641284 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.223140584 | Oct 02 06:51:12 PM UTC 24 | Oct 02 06:52:27 PM UTC 24 | 16964450622 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2074503079 | Oct 02 06:51:36 PM UTC 24 | Oct 02 06:52:29 PM UTC 24 | 14159108967 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3474352266 | Oct 02 06:52:26 PM UTC 24 | Oct 02 06:52:30 PM UTC 24 | 43221369 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.322233558 | Oct 02 06:52:19 PM UTC 24 | Oct 02 06:52:32 PM UTC 24 | 57503033 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1151983758 | Oct 02 06:52:29 PM UTC 24 | Oct 02 06:52:33 PM UTC 24 | 50022444 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2043101514 | Oct 02 06:52:11 PM UTC 24 | Oct 02 06:52:36 PM UTC 24 | 164433618 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.697719231 | Oct 02 06:52:11 PM UTC 24 | Oct 02 06:52:37 PM UTC 24 | 207380381 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3669019291 | Oct 02 06:48:03 PM UTC 24 | Oct 02 06:52:37 PM UTC 24 | 48636113817 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3343865630 | Oct 02 06:52:21 PM UTC 24 | Oct 02 06:52:39 PM UTC 24 | 170864851 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.674835441 | Oct 02 06:52:11 PM UTC 24 | Oct 02 06:52:39 PM UTC 24 | 4527761354 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1711141554 | Oct 02 06:51:02 PM UTC 24 | Oct 02 06:52:40 PM UTC 24 | 1240360667 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3020309120 | Oct 02 06:52:40 PM UTC 24 | Oct 02 06:52:44 PM UTC 24 | 155662968 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2073315576 | Oct 02 06:49:47 PM UTC 24 | Oct 02 06:52:44 PM UTC 24 | 2073903213 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3487446885 | Oct 02 06:52:17 PM UTC 24 | Oct 02 06:52:45 PM UTC 24 | 164345869 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2605155134 | Oct 02 06:52:38 PM UTC 24 | Oct 02 06:52:45 PM UTC 24 | 148626659 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3592129448 | Oct 02 06:52:11 PM UTC 24 | Oct 02 06:52:46 PM UTC 24 | 6021643715 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1422724234 | Oct 02 06:42:57 PM UTC 24 | Oct 02 06:52:47 PM UTC 24 | 18758078721 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3135140562 | Oct 02 06:52:32 PM UTC 24 | Oct 02 06:52:52 PM UTC 24 | 393813282 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3050327784 | Oct 02 06:52:40 PM UTC 24 | Oct 02 06:52:55 PM UTC 24 | 573587160 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1323915521 | Oct 02 06:49:50 PM UTC 24 | Oct 02 06:52:55 PM UTC 24 | 5439351550 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2984091639 | Oct 02 06:52:00 PM UTC 24 | Oct 02 06:52:57 PM UTC 24 | 4778596008 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3677925440 | Oct 02 06:51:43 PM UTC 24 | Oct 02 06:52:58 PM UTC 24 | 2213292969 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3351535715 | Oct 02 06:52:34 PM UTC 24 | Oct 02 06:53:00 PM UTC 24 | 172886423 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.980938542 | Oct 02 06:51:30 PM UTC 24 | Oct 02 06:53:01 PM UTC 24 | 6511074836 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3346230912 | Oct 02 06:52:45 PM UTC 24 | Oct 02 06:53:02 PM UTC 24 | 209897932 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.700486406 | Oct 02 06:52:14 PM UTC 24 | Oct 02 06:53:07 PM UTC 24 | 2922719817 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2857007688 | Oct 02 06:46:39 PM UTC 24 | Oct 02 06:53:08 PM UTC 24 | 44631613544 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1931770150 | Oct 02 06:52:21 PM UTC 24 | Oct 02 06:53:08 PM UTC 24 | 375564770 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1006004006 | Oct 02 06:52:29 PM UTC 24 | Oct 02 06:53:11 PM UTC 24 | 20458483796 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.761375363 | Oct 02 06:52:48 PM UTC 24 | Oct 02 06:53:19 PM UTC 24 | 1119805960 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3144210228 | Oct 02 06:52:42 PM UTC 24 | Oct 02 06:53:22 PM UTC 24 | 851590924 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.367457705 | Oct 02 06:45:38 PM UTC 24 | Oct 02 06:53:23 PM UTC 24 | 3402217726 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1387736782 | Oct 02 06:52:48 PM UTC 24 | Oct 02 06:53:24 PM UTC 24 | 61599171 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3224937638 | Oct 02 06:52:38 PM UTC 24 | Oct 02 06:53:26 PM UTC 24 | 13509475964 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1764704990 | Oct 02 06:52:30 PM UTC 24 | Oct 02 06:53:30 PM UTC 24 | 9047974153 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3500077796 | Oct 02 06:50:38 PM UTC 24 | Oct 02 06:53:40 PM UTC 24 | 33019172007 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1495333473 | Oct 02 06:46:48 PM UTC 24 | Oct 02 06:53:47 PM UTC 24 | 1858615168 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.153157574 | Oct 02 06:51:00 PM UTC 24 | Oct 02 06:53:57 PM UTC 24 | 16107932510 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.15597830 | Oct 02 06:52:48 PM UTC 24 | Oct 02 06:53:59 PM UTC 24 | 757041790 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1537765034 | Oct 02 06:48:28 PM UTC 24 | Oct 02 06:54:02 PM UTC 24 | 73996801013 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.379118594 | Oct 02 06:52:26 PM UTC 24 | Oct 02 06:54:03 PM UTC 24 | 288022883 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2323396451 | Oct 02 06:52:25 PM UTC 24 | Oct 02 06:54:07 PM UTC 24 | 281035810 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.726852936 | Oct 02 06:51:30 PM UTC 24 | Oct 02 06:54:14 PM UTC 24 | 1660648636 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3053814708 | Oct 02 06:52:48 PM UTC 24 | Oct 02 06:54:15 PM UTC 24 | 239869072 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.841972937 | Oct 02 06:49:17 PM UTC 24 | Oct 02 06:54:15 PM UTC 24 | 2712919938 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3368254551 | Oct 02 06:46:18 PM UTC 24 | Oct 02 06:54:24 PM UTC 24 | 156000124758 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4158222827 | Oct 02 06:51:00 PM UTC 24 | Oct 02 06:54:29 PM UTC 24 | 2777909143 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.261514309 | Oct 02 06:52:25 PM UTC 24 | Oct 02 06:54:29 PM UTC 24 | 7003792500 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3975649887 | Oct 02 06:49:55 PM UTC 24 | Oct 02 06:54:36 PM UTC 24 | 2287596861 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.869310187 | Oct 02 06:50:28 PM UTC 24 | Oct 02 06:54:37 PM UTC 24 | 1067148841 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.302218723 | Oct 02 06:52:03 PM UTC 24 | Oct 02 06:54:49 PM UTC 24 | 882871424 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4138417171 | Oct 02 06:47:59 PM UTC 24 | Oct 02 06:54:54 PM UTC 24 | 56323567025 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1029247371 | Oct 02 06:51:30 PM UTC 24 | Oct 02 06:54:59 PM UTC 24 | 2286914537 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4077737309 | Oct 02 06:51:02 PM UTC 24 | Oct 02 06:55:02 PM UTC 24 | 823169925 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2195216300 | Oct 02 06:46:21 PM UTC 24 | Oct 02 06:55:05 PM UTC 24 | 245387194509 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1755203158 | Oct 02 06:51:12 PM UTC 24 | Oct 02 06:55:07 PM UTC 24 | 36280357820 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4218187938 | Oct 02 06:48:36 PM UTC 24 | Oct 02 06:55:12 PM UTC 24 | 4004041539 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.813155434 | Oct 02 06:48:50 PM UTC 24 | Oct 02 06:55:24 PM UTC 24 | 193988986744 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2439766717 | Oct 02 06:52:14 PM UTC 24 | Oct 02 06:56:01 PM UTC 24 | 27919440431 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4011256947 | Oct 02 06:51:43 PM UTC 24 | Oct 02 06:56:12 PM UTC 24 | 34850199718 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1940700604 | Oct 02 06:52:11 PM UTC 24 | Oct 02 06:56:17 PM UTC 24 | 36881843042 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1509527390 | Oct 02 06:51:40 PM UTC 24 | Oct 02 06:56:29 PM UTC 24 | 80323258244 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4226259854 | Oct 02 06:47:53 PM UTC 24 | Oct 02 06:56:35 PM UTC 24 | 862854626 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4240327778 | Oct 02 06:47:50 PM UTC 24 | Oct 02 06:56:50 PM UTC 24 | 71947941580 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.525121373 | Oct 02 06:52:34 PM UTC 24 | Oct 02 06:56:58 PM UTC 24 | 103316904665 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3014486123 | Oct 02 06:45:54 PM UTC 24 | Oct 02 06:57:02 PM UTC 24 | 123024735016 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2835660313 | Oct 02 06:51:58 PM UTC 24 | Oct 02 06:57:13 PM UTC 24 | 2524113144 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.544051160 | Oct 02 06:51:57 PM UTC 24 | Oct 02 06:57:51 PM UTC 24 | 9514965702 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1979844390 | Oct 02 06:51:16 PM UTC 24 | Oct 02 06:57:56 PM UTC 24 | 60434895359 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3775996448 | Oct 02 06:47:04 PM UTC 24 | Oct 02 06:58:26 PM UTC 24 | 64859785626 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3541408667 | Oct 02 06:49:48 PM UTC 24 | Oct 02 06:58:31 PM UTC 24 | 3404337097 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1778473099 | Oct 02 06:48:59 PM UTC 24 | Oct 02 06:59:34 PM UTC 24 | 75918924677 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2171412764 | Oct 02 06:50:40 PM UTC 24 | Oct 02 07:00:17 PM UTC 24 | 140258065816 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1790328000 | Oct 02 06:51:43 PM UTC 24 | Oct 02 07:00:27 PM UTC 24 | 71728959700 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1337390263 | Oct 02 06:49:34 PM UTC 24 | Oct 02 07:00:46 PM UTC 24 | 54863597314 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3223886709 | Oct 02 06:48:30 PM UTC 24 | Oct 02 07:00:48 PM UTC 24 | 79764107692 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.550601819 | Oct 02 06:50:18 PM UTC 24 | Oct 02 07:01:47 PM UTC 24 | 59679327754 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1023935752 | Oct 02 06:52:16 PM UTC 24 | Oct 02 07:02:15 PM UTC 24 | 75800226882 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2579718194 | Oct 02 06:52:40 PM UTC 24 | Oct 02 07:04:54 PM UTC 24 | 71910476722 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3237044454 | Oct 02 06:47:23 PM UTC 24 | Oct 02 07:05:13 PM UTC 24 | 135020038341 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.385321153 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 461502083 ps |
| CPU time | 3.34 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:32:57 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385321153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.385321153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2927278238 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 13982804269 ps |
| CPU time | 222.21 seconds |
| Started | Oct 02 06:33:38 PM UTC 24 |
| Finished | Oct 02 06:37:24 PM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927278238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2927278238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3823694592 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 84998151418 ps |
| CPU time | 440.61 seconds |
| Started | Oct 02 06:33:43 PM UTC 24 |
| Finished | Oct 02 06:41:09 PM UTC 24 |
| Peak memory | 218328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823694592 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3823694592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3000777458 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 704874901 ps |
| CPU time | 39.6 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:33 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000777458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3000777458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3373377649 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 77876552191 ps |
| CPU time | 441.7 seconds |
| Started | Oct 02 06:33:58 PM UTC 24 |
| Finished | Oct 02 06:41:26 PM UTC 24 |
| Peak memory | 218324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373377649 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3373377649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3124611991 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 43649309690 ps |
| CPU time | 404.17 seconds |
| Started | Oct 02 06:33:32 PM UTC 24 |
| Finished | Oct 02 06:40:22 PM UTC 24 |
| Peak memory | 219752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124611991 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.3124611991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3031646320 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 444711037 ps |
| CPU time | 17.08 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:12 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031646320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3031646320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1791786089 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 79769636146 ps |
| CPU time | 290.08 seconds |
| Started | Oct 02 06:34:21 PM UTC 24 |
| Finished | Oct 02 06:39:16 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791786089 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1791786089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3291606649 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4124584436 ps |
| CPU time | 34.91 seconds |
| Started | Oct 02 06:33:16 PM UTC 24 |
| Finished | Oct 02 06:33:52 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291606649 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3291606649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2767406473 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 29386932 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:32:57 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767406473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2767406473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.786135189 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 227904900 ps |
| CPU time | 83.27 seconds |
| Started | Oct 02 06:32:58 PM UTC 24 |
| Finished | Oct 02 06:34:23 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786135189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.786135189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.958451892 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1824636094 ps |
| CPU time | 59.18 seconds |
| Started | Oct 02 06:33:30 PM UTC 24 |
| Finished | Oct 02 06:34:31 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958451892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.958451892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.990877686 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3737830314 ps |
| CPU time | 88.38 seconds |
| Started | Oct 02 06:35:33 PM UTC 24 |
| Finished | Oct 02 06:37:04 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990877686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.990877686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.2778560501 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 13186640809 ps |
| CPU time | 44.9 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:40 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778560501 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2778560501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.140978167 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 13263352025 ps |
| CPU time | 395.3 seconds |
| Started | Oct 02 06:33:36 PM UTC 24 |
| Finished | Oct 02 06:40:17 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140978167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.140978167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.3256132764 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1154519185 ps |
| CPU time | 49.36 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:45 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256132764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3256132764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.224890476 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 398185892 ps |
| CPU time | 14.79 seconds |
| Started | Oct 02 06:32:51 PM UTC 24 |
| Finished | Oct 02 06:33:07 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224890476 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.224890476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2436679555 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4625618310 ps |
| CPU time | 280.22 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:37:39 PM UTC 24 |
| Peak memory | 234168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436679555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2436679555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2214785372 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3312574579 ps |
| CPU time | 45.32 seconds |
| Started | Oct 02 06:32:50 PM UTC 24 |
| Finished | Oct 02 06:33:37 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214785372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2214785372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3072520710 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3327693764 ps |
| CPU time | 133.22 seconds |
| Started | Oct 02 06:32:56 PM UTC 24 |
| Finished | Oct 02 06:35:12 PM UTC 24 |
| Peak memory | 220136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072520710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3072520710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3377537174 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1212936866 ps |
| CPU time | 45.97 seconds |
| Started | Oct 02 06:43:56 PM UTC 24 |
| Finished | Oct 02 06:44:44 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377537174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3377537174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.211867312 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 42220077 ps |
| CPU time | 22.26 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211867312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.211867312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3474817073 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1231466045 ps |
| CPU time | 260.89 seconds |
| Started | Oct 02 06:37:52 PM UTC 24 |
| Finished | Oct 02 06:42:16 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474817073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3474817073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3893178300 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 21028282736 ps |
| CPU time | 160.23 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:35:37 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893178300 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3893178300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1642257854 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 875559953 ps |
| CPU time | 250.45 seconds |
| Started | Oct 02 06:40:10 PM UTC 24 |
| Finished | Oct 02 06:44:25 PM UTC 24 |
| Peak memory | 222280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642257854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1642257854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.31139359 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 733641284 ps |
| CPU time | 350.78 seconds |
| Started | Oct 02 06:46:31 PM UTC 24 |
| Finished | Oct 02 06:52:26 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31139359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.31139359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1071759220 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 564808198 ps |
| CPU time | 243.95 seconds |
| Started | Oct 02 06:40:46 PM UTC 24 |
| Finished | Oct 02 06:44:54 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071759220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.1071759220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3975649887 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2287596861 ps |
| CPU time | 276.6 seconds |
| Started | Oct 02 06:49:55 PM UTC 24 |
| Finished | Oct 02 06:54:36 PM UTC 24 |
| Peak memory | 232656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975649887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3975649887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3586007129 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 146270713 ps |
| CPU time | 26.12 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:19 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586007129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3586007129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.1715571847 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 323745457 ps |
| CPU time | 36.36 seconds |
| Started | Oct 02 06:37:44 PM UTC 24 |
| Finished | Oct 02 06:38:22 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715571847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1715571847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3643688568 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 83459977347 ps |
| CPU time | 589.11 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:42:49 PM UTC 24 |
| Peak memory | 221604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643688568 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3643688568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1502277512 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 281505615 ps |
| CPU time | 15.48 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:09 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502277512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1502277512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1387250124 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 80306529397 ps |
| CPU time | 159.06 seconds |
| Started | Oct 02 06:32:51 PM UTC 24 |
| Finished | Oct 02 06:35:33 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387250124 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1387250124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.86764071 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 21423274755 ps |
| CPU time | 112.08 seconds |
| Started | Oct 02 06:32:51 PM UTC 24 |
| Finished | Oct 02 06:34:45 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86764071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.86764071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2216637179 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 387632695 ps |
| CPU time | 23.26 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216637179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2216637179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.4179900396 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 38559592 ps |
| CPU time | 2.99 seconds |
| Started | Oct 02 06:32:50 PM UTC 24 |
| Finished | Oct 02 06:32:54 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179900396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4179900396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.861774633 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13786886723 ps |
| CPU time | 29.96 seconds |
| Started | Oct 02 06:32:50 PM UTC 24 |
| Finished | Oct 02 06:33:22 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861774633 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.861774633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2366913108 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7025564402 ps |
| CPU time | 44.95 seconds |
| Started | Oct 02 06:32:50 PM UTC 24 |
| Finished | Oct 02 06:33:37 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366913108 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2366913108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.538788613 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 39469844 ps |
| CPU time | 1.99 seconds |
| Started | Oct 02 06:32:50 PM UTC 24 |
| Finished | Oct 02 06:32:53 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538788613 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.538788613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.2543618858 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 6136251896 ps |
| CPU time | 140.02 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:35:15 PM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543618858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2543618858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1834758121 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 181906051 ps |
| CPU time | 14.23 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:08 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834758121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1834758121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.524527571 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 955315933 ps |
| CPU time | 22.89 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524527571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.524527571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2492937168 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3911092333 ps |
| CPU time | 42.62 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:38 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492937168 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2492937168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.876964378 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14264020 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:32:57 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876964378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.876964378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1433551077 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 218098610 ps |
| CPU time | 17.8 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:13 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433551077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1433551077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.803161349 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 70121747 ps |
| CPU time | 10.37 seconds |
| Started | Oct 02 06:32:53 PM UTC 24 |
| Finished | Oct 02 06:33:05 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803161349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.803161349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1537012739 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 488975384 ps |
| CPU time | 28.78 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:24 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537012739 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1537012739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.625064188 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2471240741 ps |
| CPU time | 24.71 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:20 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625064188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.625064188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.208191763 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9074046240 ps |
| CPU time | 31.74 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:25 PM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208191763 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.208191763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1096409956 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 7900224505 ps |
| CPU time | 33.24 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:33:27 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096409956 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1096409956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3529220806 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 32433849 ps |
| CPU time | 2.01 seconds |
| Started | Oct 02 06:32:52 PM UTC 24 |
| Finished | Oct 02 06:32:55 PM UTC 24 |
| Peak memory | 214768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529220806 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3529220806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.3934479756 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3795228604 ps |
| CPU time | 139.8 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:35:17 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934479756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3934479756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.3736807473 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2608924929 ps |
| CPU time | 50.02 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:33:46 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736807473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3736807473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1833530749 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 520119673 ps |
| CPU time | 232.84 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:36:51 PM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833530749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1833530749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1633733853 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2026459152 ps |
| CPU time | 92.94 seconds |
| Started | Oct 02 06:35:00 PM UTC 24 |
| Finished | Oct 02 06:36:35 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633733853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1633733853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.694048615 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 53653994331 ps |
| CPU time | 309.39 seconds |
| Started | Oct 02 06:35:01 PM UTC 24 |
| Finished | Oct 02 06:40:15 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694048615 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.694048615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.80401457 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 159091782 ps |
| CPU time | 10.15 seconds |
| Started | Oct 02 06:35:08 PM UTC 24 |
| Finished | Oct 02 06:35:20 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80401457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.80401457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.154884824 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2988208811 ps |
| CPU time | 31.58 seconds |
| Started | Oct 02 06:35:04 PM UTC 24 |
| Finished | Oct 02 06:35:37 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154884824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.154884824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.107075641 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2207888079 ps |
| CPU time | 36.8 seconds |
| Started | Oct 02 06:34:57 PM UTC 24 |
| Finished | Oct 02 06:35:36 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107075641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.107075641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.4095234085 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 60439972272 ps |
| CPU time | 197.33 seconds |
| Started | Oct 02 06:34:59 PM UTC 24 |
| Finished | Oct 02 06:38:19 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095234085 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.4095234085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2593047075 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 51902418974 ps |
| CPU time | 150.11 seconds |
| Started | Oct 02 06:34:59 PM UTC 24 |
| Finished | Oct 02 06:37:32 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593047075 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2593047075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3964111405 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 314650124 ps |
| CPU time | 18.55 seconds |
| Started | Oct 02 06:34:58 PM UTC 24 |
| Finished | Oct 02 06:35:17 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964111405 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3964111405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.707023408 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 322932225 ps |
| CPU time | 18.12 seconds |
| Started | Oct 02 06:35:01 PM UTC 24 |
| Finished | Oct 02 06:35:20 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707023408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.707023408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1545148146 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 327911464 ps |
| CPU time | 5.67 seconds |
| Started | Oct 02 06:34:53 PM UTC 24 |
| Finished | Oct 02 06:35:00 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545148146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1545148146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1837762657 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16981650250 ps |
| CPU time | 32.96 seconds |
| Started | Oct 02 06:34:55 PM UTC 24 |
| Finished | Oct 02 06:35:30 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837762657 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1837762657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3084375810 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 17757332950 ps |
| CPU time | 44.35 seconds |
| Started | Oct 02 06:34:55 PM UTC 24 |
| Finished | Oct 02 06:35:41 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084375810 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3084375810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2355729887 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 37463816 ps |
| CPU time | 3.04 seconds |
| Started | Oct 02 06:34:55 PM UTC 24 |
| Finished | Oct 02 06:34:59 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355729887 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2355729887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3925257595 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 558054408 ps |
| CPU time | 54.66 seconds |
| Started | Oct 02 06:35:12 PM UTC 24 |
| Finished | Oct 02 06:36:09 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925257595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3925257595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4195068110 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2783933065 ps |
| CPU time | 107.7 seconds |
| Started | Oct 02 06:35:16 PM UTC 24 |
| Finished | Oct 02 06:37:06 PM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195068110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4195068110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3679145292 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 344377830 ps |
| CPU time | 238.05 seconds |
| Started | Oct 02 06:35:13 PM UTC 24 |
| Finished | Oct 02 06:39:15 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679145292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3679145292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3616774550 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 532008943 ps |
| CPU time | 176.11 seconds |
| Started | Oct 02 06:35:16 PM UTC 24 |
| Finished | Oct 02 06:38:15 PM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616774550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3616774550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.1604841182 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4433582627 ps |
| CPU time | 41.1 seconds |
| Started | Oct 02 06:35:07 PM UTC 24 |
| Finished | Oct 02 06:35:50 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604841182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1604841182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1287661072 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 24145904802 ps |
| CPU time | 260.07 seconds |
| Started | Oct 02 06:35:33 PM UTC 24 |
| Finished | Oct 02 06:39:57 PM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287661072 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1287661072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2457609223 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 199560252 ps |
| CPU time | 7.57 seconds |
| Started | Oct 02 06:35:38 PM UTC 24 |
| Finished | Oct 02 06:35:46 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457609223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2457609223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3660904957 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 637086020 ps |
| CPU time | 10.47 seconds |
| Started | Oct 02 06:35:34 PM UTC 24 |
| Finished | Oct 02 06:35:46 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660904957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3660904957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.2294730835 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 43570904 ps |
| CPU time | 7.95 seconds |
| Started | Oct 02 06:35:22 PM UTC 24 |
| Finished | Oct 02 06:35:32 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294730835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2294730835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.668768839 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 52545881803 ps |
| CPU time | 273.81 seconds |
| Started | Oct 02 06:35:25 PM UTC 24 |
| Finished | Oct 02 06:40:03 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668768839 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.668768839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.622361226 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 9354448070 ps |
| CPU time | 79.48 seconds |
| Started | Oct 02 06:35:31 PM UTC 24 |
| Finished | Oct 02 06:36:52 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622361226 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.622361226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2141740715 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 230771012 ps |
| CPU time | 29.59 seconds |
| Started | Oct 02 06:35:24 PM UTC 24 |
| Finished | Oct 02 06:35:55 PM UTC 24 |
| Peak memory | 218012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141740715 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2141740715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3933515140 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2592316407 ps |
| CPU time | 14.45 seconds |
| Started | Oct 02 06:35:33 PM UTC 24 |
| Finished | Oct 02 06:35:49 PM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933515140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3933515140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.180586951 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 38792677 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 06:35:17 PM UTC 24 |
| Finished | Oct 02 06:35:22 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180586951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.180586951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2424836534 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8668699639 ps |
| CPU time | 35.98 seconds |
| Started | Oct 02 06:35:20 PM UTC 24 |
| Finished | Oct 02 06:35:57 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424836534 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2424836534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1861344306 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4191524661 ps |
| CPU time | 32.72 seconds |
| Started | Oct 02 06:35:21 PM UTC 24 |
| Finished | Oct 02 06:35:55 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861344306 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1861344306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.19878572 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 28139403 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 06:35:18 PM UTC 24 |
| Finished | Oct 02 06:35:23 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19878572 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.19878572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.2610358503 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1636971207 ps |
| CPU time | 74.05 seconds |
| Started | Oct 02 06:35:38 PM UTC 24 |
| Finished | Oct 02 06:36:54 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610358503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2610358503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2475645142 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4927125962 ps |
| CPU time | 35.95 seconds |
| Started | Oct 02 06:35:42 PM UTC 24 |
| Finished | Oct 02 06:36:19 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475645142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2475645142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3067653278 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 328463065 ps |
| CPU time | 101.72 seconds |
| Started | Oct 02 06:35:42 PM UTC 24 |
| Finished | Oct 02 06:37:26 PM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067653278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3067653278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2913607129 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 383911991 ps |
| CPU time | 97.05 seconds |
| Started | Oct 02 06:35:44 PM UTC 24 |
| Finished | Oct 02 06:37:23 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913607129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2913607129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.725259871 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 121863633 ps |
| CPU time | 19.92 seconds |
| Started | Oct 02 06:35:36 PM UTC 24 |
| Finished | Oct 02 06:35:58 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725259871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.725259871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.659420599 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 82681543 ps |
| CPU time | 23.45 seconds |
| Started | Oct 02 06:35:52 PM UTC 24 |
| Finished | Oct 02 06:36:17 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659420599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.659420599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1611056414 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 77150829836 ps |
| CPU time | 549 seconds |
| Started | Oct 02 06:35:56 PM UTC 24 |
| Finished | Oct 02 06:45:11 PM UTC 24 |
| Peak memory | 219564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611056414 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1611056414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.333375495 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 15917140 ps |
| CPU time | 2.77 seconds |
| Started | Oct 02 06:35:59 PM UTC 24 |
| Finished | Oct 02 06:36:03 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333375495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.333375495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.3960457835 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1072447076 ps |
| CPU time | 18.91 seconds |
| Started | Oct 02 06:35:57 PM UTC 24 |
| Finished | Oct 02 06:36:17 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960457835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3960457835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.262921997 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 175771571 ps |
| CPU time | 7.05 seconds |
| Started | Oct 02 06:35:50 PM UTC 24 |
| Finished | Oct 02 06:35:58 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262921997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.262921997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3826336276 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 80391549417 ps |
| CPU time | 130.96 seconds |
| Started | Oct 02 06:35:51 PM UTC 24 |
| Finished | Oct 02 06:38:04 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826336276 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3826336276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1096641337 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 54131132592 ps |
| CPU time | 264.78 seconds |
| Started | Oct 02 06:35:52 PM UTC 24 |
| Finished | Oct 02 06:40:21 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096641337 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1096641337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2019747977 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 38354981 ps |
| CPU time | 6.38 seconds |
| Started | Oct 02 06:35:51 PM UTC 24 |
| Finished | Oct 02 06:35:59 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019747977 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2019747977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3520957514 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 185707452 ps |
| CPU time | 16.9 seconds |
| Started | Oct 02 06:35:57 PM UTC 24 |
| Finished | Oct 02 06:36:15 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520957514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3520957514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1670840229 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 35119319 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 06:35:46 PM UTC 24 |
| Finished | Oct 02 06:35:52 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670840229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1670840229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3616754415 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 7589710822 ps |
| CPU time | 37.64 seconds |
| Started | Oct 02 06:35:48 PM UTC 24 |
| Finished | Oct 02 06:36:27 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616754415 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3616754415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3410090565 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3753164400 ps |
| CPU time | 41.02 seconds |
| Started | Oct 02 06:35:49 PM UTC 24 |
| Finished | Oct 02 06:36:31 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410090565 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3410090565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.586225257 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 27837007 ps |
| CPU time | 3.98 seconds |
| Started | Oct 02 06:35:46 PM UTC 24 |
| Finished | Oct 02 06:35:51 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586225257 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.586225257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2116114591 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4434306290 ps |
| CPU time | 87.47 seconds |
| Started | Oct 02 06:35:59 PM UTC 24 |
| Finished | Oct 02 06:37:28 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116114591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2116114591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3758848042 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10108166168 ps |
| CPU time | 247.32 seconds |
| Started | Oct 02 06:36:01 PM UTC 24 |
| Finished | Oct 02 06:40:12 PM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758848042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3758848042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2843856918 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 327359885 ps |
| CPU time | 151.43 seconds |
| Started | Oct 02 06:35:59 PM UTC 24 |
| Finished | Oct 02 06:38:33 PM UTC 24 |
| Peak memory | 219888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843856918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2843856918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3025700239 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4131962291 ps |
| CPU time | 258.44 seconds |
| Started | Oct 02 06:36:02 PM UTC 24 |
| Finished | Oct 02 06:40:25 PM UTC 24 |
| Peak memory | 232584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025700239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3025700239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3435924961 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 129071927 ps |
| CPU time | 14.94 seconds |
| Started | Oct 02 06:35:58 PM UTC 24 |
| Finished | Oct 02 06:36:14 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435924961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3435924961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.252953191 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5061199171 ps |
| CPU time | 67.43 seconds |
| Started | Oct 02 06:36:16 PM UTC 24 |
| Finished | Oct 02 06:37:25 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252953191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.252953191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3820874607 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 17488962721 ps |
| CPU time | 100.19 seconds |
| Started | Oct 02 06:36:18 PM UTC 24 |
| Finished | Oct 02 06:38:00 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820874607 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.3820874607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4124926723 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 79513773 ps |
| CPU time | 13.67 seconds |
| Started | Oct 02 06:36:26 PM UTC 24 |
| Finished | Oct 02 06:36:41 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124926723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4124926723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2449663057 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1681067861 ps |
| CPU time | 15.3 seconds |
| Started | Oct 02 06:36:20 PM UTC 24 |
| Finished | Oct 02 06:36:37 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449663057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2449663057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.2372981093 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 316741074 ps |
| CPU time | 19.95 seconds |
| Started | Oct 02 06:36:09 PM UTC 24 |
| Finished | Oct 02 06:36:30 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372981093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2372981093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.607169172 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 118508739903 ps |
| CPU time | 367.89 seconds |
| Started | Oct 02 06:36:13 PM UTC 24 |
| Finished | Oct 02 06:42:27 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607169172 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.607169172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1190190208 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 62072845290 ps |
| CPU time | 198.37 seconds |
| Started | Oct 02 06:36:15 PM UTC 24 |
| Finished | Oct 02 06:39:36 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190190208 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1190190208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1333813279 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 142430355 ps |
| CPU time | 17.46 seconds |
| Started | Oct 02 06:36:10 PM UTC 24 |
| Finished | Oct 02 06:36:29 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333813279 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1333813279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.3169684451 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 915197524 ps |
| CPU time | 20.28 seconds |
| Started | Oct 02 06:36:18 PM UTC 24 |
| Finished | Oct 02 06:36:39 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169684451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3169684451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2750245863 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 76843040 ps |
| CPU time | 2.87 seconds |
| Started | Oct 02 06:36:04 PM UTC 24 |
| Finished | Oct 02 06:36:07 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750245863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2750245863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2075871088 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 36974375633 ps |
| CPU time | 69.04 seconds |
| Started | Oct 02 06:36:08 PM UTC 24 |
| Finished | Oct 02 06:37:19 PM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075871088 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2075871088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2393580872 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3056457923 ps |
| CPU time | 26.56 seconds |
| Started | Oct 02 06:36:09 PM UTC 24 |
| Finished | Oct 02 06:36:37 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393580872 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2393580872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3799096083 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 43931912 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 06:36:08 PM UTC 24 |
| Finished | Oct 02 06:36:12 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799096083 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3799096083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.847726883 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 228663676 ps |
| CPU time | 36.79 seconds |
| Started | Oct 02 06:36:27 PM UTC 24 |
| Finished | Oct 02 06:37:06 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847726883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.847726883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.159195510 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 7813028087 ps |
| CPU time | 208.96 seconds |
| Started | Oct 02 06:36:31 PM UTC 24 |
| Finished | Oct 02 06:40:03 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159195510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.159195510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.647594213 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 311272171 ps |
| CPU time | 118.18 seconds |
| Started | Oct 02 06:36:30 PM UTC 24 |
| Finished | Oct 02 06:38:31 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647594213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.647594213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3212130254 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4149138687 ps |
| CPU time | 86 seconds |
| Started | Oct 02 06:36:32 PM UTC 24 |
| Finished | Oct 02 06:38:00 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212130254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3212130254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.4244306508 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 622565878 ps |
| CPU time | 29.23 seconds |
| Started | Oct 02 06:36:25 PM UTC 24 |
| Finished | Oct 02 06:36:56 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244306508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4244306508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.3057354241 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1678431890 ps |
| CPU time | 49.83 seconds |
| Started | Oct 02 06:36:52 PM UTC 24 |
| Finished | Oct 02 06:37:44 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057354241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3057354241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3426577654 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4402971942 ps |
| CPU time | 40.46 seconds |
| Started | Oct 02 06:36:52 PM UTC 24 |
| Finished | Oct 02 06:37:35 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426577654 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3426577654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2626841344 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 357192657 ps |
| CPU time | 11.05 seconds |
| Started | Oct 02 06:36:59 PM UTC 24 |
| Finished | Oct 02 06:37:11 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626841344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2626841344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3585469507 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 155392802 ps |
| CPU time | 3.14 seconds |
| Started | Oct 02 06:36:55 PM UTC 24 |
| Finished | Oct 02 06:36:59 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585469507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3585469507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2919328928 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1237256816 ps |
| CPU time | 43.2 seconds |
| Started | Oct 02 06:36:39 PM UTC 24 |
| Finished | Oct 02 06:37:24 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919328928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2919328928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.1898408602 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 45963737094 ps |
| CPU time | 208.03 seconds |
| Started | Oct 02 06:36:42 PM UTC 24 |
| Finished | Oct 02 06:40:13 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898408602 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1898408602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3271838963 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 50062686003 ps |
| CPU time | 272.94 seconds |
| Started | Oct 02 06:36:42 PM UTC 24 |
| Finished | Oct 02 06:41:19 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271838963 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3271838963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.951393744 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 362591698 ps |
| CPU time | 19.81 seconds |
| Started | Oct 02 06:36:41 PM UTC 24 |
| Finished | Oct 02 06:37:02 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951393744 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.951393744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.3339283465 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 962789811 ps |
| CPU time | 26.08 seconds |
| Started | Oct 02 06:36:54 PM UTC 24 |
| Finished | Oct 02 06:37:21 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339283465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3339283465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.3982533723 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 184621284 ps |
| CPU time | 5.12 seconds |
| Started | Oct 02 06:36:32 PM UTC 24 |
| Finished | Oct 02 06:36:38 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982533723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3982533723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1425113333 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5190621919 ps |
| CPU time | 49.82 seconds |
| Started | Oct 02 06:36:37 PM UTC 24 |
| Finished | Oct 02 06:37:29 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425113333 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1425113333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.85376906 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2958126707 ps |
| CPU time | 51 seconds |
| Started | Oct 02 06:36:38 PM UTC 24 |
| Finished | Oct 02 06:37:31 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85376906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.85376906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1735982839 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 45311765 ps |
| CPU time | 4 seconds |
| Started | Oct 02 06:36:36 PM UTC 24 |
| Finished | Oct 02 06:36:41 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735982839 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1735982839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3710721627 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1176224871 ps |
| CPU time | 59.38 seconds |
| Started | Oct 02 06:37:00 PM UTC 24 |
| Finished | Oct 02 06:38:01 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710721627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3710721627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3662773426 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 234251994 ps |
| CPU time | 25.25 seconds |
| Started | Oct 02 06:37:03 PM UTC 24 |
| Finished | Oct 02 06:37:30 PM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662773426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3662773426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2241318541 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 342965754 ps |
| CPU time | 181.46 seconds |
| Started | Oct 02 06:37:02 PM UTC 24 |
| Finished | Oct 02 06:40:07 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241318541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2241318541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1626415803 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1612304600 ps |
| CPU time | 94.28 seconds |
| Started | Oct 02 06:37:04 PM UTC 24 |
| Finished | Oct 02 06:38:41 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626415803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1626415803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1424118654 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3724093109 ps |
| CPU time | 36.16 seconds |
| Started | Oct 02 06:36:57 PM UTC 24 |
| Finished | Oct 02 06:37:34 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424118654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1424118654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.488370000 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2868257394 ps |
| CPU time | 56.79 seconds |
| Started | Oct 02 06:37:25 PM UTC 24 |
| Finished | Oct 02 06:38:23 PM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488370000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.488370000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.268579996 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 64811203408 ps |
| CPU time | 651.22 seconds |
| Started | Oct 02 06:37:25 PM UTC 24 |
| Finished | Oct 02 06:48:24 PM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268579996 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.268579996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1846231944 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 118086144 ps |
| CPU time | 21.98 seconds |
| Started | Oct 02 06:37:27 PM UTC 24 |
| Finished | Oct 02 06:37:51 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846231944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1846231944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3398651588 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 471944335 ps |
| CPU time | 22.24 seconds |
| Started | Oct 02 06:37:26 PM UTC 24 |
| Finished | Oct 02 06:37:49 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398651588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3398651588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.368768630 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 242170119 ps |
| CPU time | 29.25 seconds |
| Started | Oct 02 06:37:12 PM UTC 24 |
| Finished | Oct 02 06:37:43 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368768630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.368768630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.2516622232 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 40531964416 ps |
| CPU time | 278.52 seconds |
| Started | Oct 02 06:37:19 PM UTC 24 |
| Finished | Oct 02 06:42:02 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516622232 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2516622232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1639304944 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5490483364 ps |
| CPU time | 21.81 seconds |
| Started | Oct 02 06:37:22 PM UTC 24 |
| Finished | Oct 02 06:37:46 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639304944 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1639304944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3737794289 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 61978766 ps |
| CPU time | 11.37 seconds |
| Started | Oct 02 06:37:14 PM UTC 24 |
| Finished | Oct 02 06:37:27 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737794289 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3737794289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2092399355 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1282321394 ps |
| CPU time | 18.36 seconds |
| Started | Oct 02 06:37:26 PM UTC 24 |
| Finished | Oct 02 06:37:46 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092399355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2092399355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2052761650 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 192573784 ps |
| CPU time | 5.16 seconds |
| Started | Oct 02 06:37:07 PM UTC 24 |
| Finished | Oct 02 06:37:13 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052761650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2052761650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.361015774 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 6650696203 ps |
| CPU time | 61.25 seconds |
| Started | Oct 02 06:37:08 PM UTC 24 |
| Finished | Oct 02 06:38:11 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361015774 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.361015774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1003584087 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1945562430 ps |
| CPU time | 30.32 seconds |
| Started | Oct 02 06:37:12 PM UTC 24 |
| Finished | Oct 02 06:37:44 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003584087 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1003584087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1206599928 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 90021167 ps |
| CPU time | 3.58 seconds |
| Started | Oct 02 06:37:07 PM UTC 24 |
| Finished | Oct 02 06:37:11 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206599928 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1206599928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.869204724 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1107227431 ps |
| CPU time | 162.15 seconds |
| Started | Oct 02 06:37:29 PM UTC 24 |
| Finished | Oct 02 06:40:15 PM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869204724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.869204724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.433169051 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 9867682602 ps |
| CPU time | 217.95 seconds |
| Started | Oct 02 06:37:31 PM UTC 24 |
| Finished | Oct 02 06:41:12 PM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433169051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.433169051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2490070804 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 51980181 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 06:37:31 PM UTC 24 |
| Finished | Oct 02 06:37:35 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490070804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2490070804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2966176946 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 110409946 ps |
| CPU time | 16.95 seconds |
| Started | Oct 02 06:37:32 PM UTC 24 |
| Finished | Oct 02 06:37:50 PM UTC 24 |
| Peak memory | 217768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966176946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2966176946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3030854007 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 27576858 ps |
| CPU time | 8.13 seconds |
| Started | Oct 02 06:37:27 PM UTC 24 |
| Finished | Oct 02 06:37:37 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030854007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3030854007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3899385159 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 53877597211 ps |
| CPU time | 376.87 seconds |
| Started | Oct 02 06:37:45 PM UTC 24 |
| Finished | Oct 02 06:44:07 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899385159 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3899385159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.925442572 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 346115746 ps |
| CPU time | 21.02 seconds |
| Started | Oct 02 06:37:50 PM UTC 24 |
| Finished | Oct 02 06:38:13 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925442572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.925442572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3508605737 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 106133816 ps |
| CPU time | 19.37 seconds |
| Started | Oct 02 06:37:46 PM UTC 24 |
| Finished | Oct 02 06:38:07 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508605737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3508605737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.733990576 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 355791172 ps |
| CPU time | 28.59 seconds |
| Started | Oct 02 06:37:37 PM UTC 24 |
| Finished | Oct 02 06:38:07 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733990576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.733990576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1130189132 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 211861876746 ps |
| CPU time | 479.06 seconds |
| Started | Oct 02 06:37:41 PM UTC 24 |
| Finished | Oct 02 06:45:46 PM UTC 24 |
| Peak memory | 217444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130189132 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1130189132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2522864509 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 38826605037 ps |
| CPU time | 307.41 seconds |
| Started | Oct 02 06:37:41 PM UTC 24 |
| Finished | Oct 02 06:42:53 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522864509 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2522864509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.2592817073 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 711745749 ps |
| CPU time | 27.72 seconds |
| Started | Oct 02 06:37:40 PM UTC 24 |
| Finished | Oct 02 06:38:09 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592817073 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2592817073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.2881646280 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1783823016 ps |
| CPU time | 50.84 seconds |
| Started | Oct 02 06:37:45 PM UTC 24 |
| Finished | Oct 02 06:38:37 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881646280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2881646280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.111367530 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 198623621 ps |
| CPU time | 5.18 seconds |
| Started | Oct 02 06:37:33 PM UTC 24 |
| Finished | Oct 02 06:37:39 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111367530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.111367530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.174979047 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5300040917 ps |
| CPU time | 40.57 seconds |
| Started | Oct 02 06:37:36 PM UTC 24 |
| Finished | Oct 02 06:38:18 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174979047 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.174979047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1491311236 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4025865835 ps |
| CPU time | 45.66 seconds |
| Started | Oct 02 06:37:36 PM UTC 24 |
| Finished | Oct 02 06:38:23 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491311236 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1491311236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4014162577 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 27549111 ps |
| CPU time | 3.82 seconds |
| Started | Oct 02 06:37:35 PM UTC 24 |
| Finished | Oct 02 06:37:40 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014162577 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4014162577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3659720853 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 14630243109 ps |
| CPU time | 218.35 seconds |
| Started | Oct 02 06:37:50 PM UTC 24 |
| Finished | Oct 02 06:41:33 PM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659720853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3659720853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1416004463 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5029460866 ps |
| CPU time | 106.3 seconds |
| Started | Oct 02 06:38:01 PM UTC 24 |
| Finished | Oct 02 06:39:50 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416004463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1416004463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3956622386 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 260384460 ps |
| CPU time | 138.85 seconds |
| Started | Oct 02 06:38:01 PM UTC 24 |
| Finished | Oct 02 06:40:23 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956622386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3956622386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.783713358 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1151430908 ps |
| CPU time | 19.63 seconds |
| Started | Oct 02 06:37:46 PM UTC 24 |
| Finished | Oct 02 06:38:07 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783713358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.783713358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2724459086 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 358346642 ps |
| CPU time | 40.18 seconds |
| Started | Oct 02 06:38:08 PM UTC 24 |
| Finished | Oct 02 06:38:50 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724459086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2724459086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4239299861 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 52855566083 ps |
| CPU time | 213.93 seconds |
| Started | Oct 02 06:38:08 PM UTC 24 |
| Finished | Oct 02 06:41:46 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239299861 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.4239299861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4241681085 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 109724666 ps |
| CPU time | 20.9 seconds |
| Started | Oct 02 06:38:14 PM UTC 24 |
| Finished | Oct 02 06:38:36 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241681085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4241681085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.1325145521 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 139849356 ps |
| CPU time | 8.04 seconds |
| Started | Oct 02 06:38:11 PM UTC 24 |
| Finished | Oct 02 06:38:21 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325145521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1325145521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2723584765 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1354308320 ps |
| CPU time | 33.77 seconds |
| Started | Oct 02 06:38:06 PM UTC 24 |
| Finished | Oct 02 06:38:41 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723584765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2723584765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.248973066 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 212881433381 ps |
| CPU time | 393.39 seconds |
| Started | Oct 02 06:38:07 PM UTC 24 |
| Finished | Oct 02 06:44:46 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248973066 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.248973066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3072558630 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 25318192236 ps |
| CPU time | 220.56 seconds |
| Started | Oct 02 06:38:08 PM UTC 24 |
| Finished | Oct 02 06:41:52 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072558630 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3072558630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1131728085 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 193164711 ps |
| CPU time | 24.62 seconds |
| Started | Oct 02 06:38:06 PM UTC 24 |
| Finished | Oct 02 06:38:32 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131728085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1131728085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4285860002 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 38966297 ps |
| CPU time | 4.97 seconds |
| Started | Oct 02 06:38:09 PM UTC 24 |
| Finished | Oct 02 06:38:15 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285860002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4285860002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3101888871 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 34964694 ps |
| CPU time | 2.77 seconds |
| Started | Oct 02 06:38:01 PM UTC 24 |
| Finished | Oct 02 06:38:05 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101888871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3101888871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2052525118 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6942269313 ps |
| CPU time | 53.72 seconds |
| Started | Oct 02 06:38:03 PM UTC 24 |
| Finished | Oct 02 06:38:58 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052525118 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2052525118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2640529197 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4684122232 ps |
| CPU time | 30.69 seconds |
| Started | Oct 02 06:38:05 PM UTC 24 |
| Finished | Oct 02 06:38:37 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640529197 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2640529197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3042958261 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 32006080 ps |
| CPU time | 3.17 seconds |
| Started | Oct 02 06:38:01 PM UTC 24 |
| Finished | Oct 02 06:38:06 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042958261 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3042958261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.4051349322 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5243919285 ps |
| CPU time | 244.94 seconds |
| Started | Oct 02 06:38:16 PM UTC 24 |
| Finished | Oct 02 06:42:25 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051349322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4051349322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3012259030 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1143457474 ps |
| CPU time | 49.59 seconds |
| Started | Oct 02 06:38:19 PM UTC 24 |
| Finished | Oct 02 06:39:10 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012259030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3012259030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1048813677 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 912562566 ps |
| CPU time | 33.43 seconds |
| Started | Oct 02 06:38:16 PM UTC 24 |
| Finished | Oct 02 06:38:51 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048813677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1048813677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2272849273 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 12464336860 ps |
| CPU time | 252.77 seconds |
| Started | Oct 02 06:38:20 PM UTC 24 |
| Finished | Oct 02 06:42:37 PM UTC 24 |
| Peak memory | 222412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272849273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.2272849273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2225367930 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 831828391 ps |
| CPU time | 28.54 seconds |
| Started | Oct 02 06:38:13 PM UTC 24 |
| Finished | Oct 02 06:38:43 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225367930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2225367930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2687402429 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2256496281 ps |
| CPU time | 66.81 seconds |
| Started | Oct 02 06:38:33 PM UTC 24 |
| Finished | Oct 02 06:39:42 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687402429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2687402429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3427757464 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 21922590021 ps |
| CPU time | 247.69 seconds |
| Started | Oct 02 06:38:34 PM UTC 24 |
| Finished | Oct 02 06:42:46 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427757464 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3427757464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.909997289 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 132104977 ps |
| CPU time | 4.14 seconds |
| Started | Oct 02 06:38:39 PM UTC 24 |
| Finished | Oct 02 06:38:44 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909997289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.909997289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.2420559236 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5064012397 ps |
| CPU time | 44.53 seconds |
| Started | Oct 02 06:38:39 PM UTC 24 |
| Finished | Oct 02 06:39:25 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420559236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2420559236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.1041114033 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 267734738 ps |
| CPU time | 25.88 seconds |
| Started | Oct 02 06:38:24 PM UTC 24 |
| Finished | Oct 02 06:38:52 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041114033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1041114033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.586019684 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7393166290 ps |
| CPU time | 86.27 seconds |
| Started | Oct 02 06:38:27 PM UTC 24 |
| Finished | Oct 02 06:39:56 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586019684 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.586019684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1349067995 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 32049579876 ps |
| CPU time | 220.09 seconds |
| Started | Oct 02 06:38:32 PM UTC 24 |
| Finished | Oct 02 06:42:15 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349067995 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1349067995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.4145201001 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 87499085 ps |
| CPU time | 10.86 seconds |
| Started | Oct 02 06:38:26 PM UTC 24 |
| Finished | Oct 02 06:38:39 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145201001 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.4145201001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.670305413 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 532770833 ps |
| CPU time | 12.89 seconds |
| Started | Oct 02 06:38:37 PM UTC 24 |
| Finished | Oct 02 06:38:51 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670305413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.670305413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2515974535 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 340374928 ps |
| CPU time | 4.76 seconds |
| Started | Oct 02 06:38:21 PM UTC 24 |
| Finished | Oct 02 06:38:27 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515974535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2515974535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.836352931 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5493962849 ps |
| CPU time | 62.27 seconds |
| Started | Oct 02 06:38:23 PM UTC 24 |
| Finished | Oct 02 06:39:27 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836352931 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.836352931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1661076093 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2953154302 ps |
| CPU time | 19.54 seconds |
| Started | Oct 02 06:38:24 PM UTC 24 |
| Finished | Oct 02 06:38:46 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661076093 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1661076093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1239070895 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 46057419 ps |
| CPU time | 2.95 seconds |
| Started | Oct 02 06:38:22 PM UTC 24 |
| Finished | Oct 02 06:38:26 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239070895 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1239070895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2719105509 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 10730815769 ps |
| CPU time | 207.91 seconds |
| Started | Oct 02 06:38:40 PM UTC 24 |
| Finished | Oct 02 06:42:11 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719105509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2719105509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3376304897 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1402961133 ps |
| CPU time | 117.79 seconds |
| Started | Oct 02 06:38:42 PM UTC 24 |
| Finished | Oct 02 06:40:42 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376304897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3376304897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.364887959 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 166275271 ps |
| CPU time | 104.06 seconds |
| Started | Oct 02 06:38:42 PM UTC 24 |
| Finished | Oct 02 06:40:28 PM UTC 24 |
| Peak memory | 219872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364887959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.364887959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3643336300 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 457949189 ps |
| CPU time | 70.75 seconds |
| Started | Oct 02 06:38:44 PM UTC 24 |
| Finished | Oct 02 06:39:57 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643336300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3643336300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2759752960 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 148199662 ps |
| CPU time | 18.95 seconds |
| Started | Oct 02 06:38:39 PM UTC 24 |
| Finished | Oct 02 06:38:59 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759752960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2759752960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2575331206 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1360760565 ps |
| CPU time | 62.14 seconds |
| Started | Oct 02 06:38:53 PM UTC 24 |
| Finished | Oct 02 06:39:57 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575331206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2575331206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.159089568 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 63074128273 ps |
| CPU time | 450.22 seconds |
| Started | Oct 02 06:38:55 PM UTC 24 |
| Finished | Oct 02 06:46:31 PM UTC 24 |
| Peak memory | 219492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159089568 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.159089568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3650621952 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 499853964 ps |
| CPU time | 9.08 seconds |
| Started | Oct 02 06:39:06 PM UTC 24 |
| Finished | Oct 02 06:39:16 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650621952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3650621952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.2212973294 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 262931498 ps |
| CPU time | 4.25 seconds |
| Started | Oct 02 06:38:59 PM UTC 24 |
| Finished | Oct 02 06:39:04 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212973294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2212973294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.2146631715 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 221794385 ps |
| CPU time | 32.71 seconds |
| Started | Oct 02 06:38:51 PM UTC 24 |
| Finished | Oct 02 06:39:25 PM UTC 24 |
| Peak memory | 216032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146631715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2146631715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.2940984069 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 22702651253 ps |
| CPU time | 85.25 seconds |
| Started | Oct 02 06:38:52 PM UTC 24 |
| Finished | Oct 02 06:40:19 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940984069 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2940984069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2514026286 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 34469768936 ps |
| CPU time | 233.06 seconds |
| Started | Oct 02 06:38:52 PM UTC 24 |
| Finished | Oct 02 06:42:49 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514026286 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2514026286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1506010125 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 166141196 ps |
| CPU time | 37.24 seconds |
| Started | Oct 02 06:38:51 PM UTC 24 |
| Finished | Oct 02 06:39:29 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506010125 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1506010125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.790840471 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 336961665 ps |
| CPU time | 9.05 seconds |
| Started | Oct 02 06:38:59 PM UTC 24 |
| Finished | Oct 02 06:39:09 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790840471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.790840471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3220283178 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 166205172 ps |
| CPU time | 3.73 seconds |
| Started | Oct 02 06:38:44 PM UTC 24 |
| Finished | Oct 02 06:38:49 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220283178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3220283178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.4217506660 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6937107225 ps |
| CPU time | 52.71 seconds |
| Started | Oct 02 06:38:46 PM UTC 24 |
| Finished | Oct 02 06:39:41 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217506660 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4217506660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2105776373 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 14343297866 ps |
| CPU time | 34.58 seconds |
| Started | Oct 02 06:38:50 PM UTC 24 |
| Finished | Oct 02 06:39:25 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105776373 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2105776373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1687554158 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 29115711 ps |
| CPU time | 4.02 seconds |
| Started | Oct 02 06:38:44 PM UTC 24 |
| Finished | Oct 02 06:38:49 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687554158 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1687554158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.1525667828 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1620941855 ps |
| CPU time | 42.87 seconds |
| Started | Oct 02 06:39:10 PM UTC 24 |
| Finished | Oct 02 06:39:54 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525667828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1525667828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2472292326 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 694472966 ps |
| CPU time | 46.86 seconds |
| Started | Oct 02 06:39:14 PM UTC 24 |
| Finished | Oct 02 06:40:03 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472292326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2472292326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3256399353 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 718014703 ps |
| CPU time | 232.28 seconds |
| Started | Oct 02 06:39:11 PM UTC 24 |
| Finished | Oct 02 06:43:07 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256399353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3256399353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1543248286 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 65106696 ps |
| CPU time | 36.13 seconds |
| Started | Oct 02 06:39:16 PM UTC 24 |
| Finished | Oct 02 06:39:53 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543248286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1543248286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3719236832 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 123954295 ps |
| CPU time | 23.67 seconds |
| Started | Oct 02 06:39:02 PM UTC 24 |
| Finished | Oct 02 06:39:27 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719236832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3719236832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.2679419058 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2060747824 ps |
| CPU time | 44.25 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:33:41 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679419058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2679419058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.760917760 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 29295738108 ps |
| CPU time | 177.84 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:35:56 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760917760 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.760917760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3939810322 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 20076823 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 06:32:56 PM UTC 24 |
| Finished | Oct 02 06:32:58 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939810322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3939810322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1944191633 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 314869296 ps |
| CPU time | 22.02 seconds |
| Started | Oct 02 06:32:56 PM UTC 24 |
| Finished | Oct 02 06:33:19 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944191633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1944191633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2405978493 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 590388652 ps |
| CPU time | 19.7 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405978493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2405978493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.311414202 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 11975380753 ps |
| CPU time | 71.82 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:34:09 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311414202 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.311414202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3428824117 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8251185730 ps |
| CPU time | 87.84 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:34:25 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428824117 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3428824117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.786397132 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 200824214 ps |
| CPU time | 33.36 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:33:30 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786397132 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.786397132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1231556072 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 183420341 ps |
| CPU time | 19.07 seconds |
| Started | Oct 02 06:32:56 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231556072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1231556072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2986826840 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 129935237 ps |
| CPU time | 2.65 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:32:58 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986826840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2986826840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.347393722 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 12678713431 ps |
| CPU time | 40.59 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:33:37 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347393722 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.347393722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2448199933 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6796678263 ps |
| CPU time | 34.4 seconds |
| Started | Oct 02 06:32:55 PM UTC 24 |
| Finished | Oct 02 06:33:31 PM UTC 24 |
| Peak memory | 215884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448199933 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2448199933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2793397700 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 72126475 ps |
| CPU time | 2.49 seconds |
| Started | Oct 02 06:32:54 PM UTC 24 |
| Finished | Oct 02 06:32:58 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793397700 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2793397700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3758018498 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1055670839 ps |
| CPU time | 67.43 seconds |
| Started | Oct 02 06:32:58 PM UTC 24 |
| Finished | Oct 02 06:34:07 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758018498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3758018498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2608267508 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 843119659 ps |
| CPU time | 230.85 seconds |
| Started | Oct 02 06:32:57 PM UTC 24 |
| Finished | Oct 02 06:36:52 PM UTC 24 |
| Peak memory | 219816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608267508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2608267508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.316892142 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 86074687 ps |
| CPU time | 5.48 seconds |
| Started | Oct 02 06:32:56 PM UTC 24 |
| Finished | Oct 02 06:33:02 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316892142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.316892142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3503292425 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 639127190 ps |
| CPU time | 27.3 seconds |
| Started | Oct 02 06:39:27 PM UTC 24 |
| Finished | Oct 02 06:39:56 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503292425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3503292425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.4035994826 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 177452576370 ps |
| CPU time | 425.82 seconds |
| Started | Oct 02 06:39:31 PM UTC 24 |
| Finished | Oct 02 06:46:43 PM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035994826 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.4035994826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2185467362 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 960999049 ps |
| CPU time | 26.1 seconds |
| Started | Oct 02 06:39:41 PM UTC 24 |
| Finished | Oct 02 06:40:09 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185467362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2185467362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1590773249 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 597586475 ps |
| CPU time | 34.74 seconds |
| Started | Oct 02 06:39:37 PM UTC 24 |
| Finished | Oct 02 06:40:14 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590773249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1590773249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1998680302 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1796627520 ps |
| CPU time | 39.94 seconds |
| Started | Oct 02 06:39:25 PM UTC 24 |
| Finished | Oct 02 06:40:07 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998680302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1998680302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.571172143 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 33764157148 ps |
| CPU time | 264.92 seconds |
| Started | Oct 02 06:39:26 PM UTC 24 |
| Finished | Oct 02 06:43:55 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571172143 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.571172143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2995679424 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 39180728600 ps |
| CPU time | 109.4 seconds |
| Started | Oct 02 06:39:27 PM UTC 24 |
| Finished | Oct 02 06:41:19 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995679424 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2995679424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1813380952 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 100830304 ps |
| CPU time | 13.39 seconds |
| Started | Oct 02 06:39:26 PM UTC 24 |
| Finished | Oct 02 06:39:41 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813380952 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1813380952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1554242657 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 521823739 ps |
| CPU time | 12.39 seconds |
| Started | Oct 02 06:39:37 PM UTC 24 |
| Finished | Oct 02 06:39:51 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554242657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1554242657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.1039698614 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 97137989 ps |
| CPU time | 4.55 seconds |
| Started | Oct 02 06:39:17 PM UTC 24 |
| Finished | Oct 02 06:39:22 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039698614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1039698614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1137727791 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 26036242572 ps |
| CPU time | 62.73 seconds |
| Started | Oct 02 06:39:22 PM UTC 24 |
| Finished | Oct 02 06:40:26 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137727791 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1137727791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1673025219 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5111244712 ps |
| CPU time | 36.97 seconds |
| Started | Oct 02 06:39:23 PM UTC 24 |
| Finished | Oct 02 06:40:01 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673025219 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1673025219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.933732990 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 41011234 ps |
| CPU time | 3.33 seconds |
| Started | Oct 02 06:39:17 PM UTC 24 |
| Finished | Oct 02 06:39:21 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933732990 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.933732990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.263713281 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2497642343 ps |
| CPU time | 101.58 seconds |
| Started | Oct 02 06:39:41 PM UTC 24 |
| Finished | Oct 02 06:41:25 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263713281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.263713281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.390553870 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2442309742 ps |
| CPU time | 132.6 seconds |
| Started | Oct 02 06:39:43 PM UTC 24 |
| Finished | Oct 02 06:41:58 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390553870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.390553870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1947031457 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 337940674 ps |
| CPU time | 218.12 seconds |
| Started | Oct 02 06:39:43 PM UTC 24 |
| Finished | Oct 02 06:43:24 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947031457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1947031457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1417113988 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 73003961 ps |
| CPU time | 47.47 seconds |
| Started | Oct 02 06:39:51 PM UTC 24 |
| Finished | Oct 02 06:40:40 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417113988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1417113988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1876743326 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 828382736 ps |
| CPU time | 23.5 seconds |
| Started | Oct 02 06:39:37 PM UTC 24 |
| Finished | Oct 02 06:40:02 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876743326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1876743326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.2760020947 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1532042846 ps |
| CPU time | 70.72 seconds |
| Started | Oct 02 06:39:59 PM UTC 24 |
| Finished | Oct 02 06:41:12 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760020947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2760020947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2971567401 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 10836866124 ps |
| CPU time | 130.48 seconds |
| Started | Oct 02 06:40:00 PM UTC 24 |
| Finished | Oct 02 06:42:13 PM UTC 24 |
| Peak memory | 218032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971567401 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2971567401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.113872103 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 591158183 ps |
| CPU time | 23.81 seconds |
| Started | Oct 02 06:40:04 PM UTC 24 |
| Finished | Oct 02 06:40:29 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113872103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.113872103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2523257264 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 597314935 ps |
| CPU time | 18.79 seconds |
| Started | Oct 02 06:40:03 PM UTC 24 |
| Finished | Oct 02 06:40:23 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523257264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2523257264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.2340644238 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1029800395 ps |
| CPU time | 14.53 seconds |
| Started | Oct 02 06:39:57 PM UTC 24 |
| Finished | Oct 02 06:40:12 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340644238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2340644238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2451086820 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 46148771514 ps |
| CPU time | 252.43 seconds |
| Started | Oct 02 06:39:58 PM UTC 24 |
| Finished | Oct 02 06:44:14 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451086820 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2451086820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3170360978 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 43735004917 ps |
| CPU time | 202.64 seconds |
| Started | Oct 02 06:39:58 PM UTC 24 |
| Finished | Oct 02 06:43:24 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170360978 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3170360978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.269138877 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 342024477 ps |
| CPU time | 13.99 seconds |
| Started | Oct 02 06:39:58 PM UTC 24 |
| Finished | Oct 02 06:40:13 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269138877 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.269138877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3569812447 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 97752194 ps |
| CPU time | 11.55 seconds |
| Started | Oct 02 06:40:02 PM UTC 24 |
| Finished | Oct 02 06:40:15 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569812447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3569812447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.2010785222 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 57261280 ps |
| CPU time | 3.27 seconds |
| Started | Oct 02 06:39:52 PM UTC 24 |
| Finished | Oct 02 06:39:57 PM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010785222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2010785222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2529371852 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 13112957463 ps |
| CPU time | 43.33 seconds |
| Started | Oct 02 06:39:55 PM UTC 24 |
| Finished | Oct 02 06:40:40 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529371852 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2529371852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2992637460 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3992040841 ps |
| CPU time | 35.59 seconds |
| Started | Oct 02 06:39:56 PM UTC 24 |
| Finished | Oct 02 06:40:34 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992637460 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2992637460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.236563682 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 50576500 ps |
| CPU time | 3.99 seconds |
| Started | Oct 02 06:39:54 PM UTC 24 |
| Finished | Oct 02 06:39:59 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236563682 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.236563682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1361953815 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1597950843 ps |
| CPU time | 80.77 seconds |
| Started | Oct 02 06:40:05 PM UTC 24 |
| Finished | Oct 02 06:41:27 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361953815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1361953815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.83406955 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2012614582 ps |
| CPU time | 108.9 seconds |
| Started | Oct 02 06:40:08 PM UTC 24 |
| Finished | Oct 02 06:41:59 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83406955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.83406955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1973835195 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4942004445 ps |
| CPU time | 402.77 seconds |
| Started | Oct 02 06:40:08 PM UTC 24 |
| Finished | Oct 02 06:46:57 PM UTC 24 |
| Peak memory | 222260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973835195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1973835195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.271021981 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 121815529 ps |
| CPU time | 15.8 seconds |
| Started | Oct 02 06:40:03 PM UTC 24 |
| Finished | Oct 02 06:40:20 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271021981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.271021981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3847395917 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1462239703 ps |
| CPU time | 58.82 seconds |
| Started | Oct 02 06:40:17 PM UTC 24 |
| Finished | Oct 02 06:41:18 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847395917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3847395917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3501412960 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4051001186 ps |
| CPU time | 48.66 seconds |
| Started | Oct 02 06:40:19 PM UTC 24 |
| Finished | Oct 02 06:41:09 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501412960 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.3501412960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3011864573 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 122803567 ps |
| CPU time | 24.22 seconds |
| Started | Oct 02 06:40:22 PM UTC 24 |
| Finished | Oct 02 06:40:48 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011864573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3011864573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3903104643 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 462925309 ps |
| CPU time | 22.27 seconds |
| Started | Oct 02 06:40:21 PM UTC 24 |
| Finished | Oct 02 06:40:44 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903104643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3903104643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.108260028 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 140303251 ps |
| CPU time | 25.07 seconds |
| Started | Oct 02 06:40:15 PM UTC 24 |
| Finished | Oct 02 06:40:41 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108260028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.108260028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.33911917 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 46119272138 ps |
| CPU time | 295.66 seconds |
| Started | Oct 02 06:40:16 PM UTC 24 |
| Finished | Oct 02 06:45:16 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33911917 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.33911917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1333516179 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3343286348 ps |
| CPU time | 16.17 seconds |
| Started | Oct 02 06:40:16 PM UTC 24 |
| Finished | Oct 02 06:40:33 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333516179 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1333516179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3266229318 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 150798939 ps |
| CPU time | 16.28 seconds |
| Started | Oct 02 06:40:16 PM UTC 24 |
| Finished | Oct 02 06:40:34 PM UTC 24 |
| Peak memory | 216028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266229318 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3266229318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.332090765 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 158543550 ps |
| CPU time | 15.91 seconds |
| Started | Oct 02 06:40:20 PM UTC 24 |
| Finished | Oct 02 06:40:37 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332090765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.332090765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.1829812139 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 137211028 ps |
| CPU time | 5.09 seconds |
| Started | Oct 02 06:40:13 PM UTC 24 |
| Finished | Oct 02 06:40:20 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829812139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1829812139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2839656145 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 7057004319 ps |
| CPU time | 58.76 seconds |
| Started | Oct 02 06:40:13 PM UTC 24 |
| Finished | Oct 02 06:41:14 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839656145 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2839656145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.517573947 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7722704062 ps |
| CPU time | 45.75 seconds |
| Started | Oct 02 06:40:15 PM UTC 24 |
| Finished | Oct 02 06:41:02 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517573947 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.517573947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3919770057 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 44669483 ps |
| CPU time | 3.08 seconds |
| Started | Oct 02 06:40:13 PM UTC 24 |
| Finished | Oct 02 06:40:17 PM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919770057 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3919770057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2029128727 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1417620291 ps |
| CPU time | 31.21 seconds |
| Started | Oct 02 06:40:23 PM UTC 24 |
| Finished | Oct 02 06:40:56 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029128727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2029128727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3309920991 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2589061097 ps |
| CPU time | 117.12 seconds |
| Started | Oct 02 06:40:25 PM UTC 24 |
| Finished | Oct 02 06:42:24 PM UTC 24 |
| Peak memory | 220140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309920991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3309920991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2491848491 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 398562785 ps |
| CPU time | 195.9 seconds |
| Started | Oct 02 06:40:24 PM UTC 24 |
| Finished | Oct 02 06:43:44 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491848491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.2491848491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.989462456 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 811441063 ps |
| CPU time | 146.04 seconds |
| Started | Oct 02 06:40:26 PM UTC 24 |
| Finished | Oct 02 06:42:55 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989462456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.989462456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3209296166 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 519406194 ps |
| CPU time | 27.2 seconds |
| Started | Oct 02 06:40:22 PM UTC 24 |
| Finished | Oct 02 06:40:51 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209296166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3209296166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.777854485 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 131225720 ps |
| CPU time | 24.16 seconds |
| Started | Oct 02 06:40:38 PM UTC 24 |
| Finished | Oct 02 06:41:03 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777854485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.777854485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1958465252 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 102283174462 ps |
| CPU time | 577.21 seconds |
| Started | Oct 02 06:40:41 PM UTC 24 |
| Finished | Oct 02 06:50:25 PM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958465252 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.1958465252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.585842347 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 854917601 ps |
| CPU time | 33.35 seconds |
| Started | Oct 02 06:40:44 PM UTC 24 |
| Finished | Oct 02 06:41:18 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585842347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.585842347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3691255120 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 46291036 ps |
| CPU time | 4.34 seconds |
| Started | Oct 02 06:40:41 PM UTC 24 |
| Finished | Oct 02 06:40:47 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691255120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3691255120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3603731762 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 52038872 ps |
| CPU time | 4.53 seconds |
| Started | Oct 02 06:40:35 PM UTC 24 |
| Finished | Oct 02 06:40:40 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603731762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3603731762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.3459241617 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 47646730614 ps |
| CPU time | 302.95 seconds |
| Started | Oct 02 06:40:35 PM UTC 24 |
| Finished | Oct 02 06:45:42 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459241617 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3459241617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1939795247 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 31026566737 ps |
| CPU time | 351.85 seconds |
| Started | Oct 02 06:40:35 PM UTC 24 |
| Finished | Oct 02 06:46:32 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939795247 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1939795247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.1909019452 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 37873371 ps |
| CPU time | 6.75 seconds |
| Started | Oct 02 06:40:35 PM UTC 24 |
| Finished | Oct 02 06:40:42 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909019452 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1909019452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.4231257190 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3203941526 ps |
| CPU time | 23.23 seconds |
| Started | Oct 02 06:40:41 PM UTC 24 |
| Finished | Oct 02 06:41:06 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231257190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4231257190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.2387170663 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 33870064 ps |
| CPU time | 3.04 seconds |
| Started | Oct 02 06:40:27 PM UTC 24 |
| Finished | Oct 02 06:40:31 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387170663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2387170663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.497764909 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 18072286057 ps |
| CPU time | 40.98 seconds |
| Started | Oct 02 06:40:29 PM UTC 24 |
| Finished | Oct 02 06:41:12 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497764909 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.497764909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1992832936 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4386419088 ps |
| CPU time | 31.34 seconds |
| Started | Oct 02 06:40:32 PM UTC 24 |
| Finished | Oct 02 06:41:05 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992832936 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1992832936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2842976300 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 28620406 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 06:40:29 PM UTC 24 |
| Finished | Oct 02 06:40:34 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842976300 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2842976300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1606484009 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5893150590 ps |
| CPU time | 129.74 seconds |
| Started | Oct 02 06:40:44 PM UTC 24 |
| Finished | Oct 02 06:42:56 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606484009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1606484009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2314396724 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 7177934729 ps |
| CPU time | 171.06 seconds |
| Started | Oct 02 06:40:48 PM UTC 24 |
| Finished | Oct 02 06:43:42 PM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314396724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2314396724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3606545150 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 276331893 ps |
| CPU time | 114.94 seconds |
| Started | Oct 02 06:40:49 PM UTC 24 |
| Finished | Oct 02 06:42:46 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606545150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3606545150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.4163221471 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 62322981 ps |
| CPU time | 14.57 seconds |
| Started | Oct 02 06:40:42 PM UTC 24 |
| Finished | Oct 02 06:40:58 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163221471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4163221471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.375991650 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1127386166 ps |
| CPU time | 53.79 seconds |
| Started | Oct 02 06:41:07 PM UTC 24 |
| Finished | Oct 02 06:42:03 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375991650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.375991650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2034196617 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 14928672944 ps |
| CPU time | 50.79 seconds |
| Started | Oct 02 06:41:09 PM UTC 24 |
| Finished | Oct 02 06:42:02 PM UTC 24 |
| Peak memory | 216112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034196617 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.2034196617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3014924366 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 331160665 ps |
| CPU time | 14.85 seconds |
| Started | Oct 02 06:41:13 PM UTC 24 |
| Finished | Oct 02 06:41:29 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014924366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3014924366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1860481918 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 29570004 ps |
| CPU time | 4.49 seconds |
| Started | Oct 02 06:41:10 PM UTC 24 |
| Finished | Oct 02 06:41:16 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860481918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1860481918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.2033558836 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 564514081 ps |
| CPU time | 27.85 seconds |
| Started | Oct 02 06:41:02 PM UTC 24 |
| Finished | Oct 02 06:41:31 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033558836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2033558836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3364704459 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 52469957910 ps |
| CPU time | 327.84 seconds |
| Started | Oct 02 06:41:04 PM UTC 24 |
| Finished | Oct 02 06:46:36 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364704459 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3364704459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2218231628 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 31285031359 ps |
| CPU time | 224.93 seconds |
| Started | Oct 02 06:41:06 PM UTC 24 |
| Finished | Oct 02 06:44:55 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218231628 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2218231628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2823707148 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 48774763 ps |
| CPU time | 4.76 seconds |
| Started | Oct 02 06:41:03 PM UTC 24 |
| Finished | Oct 02 06:41:08 PM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823707148 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2823707148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3665213224 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1712312680 ps |
| CPU time | 37.53 seconds |
| Started | Oct 02 06:41:10 PM UTC 24 |
| Finished | Oct 02 06:41:49 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665213224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3665213224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2183429677 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 28313803 ps |
| CPU time | 2.93 seconds |
| Started | Oct 02 06:40:52 PM UTC 24 |
| Finished | Oct 02 06:40:56 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183429677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2183429677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1363883332 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 11299195113 ps |
| CPU time | 56.63 seconds |
| Started | Oct 02 06:40:57 PM UTC 24 |
| Finished | Oct 02 06:41:56 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363883332 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1363883332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3656386172 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2563461648 ps |
| CPU time | 28.67 seconds |
| Started | Oct 02 06:40:59 PM UTC 24 |
| Finished | Oct 02 06:41:29 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656386172 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3656386172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2435661038 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 31899212 ps |
| CPU time | 3.55 seconds |
| Started | Oct 02 06:40:56 PM UTC 24 |
| Finished | Oct 02 06:41:01 PM UTC 24 |
| Peak memory | 215752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435661038 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2435661038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.925855662 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 7638084410 ps |
| CPU time | 215.26 seconds |
| Started | Oct 02 06:41:13 PM UTC 24 |
| Finished | Oct 02 06:44:52 PM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925855662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.925855662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2405720005 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 7648794384 ps |
| CPU time | 269.09 seconds |
| Started | Oct 02 06:41:17 PM UTC 24 |
| Finished | Oct 02 06:45:50 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405720005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2405720005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.899645930 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 578215245 ps |
| CPU time | 300.19 seconds |
| Started | Oct 02 06:41:15 PM UTC 24 |
| Finished | Oct 02 06:46:20 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899645930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.899645930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4163962074 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3308372401 ps |
| CPU time | 211.07 seconds |
| Started | Oct 02 06:41:19 PM UTC 24 |
| Finished | Oct 02 06:44:54 PM UTC 24 |
| Peak memory | 232588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163962074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.4163962074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.3765428024 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 203756461 ps |
| CPU time | 21.36 seconds |
| Started | Oct 02 06:41:13 PM UTC 24 |
| Finished | Oct 02 06:41:35 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765428024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3765428024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.1645305948 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1088638855 ps |
| CPU time | 22 seconds |
| Started | Oct 02 06:41:30 PM UTC 24 |
| Finished | Oct 02 06:41:53 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645305948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1645305948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.902168450 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 98327786961 ps |
| CPU time | 570.96 seconds |
| Started | Oct 02 06:41:30 PM UTC 24 |
| Finished | Oct 02 06:51:08 PM UTC 24 |
| Peak memory | 219492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902168450 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.902168450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3829591242 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 123745292 ps |
| CPU time | 5.72 seconds |
| Started | Oct 02 06:41:37 PM UTC 24 |
| Finished | Oct 02 06:41:44 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829591242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3829591242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1445250756 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1230274463 ps |
| CPU time | 17.43 seconds |
| Started | Oct 02 06:41:33 PM UTC 24 |
| Finished | Oct 02 06:41:52 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445250756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1445250756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.317961747 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 38895226 ps |
| CPU time | 5.66 seconds |
| Started | Oct 02 06:41:27 PM UTC 24 |
| Finished | Oct 02 06:41:34 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317961747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.317961747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2649726677 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 12100039965 ps |
| CPU time | 50.42 seconds |
| Started | Oct 02 06:41:27 PM UTC 24 |
| Finished | Oct 02 06:42:19 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649726677 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2649726677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2502346977 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 17457843447 ps |
| CPU time | 181.7 seconds |
| Started | Oct 02 06:41:28 PM UTC 24 |
| Finished | Oct 02 06:44:33 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502346977 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2502346977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.4180250706 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 221788107 ps |
| CPU time | 28.67 seconds |
| Started | Oct 02 06:41:27 PM UTC 24 |
| Finished | Oct 02 06:41:57 PM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180250706 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4180250706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2391525311 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 7113107939 ps |
| CPU time | 42.04 seconds |
| Started | Oct 02 06:41:32 PM UTC 24 |
| Finished | Oct 02 06:42:16 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391525311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2391525311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2252917654 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 211366343 ps |
| CPU time | 5.12 seconds |
| Started | Oct 02 06:41:19 PM UTC 24 |
| Finished | Oct 02 06:41:26 PM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252917654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2252917654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1059440890 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 5579285933 ps |
| CPU time | 36.7 seconds |
| Started | Oct 02 06:41:20 PM UTC 24 |
| Finished | Oct 02 06:41:59 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059440890 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1059440890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.4125178463 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5127596064 ps |
| CPU time | 32.34 seconds |
| Started | Oct 02 06:41:27 PM UTC 24 |
| Finished | Oct 02 06:42:01 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125178463 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4125178463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3009734163 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 40223642 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 06:41:20 PM UTC 24 |
| Finished | Oct 02 06:41:25 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009734163 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3009734163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.3087710057 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1074951040 ps |
| CPU time | 105.4 seconds |
| Started | Oct 02 06:41:46 PM UTC 24 |
| Finished | Oct 02 06:43:33 PM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087710057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3087710057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.680003504 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 9306357538 ps |
| CPU time | 244.47 seconds |
| Started | Oct 02 06:41:50 PM UTC 24 |
| Finished | Oct 02 06:45:58 PM UTC 24 |
| Peak memory | 222344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680003504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.680003504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1206843495 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10514564147 ps |
| CPU time | 334.76 seconds |
| Started | Oct 02 06:41:47 PM UTC 24 |
| Finished | Oct 02 06:47:27 PM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206843495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1206843495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3699055262 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 6381714710 ps |
| CPU time | 363.04 seconds |
| Started | Oct 02 06:41:53 PM UTC 24 |
| Finished | Oct 02 06:48:02 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699055262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3699055262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3231892766 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 4221996665 ps |
| CPU time | 41.3 seconds |
| Started | Oct 02 06:41:35 PM UTC 24 |
| Finished | Oct 02 06:42:17 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231892766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3231892766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.3214594910 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 958989137 ps |
| CPU time | 16.16 seconds |
| Started | Oct 02 06:42:00 PM UTC 24 |
| Finished | Oct 02 06:42:17 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214594910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3214594910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2442218843 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 65016122817 ps |
| CPU time | 220.3 seconds |
| Started | Oct 02 06:42:01 PM UTC 24 |
| Finished | Oct 02 06:45:45 PM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442218843 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2442218843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.428453451 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 115178036 ps |
| CPU time | 5.27 seconds |
| Started | Oct 02 06:42:09 PM UTC 24 |
| Finished | Oct 02 06:42:15 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428453451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.428453451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3450729836 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 111877603 ps |
| CPU time | 4.62 seconds |
| Started | Oct 02 06:42:03 PM UTC 24 |
| Finished | Oct 02 06:42:09 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450729836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3450729836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.1414284705 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 156218366 ps |
| CPU time | 7.96 seconds |
| Started | Oct 02 06:41:59 PM UTC 24 |
| Finished | Oct 02 06:42:08 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414284705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1414284705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.514544046 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 26031661080 ps |
| CPU time | 140.47 seconds |
| Started | Oct 02 06:42:00 PM UTC 24 |
| Finished | Oct 02 06:44:23 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514544046 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.514544046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3152706972 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 40916667108 ps |
| CPU time | 275.51 seconds |
| Started | Oct 02 06:42:00 PM UTC 24 |
| Finished | Oct 02 06:46:39 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152706972 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3152706972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.508512992 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 133066715 ps |
| CPU time | 16.11 seconds |
| Started | Oct 02 06:41:59 PM UTC 24 |
| Finished | Oct 02 06:42:16 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508512992 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.508512992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2940264338 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 924467207 ps |
| CPU time | 14.37 seconds |
| Started | Oct 02 06:42:03 PM UTC 24 |
| Finished | Oct 02 06:42:19 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940264338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2940264338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.4237231265 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 36505119 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 06:41:53 PM UTC 24 |
| Finished | Oct 02 06:41:58 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237231265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4237231265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2709036835 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3983834092 ps |
| CPU time | 40.96 seconds |
| Started | Oct 02 06:41:56 PM UTC 24 |
| Finished | Oct 02 06:42:39 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709036835 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2709036835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2397757868 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3250612723 ps |
| CPU time | 35.88 seconds |
| Started | Oct 02 06:41:58 PM UTC 24 |
| Finished | Oct 02 06:42:35 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397757868 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2397757868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1347864070 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 114871497 ps |
| CPU time | 3.7 seconds |
| Started | Oct 02 06:41:54 PM UTC 24 |
| Finished | Oct 02 06:41:59 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347864070 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1347864070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2126040731 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 780200667 ps |
| CPU time | 100.3 seconds |
| Started | Oct 02 06:42:10 PM UTC 24 |
| Finished | Oct 02 06:43:52 PM UTC 24 |
| Peak memory | 219876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126040731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2126040731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4274491271 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 9272531812 ps |
| CPU time | 231.66 seconds |
| Started | Oct 02 06:42:14 PM UTC 24 |
| Finished | Oct 02 06:46:10 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274491271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4274491271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3252731201 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3244788107 ps |
| CPU time | 258.41 seconds |
| Started | Oct 02 06:42:12 PM UTC 24 |
| Finished | Oct 02 06:46:35 PM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252731201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3252731201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2346977985 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 8363887418 ps |
| CPU time | 330.16 seconds |
| Started | Oct 02 06:42:16 PM UTC 24 |
| Finished | Oct 02 06:47:51 PM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346977985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2346977985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.727414525 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1106010481 ps |
| CPU time | 16.79 seconds |
| Started | Oct 02 06:42:03 PM UTC 24 |
| Finished | Oct 02 06:42:21 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727414525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.727414525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1999718774 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2799026958 ps |
| CPU time | 52.47 seconds |
| Started | Oct 02 06:42:22 PM UTC 24 |
| Finished | Oct 02 06:43:16 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999718774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1999718774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2323054400 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 44301738812 ps |
| CPU time | 278.21 seconds |
| Started | Oct 02 06:42:23 PM UTC 24 |
| Finished | Oct 02 06:47:06 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323054400 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2323054400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3346750546 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 77156390 ps |
| CPU time | 7.62 seconds |
| Started | Oct 02 06:42:28 PM UTC 24 |
| Finished | Oct 02 06:42:37 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346750546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3346750546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.3761048125 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 250448882 ps |
| CPU time | 12.1 seconds |
| Started | Oct 02 06:42:26 PM UTC 24 |
| Finished | Oct 02 06:42:39 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761048125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3761048125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.2453420681 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 166769549 ps |
| CPU time | 20.81 seconds |
| Started | Oct 02 06:42:19 PM UTC 24 |
| Finished | Oct 02 06:42:41 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453420681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2453420681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.212043746 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 13228660100 ps |
| CPU time | 54.22 seconds |
| Started | Oct 02 06:42:20 PM UTC 24 |
| Finished | Oct 02 06:43:16 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212043746 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.212043746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.409526789 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 33911211987 ps |
| CPU time | 185.17 seconds |
| Started | Oct 02 06:42:20 PM UTC 24 |
| Finished | Oct 02 06:45:28 PM UTC 24 |
| Peak memory | 216100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409526789 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.409526789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1221240351 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 129138503 ps |
| CPU time | 8.68 seconds |
| Started | Oct 02 06:42:19 PM UTC 24 |
| Finished | Oct 02 06:42:29 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221240351 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1221240351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.92967767 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 220413645 ps |
| CPU time | 24.93 seconds |
| Started | Oct 02 06:42:24 PM UTC 24 |
| Finished | Oct 02 06:42:51 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92967767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.92967767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1596316654 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 224564723 ps |
| CPU time | 6.17 seconds |
| Started | Oct 02 06:42:16 PM UTC 24 |
| Finished | Oct 02 06:42:23 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596316654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1596316654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1263131190 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4274001956 ps |
| CPU time | 41.72 seconds |
| Started | Oct 02 06:42:18 PM UTC 24 |
| Finished | Oct 02 06:43:01 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263131190 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1263131190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3334802063 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3387495004 ps |
| CPU time | 37.6 seconds |
| Started | Oct 02 06:42:18 PM UTC 24 |
| Finished | Oct 02 06:42:57 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334802063 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3334802063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.379443560 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 28058774 ps |
| CPU time | 3.75 seconds |
| Started | Oct 02 06:42:18 PM UTC 24 |
| Finished | Oct 02 06:42:22 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379443560 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.379443560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.624213228 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 8456156560 ps |
| CPU time | 124.85 seconds |
| Started | Oct 02 06:42:30 PM UTC 24 |
| Finished | Oct 02 06:44:38 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624213228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.624213228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.178403223 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 12060669476 ps |
| CPU time | 164.21 seconds |
| Started | Oct 02 06:42:38 PM UTC 24 |
| Finished | Oct 02 06:45:25 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178403223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.178403223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1546172990 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1185264331 ps |
| CPU time | 400.98 seconds |
| Started | Oct 02 06:42:35 PM UTC 24 |
| Finished | Oct 02 06:49:23 PM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546172990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1546172990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3919115285 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2969288175 ps |
| CPU time | 196.65 seconds |
| Started | Oct 02 06:42:39 PM UTC 24 |
| Finished | Oct 02 06:45:59 PM UTC 24 |
| Peak memory | 232720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919115285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3919115285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.3730914002 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 996091824 ps |
| CPU time | 24.83 seconds |
| Started | Oct 02 06:42:27 PM UTC 24 |
| Finished | Oct 02 06:42:53 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730914002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3730914002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1864741870 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 180929676 ps |
| CPU time | 10.32 seconds |
| Started | Oct 02 06:42:50 PM UTC 24 |
| Finished | Oct 02 06:43:01 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864741870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1864741870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3302606598 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 81078598840 ps |
| CPU time | 563.7 seconds |
| Started | Oct 02 06:42:52 PM UTC 24 |
| Finished | Oct 02 06:52:24 PM UTC 24 |
| Peak memory | 219496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302606598 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3302606598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4078484357 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 690437471 ps |
| CPU time | 22.66 seconds |
| Started | Oct 02 06:42:56 PM UTC 24 |
| Finished | Oct 02 06:43:20 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078484357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4078484357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1681303339 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4378078705 ps |
| CPU time | 55.6 seconds |
| Started | Oct 02 06:42:55 PM UTC 24 |
| Finished | Oct 02 06:43:52 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681303339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1681303339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2128821164 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 291795599 ps |
| CPU time | 7.45 seconds |
| Started | Oct 02 06:42:45 PM UTC 24 |
| Finished | Oct 02 06:42:54 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128821164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2128821164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2216089248 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 37770323501 ps |
| CPU time | 226.57 seconds |
| Started | Oct 02 06:42:48 PM UTC 24 |
| Finished | Oct 02 06:46:37 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216089248 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2216089248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4103911775 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 6115778179 ps |
| CPU time | 82.21 seconds |
| Started | Oct 02 06:42:50 PM UTC 24 |
| Finished | Oct 02 06:44:14 PM UTC 24 |
| Peak memory | 216040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103911775 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4103911775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3991116110 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 291304263 ps |
| CPU time | 24.58 seconds |
| Started | Oct 02 06:42:46 PM UTC 24 |
| Finished | Oct 02 06:43:12 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991116110 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3991116110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1484364398 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 378657274 ps |
| CPU time | 25.28 seconds |
| Started | Oct 02 06:42:53 PM UTC 24 |
| Finished | Oct 02 06:43:20 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484364398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1484364398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1225156951 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 75804436 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 06:42:40 PM UTC 24 |
| Finished | Oct 02 06:42:44 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225156951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1225156951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1965944250 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 8778533834 ps |
| CPU time | 70.04 seconds |
| Started | Oct 02 06:42:42 PM UTC 24 |
| Finished | Oct 02 06:43:54 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965944250 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1965944250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3172546703 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4132883197 ps |
| CPU time | 25.02 seconds |
| Started | Oct 02 06:42:45 PM UTC 24 |
| Finished | Oct 02 06:43:11 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172546703 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3172546703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3322072233 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 42672016 ps |
| CPU time | 3.17 seconds |
| Started | Oct 02 06:42:40 PM UTC 24 |
| Finished | Oct 02 06:42:44 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322072233 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3322072233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1251318763 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 834803412 ps |
| CPU time | 112.19 seconds |
| Started | Oct 02 06:42:57 PM UTC 24 |
| Finished | Oct 02 06:44:52 PM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251318763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1251318763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.445185425 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2078096512 ps |
| CPU time | 36.87 seconds |
| Started | Oct 02 06:43:01 PM UTC 24 |
| Finished | Oct 02 06:43:40 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445185425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.445185425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1422724234 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 18758078721 ps |
| CPU time | 581.94 seconds |
| Started | Oct 02 06:42:57 PM UTC 24 |
| Finished | Oct 02 06:52:47 PM UTC 24 |
| Peak memory | 234252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422724234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1422724234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.884274290 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 252558589 ps |
| CPU time | 102.15 seconds |
| Started | Oct 02 06:43:03 PM UTC 24 |
| Finished | Oct 02 06:44:47 PM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884274290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.884274290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2852429724 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1076338424 ps |
| CPU time | 36.08 seconds |
| Started | Oct 02 06:42:55 PM UTC 24 |
| Finished | Oct 02 06:43:32 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852429724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2852429724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.2378793782 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 671443501 ps |
| CPU time | 17.71 seconds |
| Started | Oct 02 06:43:21 PM UTC 24 |
| Finished | Oct 02 06:43:40 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378793782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2378793782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1012705009 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 91266176659 ps |
| CPU time | 455.93 seconds |
| Started | Oct 02 06:43:25 PM UTC 24 |
| Finished | Oct 02 06:51:07 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012705009 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1012705009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.524986171 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 511872799 ps |
| CPU time | 24.44 seconds |
| Started | Oct 02 06:43:40 PM UTC 24 |
| Finished | Oct 02 06:44:06 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524986171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.524986171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.1671171610 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 38951442 ps |
| CPU time | 5.02 seconds |
| Started | Oct 02 06:43:33 PM UTC 24 |
| Finished | Oct 02 06:43:39 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671171610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1671171610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.4286240434 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1193646101 ps |
| CPU time | 29.36 seconds |
| Started | Oct 02 06:43:17 PM UTC 24 |
| Finished | Oct 02 06:43:48 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286240434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.4286240434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3243590141 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 34886014282 ps |
| CPU time | 126.79 seconds |
| Started | Oct 02 06:43:18 PM UTC 24 |
| Finished | Oct 02 06:45:27 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243590141 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3243590141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1436094326 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1880837167 ps |
| CPU time | 25.85 seconds |
| Started | Oct 02 06:43:21 PM UTC 24 |
| Finished | Oct 02 06:43:48 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436094326 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1436094326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.2459614385 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 341917326 ps |
| CPU time | 19.08 seconds |
| Started | Oct 02 06:43:18 PM UTC 24 |
| Finished | Oct 02 06:43:38 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459614385 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2459614385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.2197613296 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4364371858 ps |
| CPU time | 29.38 seconds |
| Started | Oct 02 06:43:26 PM UTC 24 |
| Finished | Oct 02 06:43:57 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197613296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2197613296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.1349969006 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 30445986 ps |
| CPU time | 3.58 seconds |
| Started | Oct 02 06:43:08 PM UTC 24 |
| Finished | Oct 02 06:43:13 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349969006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1349969006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.859727771 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 6823916339 ps |
| CPU time | 62.84 seconds |
| Started | Oct 02 06:43:14 PM UTC 24 |
| Finished | Oct 02 06:44:18 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859727771 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.859727771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1579275331 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7688024067 ps |
| CPU time | 45.78 seconds |
| Started | Oct 02 06:43:14 PM UTC 24 |
| Finished | Oct 02 06:44:01 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579275331 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1579275331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2734804316 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 64095321 ps |
| CPU time | 3.4 seconds |
| Started | Oct 02 06:43:12 PM UTC 24 |
| Finished | Oct 02 06:43:17 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734804316 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2734804316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.577166093 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 5745064346 ps |
| CPU time | 159.47 seconds |
| Started | Oct 02 06:43:41 PM UTC 24 |
| Finished | Oct 02 06:46:23 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577166093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.577166093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3130994968 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 13194033721 ps |
| CPU time | 227.9 seconds |
| Started | Oct 02 06:43:42 PM UTC 24 |
| Finished | Oct 02 06:47:33 PM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130994968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3130994968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1384614928 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 333670239 ps |
| CPU time | 287.9 seconds |
| Started | Oct 02 06:43:41 PM UTC 24 |
| Finished | Oct 02 06:48:33 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384614928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1384614928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3966264768 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 164002431 ps |
| CPU time | 47.65 seconds |
| Started | Oct 02 06:43:43 PM UTC 24 |
| Finished | Oct 02 06:44:33 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966264768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3966264768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1769956982 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 504989050 ps |
| CPU time | 25.34 seconds |
| Started | Oct 02 06:43:35 PM UTC 24 |
| Finished | Oct 02 06:44:01 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769956982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1769956982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.4015461215 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 347599502 ps |
| CPU time | 23.84 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:33:25 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015461215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.4015461215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3669080205 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 73625595487 ps |
| CPU time | 669.57 seconds |
| Started | Oct 02 06:33:03 PM UTC 24 |
| Finished | Oct 02 06:44:21 PM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669080205 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3669080205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.134570842 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 468222728 ps |
| CPU time | 7.87 seconds |
| Started | Oct 02 06:33:06 PM UTC 24 |
| Finished | Oct 02 06:33:15 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134570842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.134570842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2457319990 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 290771870 ps |
| CPU time | 11.39 seconds |
| Started | Oct 02 06:33:03 PM UTC 24 |
| Finished | Oct 02 06:33:16 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457319990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2457319990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3585460 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 867934902 ps |
| CPU time | 20.29 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:33:21 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3585460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.3275649187 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 26591767155 ps |
| CPU time | 201.11 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:36:24 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275649187 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3275649187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4098184068 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 20153599048 ps |
| CPU time | 59.66 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:34:01 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098184068 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4098184068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.556473423 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 339243800 ps |
| CPU time | 28.87 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:33:30 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556473423 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.556473423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.2055621911 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2840748834 ps |
| CPU time | 33.67 seconds |
| Started | Oct 02 06:33:03 PM UTC 24 |
| Finished | Oct 02 06:33:38 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055621911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2055621911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3303567805 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 26777830 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 06:32:58 PM UTC 24 |
| Finished | Oct 02 06:33:02 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303567805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3303567805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.4065135214 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 26463647711 ps |
| CPU time | 71.95 seconds |
| Started | Oct 02 06:32:58 PM UTC 24 |
| Finished | Oct 02 06:34:12 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065135214 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4065135214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.584865606 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5342997879 ps |
| CPU time | 36.8 seconds |
| Started | Oct 02 06:33:00 PM UTC 24 |
| Finished | Oct 02 06:33:38 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584865606 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.584865606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3963911523 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 27123708 ps |
| CPU time | 2.92 seconds |
| Started | Oct 02 06:32:58 PM UTC 24 |
| Finished | Oct 02 06:33:02 PM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963911523 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3963911523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.4035098776 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 9890116432 ps |
| CPU time | 231.23 seconds |
| Started | Oct 02 06:33:07 PM UTC 24 |
| Finished | Oct 02 06:37:02 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035098776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4035098776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.760978300 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 448453196 ps |
| CPU time | 46.94 seconds |
| Started | Oct 02 06:33:10 PM UTC 24 |
| Finished | Oct 02 06:33:58 PM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760978300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.760978300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3420678652 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 228932346 ps |
| CPU time | 81.34 seconds |
| Started | Oct 02 06:33:08 PM UTC 24 |
| Finished | Oct 02 06:34:32 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420678652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3420678652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.915148001 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 204395230 ps |
| CPU time | 89.44 seconds |
| Started | Oct 02 06:33:11 PM UTC 24 |
| Finished | Oct 02 06:34:42 PM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915148001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.915148001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2655103965 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 262964033 ps |
| CPU time | 11.35 seconds |
| Started | Oct 02 06:33:04 PM UTC 24 |
| Finished | Oct 02 06:33:17 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655103965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2655103965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.4177371522 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3669708540 ps |
| CPU time | 39.47 seconds |
| Started | Oct 02 06:43:57 PM UTC 24 |
| Finished | Oct 02 06:44:39 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177371522 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.4177371522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2460016301 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 64929747 ps |
| CPU time | 10.17 seconds |
| Started | Oct 02 06:44:07 PM UTC 24 |
| Finished | Oct 02 06:44:18 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460016301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2460016301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.819158058 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 337260932 ps |
| CPU time | 27.81 seconds |
| Started | Oct 02 06:44:03 PM UTC 24 |
| Finished | Oct 02 06:44:32 PM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819158058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.819158058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.2235781122 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 145283773 ps |
| CPU time | 22.81 seconds |
| Started | Oct 02 06:43:54 PM UTC 24 |
| Finished | Oct 02 06:44:18 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235781122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2235781122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2674978300 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 28188435429 ps |
| CPU time | 147.81 seconds |
| Started | Oct 02 06:43:54 PM UTC 24 |
| Finished | Oct 02 06:46:25 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674978300 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2674978300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.4274222043 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 16243990875 ps |
| CPU time | 153.56 seconds |
| Started | Oct 02 06:43:55 PM UTC 24 |
| Finished | Oct 02 06:46:31 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274222043 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4274222043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.4173919295 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 81380009 ps |
| CPU time | 10.61 seconds |
| Started | Oct 02 06:43:54 PM UTC 24 |
| Finished | Oct 02 06:44:06 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173919295 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4173919295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.2858772959 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 368725383 ps |
| CPU time | 11.89 seconds |
| Started | Oct 02 06:44:02 PM UTC 24 |
| Finished | Oct 02 06:44:15 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858772959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2858772959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.3077737966 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 129122495 ps |
| CPU time | 6.16 seconds |
| Started | Oct 02 06:43:45 PM UTC 24 |
| Finished | Oct 02 06:43:52 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077737966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3077737966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2088480217 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 14952600015 ps |
| CPU time | 48.46 seconds |
| Started | Oct 02 06:43:48 PM UTC 24 |
| Finished | Oct 02 06:44:38 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088480217 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2088480217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2663654764 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4338382702 ps |
| CPU time | 33.35 seconds |
| Started | Oct 02 06:43:54 PM UTC 24 |
| Finished | Oct 02 06:44:29 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663654764 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2663654764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3387679593 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 115307844 ps |
| CPU time | 3.77 seconds |
| Started | Oct 02 06:43:48 PM UTC 24 |
| Finished | Oct 02 06:43:53 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387679593 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3387679593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2155945060 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 11749300670 ps |
| CPU time | 105.76 seconds |
| Started | Oct 02 06:44:08 PM UTC 24 |
| Finished | Oct 02 06:45:56 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155945060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2155945060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.288134840 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1135732605 ps |
| CPU time | 33.44 seconds |
| Started | Oct 02 06:44:16 PM UTC 24 |
| Finished | Oct 02 06:44:51 PM UTC 24 |
| Peak memory | 215552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288134840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.288134840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.403164825 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1684112289 ps |
| CPU time | 423.93 seconds |
| Started | Oct 02 06:44:16 PM UTC 24 |
| Finished | Oct 02 06:51:27 PM UTC 24 |
| Peak memory | 219508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403164825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.403164825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1292961669 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2355570844 ps |
| CPU time | 416.24 seconds |
| Started | Oct 02 06:44:16 PM UTC 24 |
| Finished | Oct 02 06:51:19 PM UTC 24 |
| Peak memory | 222544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292961669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1292961669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3384591174 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 800960195 ps |
| CPU time | 24.46 seconds |
| Started | Oct 02 06:44:07 PM UTC 24 |
| Finished | Oct 02 06:44:33 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384591174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3384591174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3191916183 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1992833540 ps |
| CPU time | 35.63 seconds |
| Started | Oct 02 06:44:29 PM UTC 24 |
| Finished | Oct 02 06:45:06 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191916183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3191916183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1526217408 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 24866398057 ps |
| CPU time | 156.09 seconds |
| Started | Oct 02 06:44:33 PM UTC 24 |
| Finished | Oct 02 06:47:11 PM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526217408 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1526217408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2003828087 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 689491834 ps |
| CPU time | 24.56 seconds |
| Started | Oct 02 06:44:40 PM UTC 24 |
| Finished | Oct 02 06:45:05 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003828087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2003828087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1424483099 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1032041602 ps |
| CPU time | 32.78 seconds |
| Started | Oct 02 06:44:35 PM UTC 24 |
| Finished | Oct 02 06:45:09 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424483099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1424483099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.2624111349 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 113009609 ps |
| CPU time | 18.7 seconds |
| Started | Oct 02 06:44:24 PM UTC 24 |
| Finished | Oct 02 06:44:44 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624111349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2624111349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.4158577050 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 18900961361 ps |
| CPU time | 140.73 seconds |
| Started | Oct 02 06:44:26 PM UTC 24 |
| Finished | Oct 02 06:46:49 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158577050 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4158577050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3831815982 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 15410161519 ps |
| CPU time | 151.92 seconds |
| Started | Oct 02 06:44:26 PM UTC 24 |
| Finished | Oct 02 06:47:01 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831815982 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3831815982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3983051265 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 333191434 ps |
| CPU time | 30.88 seconds |
| Started | Oct 02 06:44:26 PM UTC 24 |
| Finished | Oct 02 06:44:58 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983051265 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3983051265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.263478405 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2031588891 ps |
| CPU time | 30.74 seconds |
| Started | Oct 02 06:44:35 PM UTC 24 |
| Finished | Oct 02 06:45:07 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263478405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.263478405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.4192783616 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 33938590 ps |
| CPU time | 3.88 seconds |
| Started | Oct 02 06:44:19 PM UTC 24 |
| Finished | Oct 02 06:44:24 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192783616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4192783616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1110675000 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 19590976360 ps |
| CPU time | 55.49 seconds |
| Started | Oct 02 06:44:19 PM UTC 24 |
| Finished | Oct 02 06:45:17 PM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110675000 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1110675000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1704170995 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4766995332 ps |
| CPU time | 54.57 seconds |
| Started | Oct 02 06:44:22 PM UTC 24 |
| Finished | Oct 02 06:45:18 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704170995 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1704170995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2218856664 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 48131855 ps |
| CPU time | 3.36 seconds |
| Started | Oct 02 06:44:19 PM UTC 24 |
| Finished | Oct 02 06:44:24 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218856664 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2218856664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3192775246 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 13066987187 ps |
| CPU time | 155.87 seconds |
| Started | Oct 02 06:44:40 PM UTC 24 |
| Finished | Oct 02 06:47:18 PM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192775246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3192775246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.605325933 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1743668734 ps |
| CPU time | 49.16 seconds |
| Started | Oct 02 06:44:45 PM UTC 24 |
| Finished | Oct 02 06:45:36 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605325933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.605325933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2292896322 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 529785926 ps |
| CPU time | 188.84 seconds |
| Started | Oct 02 06:44:40 PM UTC 24 |
| Finished | Oct 02 06:47:52 PM UTC 24 |
| Peak memory | 219888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292896322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2292896322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2504851938 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6285859891 ps |
| CPU time | 302.32 seconds |
| Started | Oct 02 06:44:46 PM UTC 24 |
| Finished | Oct 02 06:49:53 PM UTC 24 |
| Peak memory | 222412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504851938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2504851938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.51038116 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 242810199 ps |
| CPU time | 12.44 seconds |
| Started | Oct 02 06:44:35 PM UTC 24 |
| Finished | Oct 02 06:44:48 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51038116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.51038116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.768521252 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 927079246 ps |
| CPU time | 38.32 seconds |
| Started | Oct 02 06:44:57 PM UTC 24 |
| Finished | Oct 02 06:45:36 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768521252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.768521252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1890505628 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 46070490828 ps |
| CPU time | 179.19 seconds |
| Started | Oct 02 06:44:57 PM UTC 24 |
| Finished | Oct 02 06:47:59 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890505628 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1890505628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3438413725 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 279351888 ps |
| CPU time | 13.78 seconds |
| Started | Oct 02 06:45:08 PM UTC 24 |
| Finished | Oct 02 06:45:23 PM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438413725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3438413725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2910399179 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2856047476 ps |
| CPU time | 35.7 seconds |
| Started | Oct 02 06:44:59 PM UTC 24 |
| Finished | Oct 02 06:45:36 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910399179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2910399179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.2440806712 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 283186274 ps |
| CPU time | 19.69 seconds |
| Started | Oct 02 06:44:54 PM UTC 24 |
| Finished | Oct 02 06:45:15 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440806712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2440806712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.823779810 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 28331812639 ps |
| CPU time | 140.56 seconds |
| Started | Oct 02 06:44:54 PM UTC 24 |
| Finished | Oct 02 06:47:17 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823779810 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.823779810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.645520176 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 20545166022 ps |
| CPU time | 89.22 seconds |
| Started | Oct 02 06:44:57 PM UTC 24 |
| Finished | Oct 02 06:46:28 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645520176 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.645520176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.3585354221 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 171669112 ps |
| CPU time | 23.1 seconds |
| Started | Oct 02 06:44:54 PM UTC 24 |
| Finished | Oct 02 06:45:18 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585354221 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3585354221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.3007237909 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2391581990 ps |
| CPU time | 38.95 seconds |
| Started | Oct 02 06:44:57 PM UTC 24 |
| Finished | Oct 02 06:45:37 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007237909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3007237909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.320372928 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 190992030 ps |
| CPU time | 6.41 seconds |
| Started | Oct 02 06:44:47 PM UTC 24 |
| Finished | Oct 02 06:44:54 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320372928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.320372928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.650807682 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 9750680488 ps |
| CPU time | 55.5 seconds |
| Started | Oct 02 06:44:50 PM UTC 24 |
| Finished | Oct 02 06:45:47 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650807682 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.650807682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.166716677 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6094144103 ps |
| CPU time | 40.75 seconds |
| Started | Oct 02 06:44:52 PM UTC 24 |
| Finished | Oct 02 06:45:35 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166716677 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.166716677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3286020823 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 56617807 ps |
| CPU time | 3.46 seconds |
| Started | Oct 02 06:44:48 PM UTC 24 |
| Finished | Oct 02 06:44:53 PM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286020823 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3286020823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2604414044 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 26991122073 ps |
| CPU time | 177.17 seconds |
| Started | Oct 02 06:45:08 PM UTC 24 |
| Finished | Oct 02 06:48:09 PM UTC 24 |
| Peak memory | 222248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604414044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2604414044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.180031631 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 26940422696 ps |
| CPU time | 305.96 seconds |
| Started | Oct 02 06:45:13 PM UTC 24 |
| Finished | Oct 02 06:50:24 PM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180031631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.180031631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4202201103 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 81211646 ps |
| CPU time | 85.69 seconds |
| Started | Oct 02 06:45:10 PM UTC 24 |
| Finished | Oct 02 06:46:37 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202201103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.4202201103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1517933455 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 256755761 ps |
| CPU time | 116.27 seconds |
| Started | Oct 02 06:45:16 PM UTC 24 |
| Finished | Oct 02 06:47:15 PM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517933455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1517933455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.570827138 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 113253805 ps |
| CPU time | 9.07 seconds |
| Started | Oct 02 06:45:07 PM UTC 24 |
| Finished | Oct 02 06:45:17 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570827138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.570827138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.2843924880 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2380811180 ps |
| CPU time | 73.02 seconds |
| Started | Oct 02 06:45:26 PM UTC 24 |
| Finished | Oct 02 06:46:41 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843924880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2843924880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1928652726 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 14701113372 ps |
| CPU time | 121.05 seconds |
| Started | Oct 02 06:45:28 PM UTC 24 |
| Finished | Oct 02 06:47:32 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928652726 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1928652726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.433911335 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 619429226 ps |
| CPU time | 14.98 seconds |
| Started | Oct 02 06:45:36 PM UTC 24 |
| Finished | Oct 02 06:45:52 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433911335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.433911335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.2708428169 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 573451842 ps |
| CPU time | 12.38 seconds |
| Started | Oct 02 06:45:29 PM UTC 24 |
| Finished | Oct 02 06:45:43 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708428169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2708428169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3482228441 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 176437084 ps |
| CPU time | 6.54 seconds |
| Started | Oct 02 06:45:19 PM UTC 24 |
| Finished | Oct 02 06:45:27 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482228441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3482228441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.3174961221 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 14963669477 ps |
| CPU time | 51.08 seconds |
| Started | Oct 02 06:45:24 PM UTC 24 |
| Finished | Oct 02 06:46:17 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174961221 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3174961221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.733807338 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 38210646345 ps |
| CPU time | 254.83 seconds |
| Started | Oct 02 06:45:25 PM UTC 24 |
| Finished | Oct 02 06:49:45 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733807338 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.733807338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.4271229267 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 31760683 ps |
| CPU time | 4.62 seconds |
| Started | Oct 02 06:45:24 PM UTC 24 |
| Finished | Oct 02 06:45:30 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271229267 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.4271229267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3183036758 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3362491271 ps |
| CPU time | 32.26 seconds |
| Started | Oct 02 06:45:28 PM UTC 24 |
| Finished | Oct 02 06:46:02 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183036758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3183036758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2175680112 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 23106929 ps |
| CPU time | 3.32 seconds |
| Started | Oct 02 06:45:18 PM UTC 24 |
| Finished | Oct 02 06:45:22 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175680112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2175680112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1682988894 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 9001652544 ps |
| CPU time | 43.82 seconds |
| Started | Oct 02 06:45:18 PM UTC 24 |
| Finished | Oct 02 06:46:03 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682988894 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1682988894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2819807504 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3270615388 ps |
| CPU time | 33.41 seconds |
| Started | Oct 02 06:45:19 PM UTC 24 |
| Finished | Oct 02 06:45:54 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819807504 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2819807504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3501343942 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 34150195 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 06:45:18 PM UTC 24 |
| Finished | Oct 02 06:45:22 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501343942 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3501343942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.4161467685 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 7441199132 ps |
| CPU time | 133.6 seconds |
| Started | Oct 02 06:45:38 PM UTC 24 |
| Finished | Oct 02 06:47:55 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161467685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4161467685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.4016819883 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4653585838 ps |
| CPU time | 129.26 seconds |
| Started | Oct 02 06:45:38 PM UTC 24 |
| Finished | Oct 02 06:47:50 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016819883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4016819883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.367457705 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3402217726 ps |
| CPU time | 458.31 seconds |
| Started | Oct 02 06:45:38 PM UTC 24 |
| Finished | Oct 02 06:53:23 PM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367457705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.367457705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2861295920 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 96260998 ps |
| CPU time | 20.14 seconds |
| Started | Oct 02 06:45:38 PM UTC 24 |
| Finished | Oct 02 06:46:00 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861295920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2861295920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.594748939 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 228504788 ps |
| CPU time | 9.51 seconds |
| Started | Oct 02 06:45:31 PM UTC 24 |
| Finished | Oct 02 06:45:41 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594748939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.594748939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1602592389 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42579457 ps |
| CPU time | 10.07 seconds |
| Started | Oct 02 06:45:52 PM UTC 24 |
| Finished | Oct 02 06:46:03 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602592389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1602592389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3014486123 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 123024735016 ps |
| CPU time | 660.2 seconds |
| Started | Oct 02 06:45:54 PM UTC 24 |
| Finished | Oct 02 06:57:02 PM UTC 24 |
| Peak memory | 219756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014486123 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3014486123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.445656342 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 340799604 ps |
| CPU time | 14.27 seconds |
| Started | Oct 02 06:46:00 PM UTC 24 |
| Finished | Oct 02 06:46:15 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445656342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.445656342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.2688741340 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 97723001 ps |
| CPU time | 4.2 seconds |
| Started | Oct 02 06:45:57 PM UTC 24 |
| Finished | Oct 02 06:46:02 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688741340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2688741340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.662041818 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 626655724 ps |
| CPU time | 18.48 seconds |
| Started | Oct 02 06:45:47 PM UTC 24 |
| Finished | Oct 02 06:46:07 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662041818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.662041818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.3238413342 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4451637975 ps |
| CPU time | 42.27 seconds |
| Started | Oct 02 06:45:48 PM UTC 24 |
| Finished | Oct 02 06:46:32 PM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238413342 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3238413342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.226155017 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 19099438438 ps |
| CPU time | 198.94 seconds |
| Started | Oct 02 06:45:51 PM UTC 24 |
| Finished | Oct 02 06:49:13 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226155017 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.226155017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3642888675 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 195824202 ps |
| CPU time | 15.2 seconds |
| Started | Oct 02 06:45:48 PM UTC 24 |
| Finished | Oct 02 06:46:05 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642888675 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3642888675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.1301406272 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1087494695 ps |
| CPU time | 19.81 seconds |
| Started | Oct 02 06:45:55 PM UTC 24 |
| Finished | Oct 02 06:46:16 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301406272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1301406272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.43006994 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 156909129 ps |
| CPU time | 5.75 seconds |
| Started | Oct 02 06:45:43 PM UTC 24 |
| Finished | Oct 02 06:45:50 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43006994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.43006994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2740712035 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 27284593466 ps |
| CPU time | 72.34 seconds |
| Started | Oct 02 06:45:44 PM UTC 24 |
| Finished | Oct 02 06:46:59 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740712035 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2740712035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.616775506 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 11255969739 ps |
| CPU time | 39.1 seconds |
| Started | Oct 02 06:45:46 PM UTC 24 |
| Finished | Oct 02 06:46:26 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616775506 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.616775506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1226875735 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 26279616 ps |
| CPU time | 3.29 seconds |
| Started | Oct 02 06:45:43 PM UTC 24 |
| Finished | Oct 02 06:45:47 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226875735 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1226875735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.3156109521 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1116023753 ps |
| CPU time | 55.35 seconds |
| Started | Oct 02 06:46:01 PM UTC 24 |
| Finished | Oct 02 06:46:58 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156109521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3156109521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3223096590 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 18087714247 ps |
| CPU time | 153.79 seconds |
| Started | Oct 02 06:46:03 PM UTC 24 |
| Finished | Oct 02 06:48:40 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223096590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3223096590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2827178361 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 180409293 ps |
| CPU time | 118.2 seconds |
| Started | Oct 02 06:46:03 PM UTC 24 |
| Finished | Oct 02 06:48:04 PM UTC 24 |
| Peak memory | 219888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827178361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2827178361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3367093093 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 857987236 ps |
| CPU time | 250.49 seconds |
| Started | Oct 02 06:46:05 PM UTC 24 |
| Finished | Oct 02 06:50:19 PM UTC 24 |
| Peak memory | 232524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367093093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3367093093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.1272913262 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1387802179 ps |
| CPU time | 20.54 seconds |
| Started | Oct 02 06:46:00 PM UTC 24 |
| Finished | Oct 02 06:46:21 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272913262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1272913262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.3365822540 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2038288319 ps |
| CPU time | 45.82 seconds |
| Started | Oct 02 06:46:18 PM UTC 24 |
| Finished | Oct 02 06:47:05 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365822540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3365822540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2195216300 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 245387194509 ps |
| CPU time | 517.05 seconds |
| Started | Oct 02 06:46:21 PM UTC 24 |
| Finished | Oct 02 06:55:05 PM UTC 24 |
| Peak memory | 219496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195216300 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2195216300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1479913385 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1968209145 ps |
| CPU time | 22.55 seconds |
| Started | Oct 02 06:46:27 PM UTC 24 |
| Finished | Oct 02 06:46:51 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479913385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1479913385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.211872847 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 304684962 ps |
| CPU time | 7.98 seconds |
| Started | Oct 02 06:46:24 PM UTC 24 |
| Finished | Oct 02 06:46:33 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211872847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.211872847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.2830317451 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 441524443 ps |
| CPU time | 24.39 seconds |
| Started | Oct 02 06:46:12 PM UTC 24 |
| Finished | Oct 02 06:46:38 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830317451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2830317451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.1829261906 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 26970018140 ps |
| CPU time | 150.56 seconds |
| Started | Oct 02 06:46:16 PM UTC 24 |
| Finished | Oct 02 06:48:49 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829261906 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1829261906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3368254551 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 156000124758 ps |
| CPU time | 479.94 seconds |
| Started | Oct 02 06:46:18 PM UTC 24 |
| Finished | Oct 02 06:54:24 PM UTC 24 |
| Peak memory | 217640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368254551 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3368254551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2393993847 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 162018171 ps |
| CPU time | 26.69 seconds |
| Started | Oct 02 06:46:12 PM UTC 24 |
| Finished | Oct 02 06:46:40 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393993847 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2393993847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3337517282 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2596396170 ps |
| CPU time | 39.73 seconds |
| Started | Oct 02 06:46:22 PM UTC 24 |
| Finished | Oct 02 06:47:04 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337517282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3337517282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.4105194660 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 192854036 ps |
| CPU time | 4.95 seconds |
| Started | Oct 02 06:46:05 PM UTC 24 |
| Finished | Oct 02 06:46:11 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105194660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4105194660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2274441259 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 24451141539 ps |
| CPU time | 52.31 seconds |
| Started | Oct 02 06:46:07 PM UTC 24 |
| Finished | Oct 02 06:47:01 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274441259 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2274441259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3408036852 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 7831911763 ps |
| CPU time | 37.75 seconds |
| Started | Oct 02 06:46:11 PM UTC 24 |
| Finished | Oct 02 06:46:50 PM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408036852 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3408036852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4257079337 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 43881021 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 06:46:06 PM UTC 24 |
| Finished | Oct 02 06:46:11 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257079337 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4257079337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2779458313 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3908678060 ps |
| CPU time | 79.86 seconds |
| Started | Oct 02 06:46:28 PM UTC 24 |
| Finished | Oct 02 06:47:50 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779458313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2779458313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3917978168 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 276827623 ps |
| CPU time | 5.8 seconds |
| Started | Oct 02 06:46:32 PM UTC 24 |
| Finished | Oct 02 06:46:39 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917978168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3917978168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.770047827 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 505841265 ps |
| CPU time | 98.35 seconds |
| Started | Oct 02 06:46:32 PM UTC 24 |
| Finished | Oct 02 06:48:12 PM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770047827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.770047827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.1164125347 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 16825468 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 06:46:26 PM UTC 24 |
| Finished | Oct 02 06:46:30 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164125347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1164125347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.382330356 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4790318683 ps |
| CPU time | 62.6 seconds |
| Started | Oct 02 06:46:39 PM UTC 24 |
| Finished | Oct 02 06:47:44 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382330356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.382330356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1904167952 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5475531612 ps |
| CPU time | 34.62 seconds |
| Started | Oct 02 06:46:39 PM UTC 24 |
| Finished | Oct 02 06:47:15 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904167952 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1904167952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1850797557 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 736370997 ps |
| CPU time | 27.48 seconds |
| Started | Oct 02 06:46:42 PM UTC 24 |
| Finished | Oct 02 06:47:11 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850797557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1850797557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.2855233036 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 927685916 ps |
| CPU time | 21.08 seconds |
| Started | Oct 02 06:46:41 PM UTC 24 |
| Finished | Oct 02 06:47:03 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855233036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2855233036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3166206896 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 142582943 ps |
| CPU time | 15.81 seconds |
| Started | Oct 02 06:46:37 PM UTC 24 |
| Finished | Oct 02 06:46:54 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166206896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3166206896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.1734787464 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 30431105452 ps |
| CPU time | 146.87 seconds |
| Started | Oct 02 06:46:39 PM UTC 24 |
| Finished | Oct 02 06:49:09 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734787464 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1734787464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2857007688 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 44631613544 ps |
| CPU time | 382.84 seconds |
| Started | Oct 02 06:46:39 PM UTC 24 |
| Finished | Oct 02 06:53:08 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857007688 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2857007688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.1259097085 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 116137138 ps |
| CPU time | 26.79 seconds |
| Started | Oct 02 06:46:39 PM UTC 24 |
| Finished | Oct 02 06:47:07 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259097085 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1259097085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.343555879 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1701752334 ps |
| CPU time | 43.51 seconds |
| Started | Oct 02 06:46:41 PM UTC 24 |
| Finished | Oct 02 06:47:26 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343555879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.343555879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.3629461863 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 65474624 ps |
| CPU time | 3.26 seconds |
| Started | Oct 02 06:46:33 PM UTC 24 |
| Finished | Oct 02 06:46:38 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629461863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3629461863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3046965694 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 35650694165 ps |
| CPU time | 64.08 seconds |
| Started | Oct 02 06:46:34 PM UTC 24 |
| Finished | Oct 02 06:47:39 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046965694 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3046965694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.453877847 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 8017545570 ps |
| CPU time | 26.53 seconds |
| Started | Oct 02 06:46:36 PM UTC 24 |
| Finished | Oct 02 06:47:04 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453877847 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.453877847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1617924627 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 27388376 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 06:46:34 PM UTC 24 |
| Finished | Oct 02 06:46:38 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617924627 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1617924627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.3478401062 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1013473424 ps |
| CPU time | 108.07 seconds |
| Started | Oct 02 06:46:44 PM UTC 24 |
| Finished | Oct 02 06:48:34 PM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478401062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3478401062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.696159601 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 15889005908 ps |
| CPU time | 202.73 seconds |
| Started | Oct 02 06:46:50 PM UTC 24 |
| Finished | Oct 02 06:50:17 PM UTC 24 |
| Peak memory | 220140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696159601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.696159601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1495333473 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1858615168 ps |
| CPU time | 413.2 seconds |
| Started | Oct 02 06:46:48 PM UTC 24 |
| Finished | Oct 02 06:53:47 PM UTC 24 |
| Peak memory | 222348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495333473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1495333473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3398701938 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 82399096 ps |
| CPU time | 13.37 seconds |
| Started | Oct 02 06:46:52 PM UTC 24 |
| Finished | Oct 02 06:47:07 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398701938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3398701938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3839971772 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 100920139 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 06:46:41 PM UTC 24 |
| Finished | Oct 02 06:46:47 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839971772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3839971772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.2905884034 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 264684246 ps |
| CPU time | 16.94 seconds |
| Started | Oct 02 06:47:03 PM UTC 24 |
| Finished | Oct 02 06:47:21 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905884034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2905884034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3775996448 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 64859785626 ps |
| CPU time | 673.08 seconds |
| Started | Oct 02 06:47:04 PM UTC 24 |
| Finished | Oct 02 06:58:26 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775996448 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3775996448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3170002341 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3293969626 ps |
| CPU time | 25.01 seconds |
| Started | Oct 02 06:47:07 PM UTC 24 |
| Finished | Oct 02 06:47:33 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170002341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3170002341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.3685659748 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 67678733 ps |
| CPU time | 9.64 seconds |
| Started | Oct 02 06:47:06 PM UTC 24 |
| Finished | Oct 02 06:47:16 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685659748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3685659748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1667940609 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 250464873 ps |
| CPU time | 10.12 seconds |
| Started | Oct 02 06:47:00 PM UTC 24 |
| Finished | Oct 02 06:47:11 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667940609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1667940609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3745689803 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 44068372053 ps |
| CPU time | 201.18 seconds |
| Started | Oct 02 06:47:02 PM UTC 24 |
| Finished | Oct 02 06:50:26 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745689803 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3745689803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3122226195 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 16009253137 ps |
| CPU time | 74.22 seconds |
| Started | Oct 02 06:47:02 PM UTC 24 |
| Finished | Oct 02 06:48:18 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122226195 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3122226195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.1208144265 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 885931471 ps |
| CPU time | 23.55 seconds |
| Started | Oct 02 06:47:00 PM UTC 24 |
| Finished | Oct 02 06:47:25 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208144265 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1208144265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.353595488 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 209938274 ps |
| CPU time | 22.28 seconds |
| Started | Oct 02 06:47:06 PM UTC 24 |
| Finished | Oct 02 06:47:29 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353595488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.353595488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.2278906478 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 299031100 ps |
| CPU time | 6.53 seconds |
| Started | Oct 02 06:46:52 PM UTC 24 |
| Finished | Oct 02 06:47:00 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278906478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2278906478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3138052113 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 6561146984 ps |
| CPU time | 39.68 seconds |
| Started | Oct 02 06:46:58 PM UTC 24 |
| Finished | Oct 02 06:47:40 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138052113 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3138052113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2401602014 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5901638994 ps |
| CPU time | 45.83 seconds |
| Started | Oct 02 06:47:00 PM UTC 24 |
| Finished | Oct 02 06:47:47 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401602014 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2401602014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3433636567 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 43642881 ps |
| CPU time | 3.08 seconds |
| Started | Oct 02 06:46:55 PM UTC 24 |
| Finished | Oct 02 06:46:59 PM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433636567 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3433636567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3152179049 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 325240077 ps |
| CPU time | 44.29 seconds |
| Started | Oct 02 06:47:09 PM UTC 24 |
| Finished | Oct 02 06:47:54 PM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152179049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3152179049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1531144508 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 936002595 ps |
| CPU time | 80.16 seconds |
| Started | Oct 02 06:47:12 PM UTC 24 |
| Finished | Oct 02 06:48:34 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531144508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1531144508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3435972729 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 693951831 ps |
| CPU time | 263.88 seconds |
| Started | Oct 02 06:47:09 PM UTC 24 |
| Finished | Oct 02 06:51:36 PM UTC 24 |
| Peak memory | 219888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435972729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3435972729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3261022514 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 7482087805 ps |
| CPU time | 248.54 seconds |
| Started | Oct 02 06:47:12 PM UTC 24 |
| Finished | Oct 02 06:51:25 PM UTC 24 |
| Peak memory | 232784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261022514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3261022514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.2119452294 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 366790544 ps |
| CPU time | 18.6 seconds |
| Started | Oct 02 06:47:07 PM UTC 24 |
| Finished | Oct 02 06:47:27 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119452294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2119452294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1383300636 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 411168061 ps |
| CPU time | 27.36 seconds |
| Started | Oct 02 06:47:22 PM UTC 24 |
| Finished | Oct 02 06:47:51 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383300636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1383300636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3237044454 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 135020038341 ps |
| CPU time | 1055.94 seconds |
| Started | Oct 02 06:47:23 PM UTC 24 |
| Finished | Oct 02 07:05:13 PM UTC 24 |
| Peak memory | 219496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237044454 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3237044454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1453034232 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 369240972 ps |
| CPU time | 7.98 seconds |
| Started | Oct 02 06:47:29 PM UTC 24 |
| Finished | Oct 02 06:47:38 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453034232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1453034232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.1728075818 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2093186413 ps |
| CPU time | 22.69 seconds |
| Started | Oct 02 06:47:27 PM UTC 24 |
| Finished | Oct 02 06:47:51 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728075818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1728075818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1447159040 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 68012785 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 06:47:19 PM UTC 24 |
| Finished | Oct 02 06:47:23 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447159040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1447159040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1854535651 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 46884257858 ps |
| CPU time | 281.37 seconds |
| Started | Oct 02 06:47:22 PM UTC 24 |
| Finished | Oct 02 06:52:08 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854535651 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1854535651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1749611984 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 53206501141 ps |
| CPU time | 259.17 seconds |
| Started | Oct 02 06:47:22 PM UTC 24 |
| Finished | Oct 02 06:51:45 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749611984 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1749611984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.3678464526 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 97030738 ps |
| CPU time | 10.63 seconds |
| Started | Oct 02 06:47:21 PM UTC 24 |
| Finished | Oct 02 06:47:32 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678464526 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3678464526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1975345140 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 700918990 ps |
| CPU time | 23.75 seconds |
| Started | Oct 02 06:47:26 PM UTC 24 |
| Finished | Oct 02 06:47:51 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975345140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1975345140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2442371797 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 401641994 ps |
| CPU time | 6.27 seconds |
| Started | Oct 02 06:47:13 PM UTC 24 |
| Finished | Oct 02 06:47:21 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442371797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2442371797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.384796812 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4786321320 ps |
| CPU time | 57.4 seconds |
| Started | Oct 02 06:47:16 PM UTC 24 |
| Finished | Oct 02 06:48:15 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384796812 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.384796812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3789412898 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 7127009574 ps |
| CPU time | 33.01 seconds |
| Started | Oct 02 06:47:18 PM UTC 24 |
| Finished | Oct 02 06:47:52 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789412898 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3789412898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1413811820 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 29596768 ps |
| CPU time | 3.84 seconds |
| Started | Oct 02 06:47:16 PM UTC 24 |
| Finished | Oct 02 06:47:21 PM UTC 24 |
| Peak memory | 215752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413811820 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1413811820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.1525690507 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3006791016 ps |
| CPU time | 92.38 seconds |
| Started | Oct 02 06:47:30 PM UTC 24 |
| Finished | Oct 02 06:49:04 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525690507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1525690507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.877000567 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 601056406 ps |
| CPU time | 11.78 seconds |
| Started | Oct 02 06:47:34 PM UTC 24 |
| Finished | Oct 02 06:47:47 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877000567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.877000567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1610427736 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2353183090 ps |
| CPU time | 284.37 seconds |
| Started | Oct 02 06:47:34 PM UTC 24 |
| Finished | Oct 02 06:52:23 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610427736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1610427736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2598408620 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1505921196 ps |
| CPU time | 80.78 seconds |
| Started | Oct 02 06:47:34 PM UTC 24 |
| Finished | Oct 02 06:48:57 PM UTC 24 |
| Peak memory | 219820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598408620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2598408620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.981676358 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 152035766 ps |
| CPU time | 21.43 seconds |
| Started | Oct 02 06:47:29 PM UTC 24 |
| Finished | Oct 02 06:47:51 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981676358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.981676358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2337471475 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1367268339 ps |
| CPU time | 17.78 seconds |
| Started | Oct 02 06:47:50 PM UTC 24 |
| Finished | Oct 02 06:48:09 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337471475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2337471475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4240327778 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 71947941580 ps |
| CPU time | 533.91 seconds |
| Started | Oct 02 06:47:50 PM UTC 24 |
| Finished | Oct 02 06:56:50 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240327778 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.4240327778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1198978705 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 126979815 ps |
| CPU time | 7.74 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:48:02 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198978705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1198978705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1702903346 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 330885349 ps |
| CPU time | 26.75 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:48:21 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702903346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1702903346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.3514724880 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 64557202 ps |
| CPU time | 3.57 seconds |
| Started | Oct 02 06:47:43 PM UTC 24 |
| Finished | Oct 02 06:47:48 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514724880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3514724880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2277500310 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 34908322169 ps |
| CPU time | 166.37 seconds |
| Started | Oct 02 06:47:45 PM UTC 24 |
| Finished | Oct 02 06:50:34 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277500310 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2277500310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2774053125 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 33321057470 ps |
| CPU time | 265.79 seconds |
| Started | Oct 02 06:47:50 PM UTC 24 |
| Finished | Oct 02 06:52:19 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774053125 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2774053125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.1087054573 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 117638244 ps |
| CPU time | 12.67 seconds |
| Started | Oct 02 06:47:45 PM UTC 24 |
| Finished | Oct 02 06:47:58 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087054573 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1087054573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.1685723188 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1390604482 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:48:04 PM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685723188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1685723188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2945209093 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 183483820 ps |
| CPU time | 4.82 seconds |
| Started | Oct 02 06:47:36 PM UTC 24 |
| Finished | Oct 02 06:47:41 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945209093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2945209093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3544280389 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5774153010 ps |
| CPU time | 44.66 seconds |
| Started | Oct 02 06:47:41 PM UTC 24 |
| Finished | Oct 02 06:48:27 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544280389 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3544280389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1683943217 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6588708468 ps |
| CPU time | 51.15 seconds |
| Started | Oct 02 06:47:41 PM UTC 24 |
| Finished | Oct 02 06:48:33 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683943217 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1683943217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2145082790 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 30408408 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 06:47:39 PM UTC 24 |
| Finished | Oct 02 06:47:43 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145082790 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2145082790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.4145278474 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1881595236 ps |
| CPU time | 124.47 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:50:00 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145278474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4145278474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2795659209 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2819735099 ps |
| CPU time | 138.52 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:50:14 PM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795659209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2795659209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4226259854 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 862854626 ps |
| CPU time | 514.78 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:56:35 PM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226259854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.4226259854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3344460374 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 803789932 ps |
| CPU time | 137.52 seconds |
| Started | Oct 02 06:47:55 PM UTC 24 |
| Finished | Oct 02 06:50:15 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344460374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3344460374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.3315059882 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 19056722 ps |
| CPU time | 2.3 seconds |
| Started | Oct 02 06:47:53 PM UTC 24 |
| Finished | Oct 02 06:47:56 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315059882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3315059882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.671612455 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 449671680 ps |
| CPU time | 22.88 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:33:41 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671612455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.671612455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3704265936 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 53355632602 ps |
| CPU time | 227.13 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:37:07 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704265936 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3704265936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1487344370 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 125317714 ps |
| CPU time | 18.23 seconds |
| Started | Oct 02 06:33:20 PM UTC 24 |
| Finished | Oct 02 06:33:39 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487344370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1487344370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2504672828 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5700111718 ps |
| CPU time | 38.55 seconds |
| Started | Oct 02 06:33:18 PM UTC 24 |
| Finished | Oct 02 06:33:58 PM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504672828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2504672828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.2191412695 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 196028239 ps |
| CPU time | 16.78 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:33:35 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191412695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2191412695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.806072762 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 31427047273 ps |
| CPU time | 108.26 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:35:07 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806072762 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.806072762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2626183286 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 19784755883 ps |
| CPU time | 168.73 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:36:09 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626183286 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2626183286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2265196088 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 402561959 ps |
| CPU time | 29.44 seconds |
| Started | Oct 02 06:33:17 PM UTC 24 |
| Finished | Oct 02 06:33:48 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265196088 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2265196088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1061009405 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 310683695 ps |
| CPU time | 26.54 seconds |
| Started | Oct 02 06:33:18 PM UTC 24 |
| Finished | Oct 02 06:33:46 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061009405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1061009405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3949276074 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 32336655 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 06:33:13 PM UTC 24 |
| Finished | Oct 02 06:33:17 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949276074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3949276074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2483910053 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 11325305056 ps |
| CPU time | 42.88 seconds |
| Started | Oct 02 06:33:14 PM UTC 24 |
| Finished | Oct 02 06:33:59 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483910053 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2483910053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2698688000 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 38644194 ps |
| CPU time | 3.66 seconds |
| Started | Oct 02 06:33:14 PM UTC 24 |
| Finished | Oct 02 06:33:19 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698688000 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2698688000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2511811287 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2803443997 ps |
| CPU time | 104.14 seconds |
| Started | Oct 02 06:33:20 PM UTC 24 |
| Finished | Oct 02 06:35:06 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511811287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2511811287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2407918204 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3346224346 ps |
| CPU time | 164.45 seconds |
| Started | Oct 02 06:33:21 PM UTC 24 |
| Finished | Oct 02 06:36:08 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407918204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2407918204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2780574712 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 19403998344 ps |
| CPU time | 370.33 seconds |
| Started | Oct 02 06:33:20 PM UTC 24 |
| Finished | Oct 02 06:39:36 PM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780574712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2780574712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2208381643 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 9402615579 ps |
| CPU time | 285.97 seconds |
| Started | Oct 02 06:33:21 PM UTC 24 |
| Finished | Oct 02 06:38:11 PM UTC 24 |
| Peak memory | 232648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208381643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2208381643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.336048854 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 423165911 ps |
| CPU time | 18.48 seconds |
| Started | Oct 02 06:33:18 PM UTC 24 |
| Finished | Oct 02 06:33:38 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336048854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.336048854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1148221250 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 167840973 ps |
| CPU time | 13.45 seconds |
| Started | Oct 02 06:48:03 PM UTC 24 |
| Finished | Oct 02 06:48:18 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148221250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1148221250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3669019291 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 48636113817 ps |
| CPU time | 269.93 seconds |
| Started | Oct 02 06:48:03 PM UTC 24 |
| Finished | Oct 02 06:52:37 PM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669019291 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3669019291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4279670304 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 124902256 ps |
| CPU time | 6.24 seconds |
| Started | Oct 02 06:48:10 PM UTC 24 |
| Finished | Oct 02 06:48:17 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279670304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4279670304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2992497922 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 862114694 ps |
| CPU time | 24.92 seconds |
| Started | Oct 02 06:48:05 PM UTC 24 |
| Finished | Oct 02 06:48:31 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992497922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2992497922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.1696428806 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1799659155 ps |
| CPU time | 17.94 seconds |
| Started | Oct 02 06:47:58 PM UTC 24 |
| Finished | Oct 02 06:48:17 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696428806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1696428806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4138417171 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 56323567025 ps |
| CPU time | 408.32 seconds |
| Started | Oct 02 06:47:59 PM UTC 24 |
| Finished | Oct 02 06:54:54 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138417171 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4138417171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1860419061 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 27909941952 ps |
| CPU time | 214.65 seconds |
| Started | Oct 02 06:48:01 PM UTC 24 |
| Finished | Oct 02 06:51:40 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860419061 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1860419061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.798565583 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 463316744 ps |
| CPU time | 24.91 seconds |
| Started | Oct 02 06:47:59 PM UTC 24 |
| Finished | Oct 02 06:48:26 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798565583 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.798565583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2088912335 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 882038089 ps |
| CPU time | 37.09 seconds |
| Started | Oct 02 06:48:03 PM UTC 24 |
| Finished | Oct 02 06:48:42 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088912335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2088912335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3211626874 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 35486651 ps |
| CPU time | 2.53 seconds |
| Started | Oct 02 06:47:55 PM UTC 24 |
| Finished | Oct 02 06:47:58 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211626874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3211626874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.558474580 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 5301376210 ps |
| CPU time | 40.57 seconds |
| Started | Oct 02 06:47:58 PM UTC 24 |
| Finished | Oct 02 06:48:40 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558474580 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.558474580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4120110266 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 8212802548 ps |
| CPU time | 38.66 seconds |
| Started | Oct 02 06:47:58 PM UTC 24 |
| Finished | Oct 02 06:48:38 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120110266 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4120110266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.644382563 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 39203745 ps |
| CPU time | 3.22 seconds |
| Started | Oct 02 06:47:58 PM UTC 24 |
| Finished | Oct 02 06:48:02 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644382563 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.644382563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.464411242 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 6443896091 ps |
| CPU time | 151.56 seconds |
| Started | Oct 02 06:48:10 PM UTC 24 |
| Finished | Oct 02 06:50:44 PM UTC 24 |
| Peak memory | 219352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464411242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.464411242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1639989410 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1878991430 ps |
| CPU time | 164.99 seconds |
| Started | Oct 02 06:48:16 PM UTC 24 |
| Finished | Oct 02 06:51:04 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639989410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1639989410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2916816887 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 605799140 ps |
| CPU time | 220.47 seconds |
| Started | Oct 02 06:48:14 PM UTC 24 |
| Finished | Oct 02 06:51:58 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916816887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2916816887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3576747961 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 101754123 ps |
| CPU time | 37.8 seconds |
| Started | Oct 02 06:48:18 PM UTC 24 |
| Finished | Oct 02 06:48:57 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576747961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3576747961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1108966710 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 300553896 ps |
| CPU time | 19.93 seconds |
| Started | Oct 02 06:48:05 PM UTC 24 |
| Finished | Oct 02 06:48:26 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108966710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1108966710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.513243618 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2073597393 ps |
| CPU time | 61.46 seconds |
| Started | Oct 02 06:48:28 PM UTC 24 |
| Finished | Oct 02 06:49:31 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513243618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.513243618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3223886709 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 79764107692 ps |
| CPU time | 729.69 seconds |
| Started | Oct 02 06:48:30 PM UTC 24 |
| Finished | Oct 02 07:00:48 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223886709 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3223886709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3390425975 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 383139285 ps |
| CPU time | 17.05 seconds |
| Started | Oct 02 06:48:36 PM UTC 24 |
| Finished | Oct 02 06:48:55 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390425975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3390425975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.3377777526 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1050680551 ps |
| CPU time | 27.3 seconds |
| Started | Oct 02 06:48:33 PM UTC 24 |
| Finished | Oct 02 06:49:02 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377777526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3377777526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.4227390505 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 64848615 ps |
| CPU time | 11.46 seconds |
| Started | Oct 02 06:48:26 PM UTC 24 |
| Finished | Oct 02 06:48:39 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227390505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.4227390505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.604032157 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 85740389631 ps |
| CPU time | 230.4 seconds |
| Started | Oct 02 06:48:26 PM UTC 24 |
| Finished | Oct 02 06:52:20 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604032157 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.604032157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1537765034 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 73996801013 ps |
| CPU time | 329.37 seconds |
| Started | Oct 02 06:48:28 PM UTC 24 |
| Finished | Oct 02 06:54:02 PM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537765034 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1537765034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.715840882 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 22202096 ps |
| CPU time | 3.5 seconds |
| Started | Oct 02 06:48:26 PM UTC 24 |
| Finished | Oct 02 06:48:31 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715840882 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.715840882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.848280918 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 133077110 ps |
| CPU time | 12.9 seconds |
| Started | Oct 02 06:48:32 PM UTC 24 |
| Finished | Oct 02 06:48:46 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848280918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.848280918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.535203910 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 292033313 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 06:48:19 PM UTC 24 |
| Finished | Oct 02 06:48:24 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535203910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.535203910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3186071805 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5744944139 ps |
| CPU time | 41.55 seconds |
| Started | Oct 02 06:48:19 PM UTC 24 |
| Finished | Oct 02 06:49:03 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186071805 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3186071805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2201760991 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3111456529 ps |
| CPU time | 44.51 seconds |
| Started | Oct 02 06:48:22 PM UTC 24 |
| Finished | Oct 02 06:49:08 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201760991 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2201760991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2863170650 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 27643739 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 06:48:19 PM UTC 24 |
| Finished | Oct 02 06:48:24 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863170650 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2863170650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.786292108 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1237807079 ps |
| CPU time | 157.48 seconds |
| Started | Oct 02 06:48:36 PM UTC 24 |
| Finished | Oct 02 06:51:17 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786292108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.786292108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4191951375 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2024941378 ps |
| CPU time | 67.07 seconds |
| Started | Oct 02 06:48:39 PM UTC 24 |
| Finished | Oct 02 06:49:48 PM UTC 24 |
| Peak memory | 217768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191951375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4191951375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4218187938 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4004041539 ps |
| CPU time | 389.59 seconds |
| Started | Oct 02 06:48:36 PM UTC 24 |
| Finished | Oct 02 06:55:12 PM UTC 24 |
| Peak memory | 219952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218187938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.4218187938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1611858240 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 16831944853 ps |
| CPU time | 206.01 seconds |
| Started | Oct 02 06:48:41 PM UTC 24 |
| Finished | Oct 02 06:52:10 PM UTC 24 |
| Peak memory | 222256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611858240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1611858240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2081976159 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 261344492 ps |
| CPU time | 10.89 seconds |
| Started | Oct 02 06:48:36 PM UTC 24 |
| Finished | Oct 02 06:48:49 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081976159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2081976159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3598876712 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 2218754288 ps |
| CPU time | 41.6 seconds |
| Started | Oct 02 06:48:56 PM UTC 24 |
| Finished | Oct 02 06:49:39 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598876712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3598876712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1778473099 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 75918924677 ps |
| CPU time | 627.17 seconds |
| Started | Oct 02 06:48:59 PM UTC 24 |
| Finished | Oct 02 06:59:34 PM UTC 24 |
| Peak memory | 219496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778473099 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1778473099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2146376717 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4793857019 ps |
| CPU time | 32.84 seconds |
| Started | Oct 02 06:49:06 PM UTC 24 |
| Finished | Oct 02 06:49:40 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146376717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2146376717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1733330481 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 184302062 ps |
| CPU time | 10.67 seconds |
| Started | Oct 02 06:49:04 PM UTC 24 |
| Finished | Oct 02 06:49:16 PM UTC 24 |
| Peak memory | 216028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733330481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1733330481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2816570657 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1468795982 ps |
| CPU time | 42.44 seconds |
| Started | Oct 02 06:48:49 PM UTC 24 |
| Finished | Oct 02 06:49:33 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816570657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2816570657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.813155434 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 193988986744 ps |
| CPU time | 388.12 seconds |
| Started | Oct 02 06:48:50 PM UTC 24 |
| Finished | Oct 02 06:55:24 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813155434 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.813155434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.878821723 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4194361845 ps |
| CPU time | 26.96 seconds |
| Started | Oct 02 06:48:50 PM UTC 24 |
| Finished | Oct 02 06:49:19 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878821723 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.878821723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2265862313 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1373690569 ps |
| CPU time | 37.27 seconds |
| Started | Oct 02 06:48:49 PM UTC 24 |
| Finished | Oct 02 06:49:28 PM UTC 24 |
| Peak memory | 217752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265862313 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2265862313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.203019175 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 216558627 ps |
| CPU time | 23.23 seconds |
| Started | Oct 02 06:48:59 PM UTC 24 |
| Finished | Oct 02 06:49:24 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203019175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.203019175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3449985600 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 173717130 ps |
| CPU time | 5.43 seconds |
| Started | Oct 02 06:48:41 PM UTC 24 |
| Finished | Oct 02 06:48:47 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449985600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3449985600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1897886997 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5426757554 ps |
| CPU time | 36.7 seconds |
| Started | Oct 02 06:48:44 PM UTC 24 |
| Finished | Oct 02 06:49:22 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897886997 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1897886997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2055239533 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 13262859869 ps |
| CPU time | 57.07 seconds |
| Started | Oct 02 06:48:49 PM UTC 24 |
| Finished | Oct 02 06:49:48 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055239533 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2055239533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.155065467 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 72546349 ps |
| CPU time | 3.37 seconds |
| Started | Oct 02 06:48:42 PM UTC 24 |
| Finished | Oct 02 06:48:47 PM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155065467 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.155065467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.820333863 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1992325978 ps |
| CPU time | 81.06 seconds |
| Started | Oct 02 06:49:10 PM UTC 24 |
| Finished | Oct 02 06:50:33 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820333863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.820333863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2846635391 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 9350885503 ps |
| CPU time | 103.93 seconds |
| Started | Oct 02 06:49:14 PM UTC 24 |
| Finished | Oct 02 06:51:00 PM UTC 24 |
| Peak memory | 220140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846635391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2846635391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.612516445 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 521355231 ps |
| CPU time | 133.1 seconds |
| Started | Oct 02 06:49:10 PM UTC 24 |
| Finished | Oct 02 06:51:26 PM UTC 24 |
| Peak memory | 219812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612516445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.612516445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.841972937 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2712919938 ps |
| CPU time | 293.82 seconds |
| Started | Oct 02 06:49:17 PM UTC 24 |
| Finished | Oct 02 06:54:15 PM UTC 24 |
| Peak memory | 232588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841972937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.841972937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.995037594 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 151079548 ps |
| CPU time | 18.17 seconds |
| Started | Oct 02 06:49:04 PM UTC 24 |
| Finished | Oct 02 06:49:24 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995037594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.995037594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.881756765 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1480154878 ps |
| CPU time | 44.82 seconds |
| Started | Oct 02 06:49:33 PM UTC 24 |
| Finished | Oct 02 06:50:19 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881756765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.881756765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1337390263 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 54863597314 ps |
| CPU time | 663.64 seconds |
| Started | Oct 02 06:49:34 PM UTC 24 |
| Finished | Oct 02 07:00:46 PM UTC 24 |
| Peak memory | 219820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337390263 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1337390263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1016110603 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 160903628 ps |
| CPU time | 22.78 seconds |
| Started | Oct 02 06:49:46 PM UTC 24 |
| Finished | Oct 02 06:50:10 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016110603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1016110603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2889622395 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1375405804 ps |
| CPU time | 27.71 seconds |
| Started | Oct 02 06:49:40 PM UTC 24 |
| Finished | Oct 02 06:50:09 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889622395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2889622395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.579398318 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 153885541 ps |
| CPU time | 18.33 seconds |
| Started | Oct 02 06:49:26 PM UTC 24 |
| Finished | Oct 02 06:49:45 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579398318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.579398318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.57027697 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 23457216836 ps |
| CPU time | 48.29 seconds |
| Started | Oct 02 06:49:29 PM UTC 24 |
| Finished | Oct 02 06:50:19 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57027697 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.57027697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2668893961 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1618276555 ps |
| CPU time | 26.41 seconds |
| Started | Oct 02 06:49:29 PM UTC 24 |
| Finished | Oct 02 06:49:57 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668893961 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2668893961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.92919196 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 111138727 ps |
| CPU time | 5.1 seconds |
| Started | Oct 02 06:49:27 PM UTC 24 |
| Finished | Oct 02 06:49:34 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92919196 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.92919196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.3419535959 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3417429948 ps |
| CPU time | 43.26 seconds |
| Started | Oct 02 06:49:34 PM UTC 24 |
| Finished | Oct 02 06:50:19 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419535959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3419535959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1222906364 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 186571854 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 06:49:20 PM UTC 24 |
| Finished | Oct 02 06:49:26 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222906364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1222906364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.4187787560 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 8136825179 ps |
| CPU time | 72.44 seconds |
| Started | Oct 02 06:49:24 PM UTC 24 |
| Finished | Oct 02 06:50:38 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187787560 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4187787560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3653767224 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 14579274826 ps |
| CPU time | 51.55 seconds |
| Started | Oct 02 06:49:26 PM UTC 24 |
| Finished | Oct 02 06:50:19 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653767224 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3653767224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3125440615 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 28253542 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 06:49:24 PM UTC 24 |
| Finished | Oct 02 06:49:28 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125440615 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3125440615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2073315576 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2073903213 ps |
| CPU time | 174.13 seconds |
| Started | Oct 02 06:49:47 PM UTC 24 |
| Finished | Oct 02 06:52:44 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073315576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2073315576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1323915521 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5439351550 ps |
| CPU time | 182.06 seconds |
| Started | Oct 02 06:49:50 PM UTC 24 |
| Finished | Oct 02 06:52:55 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323915521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1323915521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3541408667 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 3404337097 ps |
| CPU time | 515.05 seconds |
| Started | Oct 02 06:49:48 PM UTC 24 |
| Finished | Oct 02 06:58:31 PM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541408667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3541408667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2898377171 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 441706730 ps |
| CPU time | 14.46 seconds |
| Started | Oct 02 06:49:41 PM UTC 24 |
| Finished | Oct 02 06:49:57 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898377171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2898377171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2124988826 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 227607863 ps |
| CPU time | 9.93 seconds |
| Started | Oct 02 06:50:17 PM UTC 24 |
| Finished | Oct 02 06:50:28 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124988826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2124988826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.550601819 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 59679327754 ps |
| CPU time | 680.19 seconds |
| Started | Oct 02 06:50:18 PM UTC 24 |
| Finished | Oct 02 07:01:47 PM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550601819 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.550601819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.474110481 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 132979391 ps |
| CPU time | 14.45 seconds |
| Started | Oct 02 06:50:23 PM UTC 24 |
| Finished | Oct 02 06:50:39 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474110481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.474110481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1588027674 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 121433317 ps |
| CPU time | 2.95 seconds |
| Started | Oct 02 06:50:23 PM UTC 24 |
| Finished | Oct 02 06:50:27 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588027674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1588027674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.904375167 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1429510153 ps |
| CPU time | 34.05 seconds |
| Started | Oct 02 06:50:06 PM UTC 24 |
| Finished | Oct 02 06:50:42 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904375167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.904375167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1616386051 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8413554712 ps |
| CPU time | 52.73 seconds |
| Started | Oct 02 06:50:11 PM UTC 24 |
| Finished | Oct 02 06:51:05 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616386051 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1616386051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1398100644 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 21216398457 ps |
| CPU time | 125.8 seconds |
| Started | Oct 02 06:50:17 PM UTC 24 |
| Finished | Oct 02 06:52:25 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398100644 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1398100644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3912798301 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 339953848 ps |
| CPU time | 14.65 seconds |
| Started | Oct 02 06:50:11 PM UTC 24 |
| Finished | Oct 02 06:50:27 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912798301 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3912798301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.339755376 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1764900614 ps |
| CPU time | 43.34 seconds |
| Started | Oct 02 06:50:23 PM UTC 24 |
| Finished | Oct 02 06:51:08 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339755376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.339755376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.3265729770 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 198771804 ps |
| CPU time | 5.34 seconds |
| Started | Oct 02 06:49:59 PM UTC 24 |
| Finished | Oct 02 06:50:05 PM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265729770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3265729770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1156309630 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6526216149 ps |
| CPU time | 33.44 seconds |
| Started | Oct 02 06:50:01 PM UTC 24 |
| Finished | Oct 02 06:50:36 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156309630 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1156309630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.265608640 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 15072085458 ps |
| CPU time | 39.81 seconds |
| Started | Oct 02 06:50:04 PM UTC 24 |
| Finished | Oct 02 06:50:45 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265608640 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.265608640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2664444713 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 97671270 ps |
| CPU time | 2.78 seconds |
| Started | Oct 02 06:49:59 PM UTC 24 |
| Finished | Oct 02 06:50:03 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664444713 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2664444713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2476075277 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1499633951 ps |
| CPU time | 94.92 seconds |
| Started | Oct 02 06:50:23 PM UTC 24 |
| Finished | Oct 02 06:52:00 PM UTC 24 |
| Peak memory | 219872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476075277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2476075277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1474919351 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 750140532 ps |
| CPU time | 92.38 seconds |
| Started | Oct 02 06:50:26 PM UTC 24 |
| Finished | Oct 02 06:52:01 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474919351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1474919351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3724801804 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 72491756 ps |
| CPU time | 59.74 seconds |
| Started | Oct 02 06:50:25 PM UTC 24 |
| Finished | Oct 02 06:51:26 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724801804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3724801804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.869310187 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1067148841 ps |
| CPU time | 245.3 seconds |
| Started | Oct 02 06:50:28 PM UTC 24 |
| Finished | Oct 02 06:54:37 PM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869310187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.869310187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2112564773 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 513700698 ps |
| CPU time | 19.26 seconds |
| Started | Oct 02 06:50:23 PM UTC 24 |
| Finished | Oct 02 06:50:43 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112564773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2112564773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2286764985 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 180600544 ps |
| CPU time | 21.67 seconds |
| Started | Oct 02 06:50:40 PM UTC 24 |
| Finished | Oct 02 06:51:03 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286764985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2286764985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2171412764 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 140258065816 ps |
| CPU time | 569.76 seconds |
| Started | Oct 02 06:50:40 PM UTC 24 |
| Finished | Oct 02 07:00:17 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171412764 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2171412764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2135076248 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 151648635 ps |
| CPU time | 10.87 seconds |
| Started | Oct 02 06:50:47 PM UTC 24 |
| Finished | Oct 02 06:50:59 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135076248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2135076248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3705304146 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 267454948 ps |
| CPU time | 27.94 seconds |
| Started | Oct 02 06:50:45 PM UTC 24 |
| Finished | Oct 02 06:51:14 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705304146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3705304146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.690364348 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 785235863 ps |
| CPU time | 44.26 seconds |
| Started | Oct 02 06:50:33 PM UTC 24 |
| Finished | Oct 02 06:51:20 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690364348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.690364348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.4091575279 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8755417481 ps |
| CPU time | 76.92 seconds |
| Started | Oct 02 06:50:36 PM UTC 24 |
| Finished | Oct 02 06:51:55 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091575279 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4091575279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3500077796 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 33019172007 ps |
| CPU time | 179.45 seconds |
| Started | Oct 02 06:50:38 PM UTC 24 |
| Finished | Oct 02 06:53:40 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500077796 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3500077796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.3983452217 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 153460382 ps |
| CPU time | 23.59 seconds |
| Started | Oct 02 06:50:36 PM UTC 24 |
| Finished | Oct 02 06:51:01 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983452217 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3983452217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1802329583 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1277724020 ps |
| CPU time | 25.06 seconds |
| Started | Oct 02 06:50:43 PM UTC 24 |
| Finished | Oct 02 06:51:10 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802329583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1802329583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2502699767 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 31433164 ps |
| CPU time | 3.15 seconds |
| Started | Oct 02 06:50:28 PM UTC 24 |
| Finished | Oct 02 06:50:32 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502699767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2502699767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.208698521 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 6189161364 ps |
| CPU time | 47.82 seconds |
| Started | Oct 02 06:50:29 PM UTC 24 |
| Finished | Oct 02 06:51:19 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208698521 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.208698521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1144461917 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 17459030971 ps |
| CPU time | 47.72 seconds |
| Started | Oct 02 06:50:33 PM UTC 24 |
| Finished | Oct 02 06:51:23 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144461917 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1144461917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2249060772 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 26590072 ps |
| CPU time | 3.13 seconds |
| Started | Oct 02 06:50:28 PM UTC 24 |
| Finished | Oct 02 06:50:32 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249060772 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2249060772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.153157574 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 16107932510 ps |
| CPU time | 173.66 seconds |
| Started | Oct 02 06:51:00 PM UTC 24 |
| Finished | Oct 02 06:53:57 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153157574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.153157574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1711141554 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1240360667 ps |
| CPU time | 95.8 seconds |
| Started | Oct 02 06:51:02 PM UTC 24 |
| Finished | Oct 02 06:52:40 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711141554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1711141554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4158222827 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2777909143 ps |
| CPU time | 205.28 seconds |
| Started | Oct 02 06:51:00 PM UTC 24 |
| Finished | Oct 02 06:54:29 PM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158222827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.4158222827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.4077737309 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 823169925 ps |
| CPU time | 235.49 seconds |
| Started | Oct 02 06:51:02 PM UTC 24 |
| Finished | Oct 02 06:55:02 PM UTC 24 |
| Peak memory | 222284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077737309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.4077737309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3336924394 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 121152548 ps |
| CPU time | 10.37 seconds |
| Started | Oct 02 06:50:46 PM UTC 24 |
| Finished | Oct 02 06:50:58 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336924394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3336924394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.2427579884 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 709965752 ps |
| CPU time | 33.08 seconds |
| Started | Oct 02 06:51:13 PM UTC 24 |
| Finished | Oct 02 06:51:48 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427579884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2427579884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1979844390 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 60434895359 ps |
| CPU time | 394.86 seconds |
| Started | Oct 02 06:51:16 PM UTC 24 |
| Finished | Oct 02 06:57:56 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979844390 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1979844390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.796917167 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 134574356 ps |
| CPU time | 15.88 seconds |
| Started | Oct 02 06:51:22 PM UTC 24 |
| Finished | Oct 02 06:51:39 PM UTC 24 |
| Peak memory | 215984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796917167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.796917167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4149140809 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 820951496 ps |
| CPU time | 19.03 seconds |
| Started | Oct 02 06:51:20 PM UTC 24 |
| Finished | Oct 02 06:51:40 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149140809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4149140809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.826986849 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 146998459 ps |
| CPU time | 12.23 seconds |
| Started | Oct 02 06:51:11 PM UTC 24 |
| Finished | Oct 02 06:51:25 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826986849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.826986849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1755203158 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 36280357820 ps |
| CPU time | 231.35 seconds |
| Started | Oct 02 06:51:12 PM UTC 24 |
| Finished | Oct 02 06:55:07 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755203158 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1755203158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.223140584 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 16964450622 ps |
| CPU time | 73.2 seconds |
| Started | Oct 02 06:51:12 PM UTC 24 |
| Finished | Oct 02 06:52:27 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223140584 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.223140584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2915624298 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 256865860 ps |
| CPU time | 22.74 seconds |
| Started | Oct 02 06:51:12 PM UTC 24 |
| Finished | Oct 02 06:51:36 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915624298 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2915624298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2428448831 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 253983709 ps |
| CPU time | 20.42 seconds |
| Started | Oct 02 06:51:18 PM UTC 24 |
| Finished | Oct 02 06:51:40 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428448831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2428448831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1920647156 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 28612332 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 06:51:04 PM UTC 24 |
| Finished | Oct 02 06:51:08 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920647156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1920647156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3010217846 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7145386622 ps |
| CPU time | 34.87 seconds |
| Started | Oct 02 06:51:07 PM UTC 24 |
| Finished | Oct 02 06:51:43 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010217846 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3010217846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3738158441 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 20100656798 ps |
| CPU time | 63.07 seconds |
| Started | Oct 02 06:51:08 PM UTC 24 |
| Finished | Oct 02 06:52:13 PM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738158441 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3738158441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1119478710 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 31374561 ps |
| CPU time | 2.53 seconds |
| Started | Oct 02 06:51:05 PM UTC 24 |
| Finished | Oct 02 06:51:09 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119478710 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1119478710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.340153163 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1399540775 ps |
| CPU time | 47.18 seconds |
| Started | Oct 02 06:51:24 PM UTC 24 |
| Finished | Oct 02 06:52:13 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340153163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.340153163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.980938542 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 6511074836 ps |
| CPU time | 89.29 seconds |
| Started | Oct 02 06:51:30 PM UTC 24 |
| Finished | Oct 02 06:53:01 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980938542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.980938542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1029247371 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2286914537 ps |
| CPU time | 204.74 seconds |
| Started | Oct 02 06:51:30 PM UTC 24 |
| Finished | Oct 02 06:54:59 PM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029247371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1029247371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.726852936 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1660648636 ps |
| CPU time | 161.38 seconds |
| Started | Oct 02 06:51:30 PM UTC 24 |
| Finished | Oct 02 06:54:14 PM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726852936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.726852936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2822466182 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 519365056 ps |
| CPU time | 27.38 seconds |
| Started | Oct 02 06:51:22 PM UTC 24 |
| Finished | Oct 02 06:51:50 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822466182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2822466182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3677925440 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2213292969 ps |
| CPU time | 73.49 seconds |
| Started | Oct 02 06:51:43 PM UTC 24 |
| Finished | Oct 02 06:52:58 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677925440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3677925440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1790328000 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 71728959700 ps |
| CPU time | 517.36 seconds |
| Started | Oct 02 06:51:43 PM UTC 24 |
| Finished | Oct 02 07:00:27 PM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790328000 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1790328000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.635960244 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1119438841 ps |
| CPU time | 15.8 seconds |
| Started | Oct 02 06:51:52 PM UTC 24 |
| Finished | Oct 02 06:52:09 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635960244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.635960244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.71755907 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2827532892 ps |
| CPU time | 29.65 seconds |
| Started | Oct 02 06:51:46 PM UTC 24 |
| Finished | Oct 02 06:52:17 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71755907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.71755907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.4213783155 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 236869371 ps |
| CPU time | 35.69 seconds |
| Started | Oct 02 06:51:39 PM UTC 24 |
| Finished | Oct 02 06:52:16 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213783155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.4213783155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1509527390 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 80323258244 ps |
| CPU time | 283.77 seconds |
| Started | Oct 02 06:51:40 PM UTC 24 |
| Finished | Oct 02 06:56:29 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509527390 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1509527390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4011256947 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 34850199718 ps |
| CPU time | 265.56 seconds |
| Started | Oct 02 06:51:43 PM UTC 24 |
| Finished | Oct 02 06:56:12 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011256947 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4011256947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.4024371401 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 226082269 ps |
| CPU time | 28.04 seconds |
| Started | Oct 02 06:51:39 PM UTC 24 |
| Finished | Oct 02 06:52:08 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024371401 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.4024371401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3141353145 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 603139872 ps |
| CPU time | 20.15 seconds |
| Started | Oct 02 06:51:45 PM UTC 24 |
| Finished | Oct 02 06:52:06 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141353145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3141353145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.2541057737 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 49148265 ps |
| CPU time | 3.59 seconds |
| Started | Oct 02 06:51:30 PM UTC 24 |
| Finished | Oct 02 06:51:35 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541057737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2541057737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2074503079 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 14159108967 ps |
| CPU time | 50.94 seconds |
| Started | Oct 02 06:51:36 PM UTC 24 |
| Finished | Oct 02 06:52:29 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074503079 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2074503079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.4108643560 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3472563449 ps |
| CPU time | 30.36 seconds |
| Started | Oct 02 06:51:36 PM UTC 24 |
| Finished | Oct 02 06:52:08 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108643560 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.4108643560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1788455230 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 113910443 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 06:51:30 PM UTC 24 |
| Finished | Oct 02 06:51:35 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788455230 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1788455230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.544051160 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 9514965702 ps |
| CPU time | 348.99 seconds |
| Started | Oct 02 06:51:57 PM UTC 24 |
| Finished | Oct 02 06:57:51 PM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544051160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.544051160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2984091639 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 4778596008 ps |
| CPU time | 54.33 seconds |
| Started | Oct 02 06:52:00 PM UTC 24 |
| Finished | Oct 02 06:52:57 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984091639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2984091639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2835660313 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2524113144 ps |
| CPU time | 309.59 seconds |
| Started | Oct 02 06:51:58 PM UTC 24 |
| Finished | Oct 02 06:57:13 PM UTC 24 |
| Peak memory | 219952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835660313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2835660313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.302218723 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 882871424 ps |
| CPU time | 163.42 seconds |
| Started | Oct 02 06:52:03 PM UTC 24 |
| Finished | Oct 02 06:54:49 PM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302218723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.302218723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.3856555551 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 124802830 ps |
| CPU time | 5.69 seconds |
| Started | Oct 02 06:51:49 PM UTC 24 |
| Finished | Oct 02 06:51:57 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856555551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3856555551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.700486406 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2922719817 ps |
| CPU time | 51.6 seconds |
| Started | Oct 02 06:52:14 PM UTC 24 |
| Finished | Oct 02 06:53:07 PM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700486406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.700486406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1023935752 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 75800226882 ps |
| CPU time | 592.04 seconds |
| Started | Oct 02 06:52:16 PM UTC 24 |
| Finished | Oct 02 07:02:15 PM UTC 24 |
| Peak memory | 219756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023935752 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1023935752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3343865630 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 170864851 ps |
| CPU time | 15.85 seconds |
| Started | Oct 02 06:52:21 PM UTC 24 |
| Finished | Oct 02 06:52:39 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343865630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3343865630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3487446885 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 164345869 ps |
| CPU time | 26.5 seconds |
| Started | Oct 02 06:52:17 PM UTC 24 |
| Finished | Oct 02 06:52:45 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487446885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3487446885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2043101514 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 164433618 ps |
| CPU time | 23.73 seconds |
| Started | Oct 02 06:52:11 PM UTC 24 |
| Finished | Oct 02 06:52:36 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043101514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2043101514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1940700604 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 36881843042 ps |
| CPU time | 241.58 seconds |
| Started | Oct 02 06:52:11 PM UTC 24 |
| Finished | Oct 02 06:56:17 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940700604 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1940700604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2439766717 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 27919440431 ps |
| CPU time | 223.74 seconds |
| Started | Oct 02 06:52:14 PM UTC 24 |
| Finished | Oct 02 06:56:01 PM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439766717 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2439766717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.697719231 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 207380381 ps |
| CPU time | 24.14 seconds |
| Started | Oct 02 06:52:11 PM UTC 24 |
| Finished | Oct 02 06:52:37 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697719231 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.697719231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2446009925 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 264319152 ps |
| CPU time | 8.32 seconds |
| Started | Oct 02 06:52:16 PM UTC 24 |
| Finished | Oct 02 06:52:25 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446009925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2446009925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1656499351 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 21492354 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 06:52:03 PM UTC 24 |
| Finished | Oct 02 06:52:08 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656499351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1656499351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3592129448 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 6021643715 ps |
| CPU time | 33.94 seconds |
| Started | Oct 02 06:52:11 PM UTC 24 |
| Finished | Oct 02 06:52:46 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592129448 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3592129448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.674835441 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4527761354 ps |
| CPU time | 26.29 seconds |
| Started | Oct 02 06:52:11 PM UTC 24 |
| Finished | Oct 02 06:52:39 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674835441 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.674835441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1874179038 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 59221466 ps |
| CPU time | 2.89 seconds |
| Started | Oct 02 06:52:07 PM UTC 24 |
| Finished | Oct 02 06:52:11 PM UTC 24 |
| Peak memory | 215692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874179038 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1874179038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1931770150 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 375564770 ps |
| CPU time | 45.12 seconds |
| Started | Oct 02 06:52:21 PM UTC 24 |
| Finished | Oct 02 06:53:08 PM UTC 24 |
| Peak memory | 217760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931770150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1931770150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.261514309 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7003792500 ps |
| CPU time | 121.55 seconds |
| Started | Oct 02 06:52:25 PM UTC 24 |
| Finished | Oct 02 06:54:29 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261514309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.261514309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2323396451 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 281035810 ps |
| CPU time | 99.91 seconds |
| Started | Oct 02 06:52:25 PM UTC 24 |
| Finished | Oct 02 06:54:07 PM UTC 24 |
| Peak memory | 220080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323396451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2323396451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.379118594 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 288022883 ps |
| CPU time | 94.07 seconds |
| Started | Oct 02 06:52:26 PM UTC 24 |
| Finished | Oct 02 06:54:03 PM UTC 24 |
| Peak memory | 219880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379118594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.379118594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.322233558 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 57503033 ps |
| CPU time | 11.69 seconds |
| Started | Oct 02 06:52:19 PM UTC 24 |
| Finished | Oct 02 06:52:32 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322233558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.322233558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2605155134 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 148626659 ps |
| CPU time | 6.18 seconds |
| Started | Oct 02 06:52:38 PM UTC 24 |
| Finished | Oct 02 06:52:45 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605155134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2605155134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2579718194 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 71910476722 ps |
| CPU time | 724.48 seconds |
| Started | Oct 02 06:52:40 PM UTC 24 |
| Finished | Oct 02 07:04:54 PM UTC 24 |
| Peak memory | 219564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579718194 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2579718194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3346230912 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 209897932 ps |
| CPU time | 16.44 seconds |
| Started | Oct 02 06:52:45 PM UTC 24 |
| Finished | Oct 02 06:53:02 PM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346230912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3346230912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3020309120 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 155662968 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 06:52:40 PM UTC 24 |
| Finished | Oct 02 06:52:44 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020309120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3020309120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3135140562 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 393813282 ps |
| CPU time | 18.29 seconds |
| Started | Oct 02 06:52:32 PM UTC 24 |
| Finished | Oct 02 06:52:52 PM UTC 24 |
| Peak memory | 216036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135140562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3135140562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.525121373 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 103316904665 ps |
| CPU time | 259.81 seconds |
| Started | Oct 02 06:52:34 PM UTC 24 |
| Finished | Oct 02 06:56:58 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525121373 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.525121373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3224937638 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 13509475964 ps |
| CPU time | 46.66 seconds |
| Started | Oct 02 06:52:38 PM UTC 24 |
| Finished | Oct 02 06:53:26 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224937638 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3224937638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3351535715 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 172886423 ps |
| CPU time | 25.1 seconds |
| Started | Oct 02 06:52:34 PM UTC 24 |
| Finished | Oct 02 06:53:00 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351535715 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3351535715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3050327784 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 573587160 ps |
| CPU time | 13.68 seconds |
| Started | Oct 02 06:52:40 PM UTC 24 |
| Finished | Oct 02 06:52:55 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050327784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3050327784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3474352266 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 43221369 ps |
| CPU time | 2.93 seconds |
| Started | Oct 02 06:52:26 PM UTC 24 |
| Finished | Oct 02 06:52:30 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474352266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3474352266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1006004006 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 20458483796 ps |
| CPU time | 40.93 seconds |
| Started | Oct 02 06:52:29 PM UTC 24 |
| Finished | Oct 02 06:53:11 PM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006004006 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1006004006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1764704990 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 9047974153 ps |
| CPU time | 57.58 seconds |
| Started | Oct 02 06:52:30 PM UTC 24 |
| Finished | Oct 02 06:53:30 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764704990 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1764704990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1151983758 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 50022444 ps |
| CPU time | 2.98 seconds |
| Started | Oct 02 06:52:29 PM UTC 24 |
| Finished | Oct 02 06:52:33 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151983758 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1151983758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.15597830 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 757041790 ps |
| CPU time | 68.89 seconds |
| Started | Oct 02 06:52:48 PM UTC 24 |
| Finished | Oct 02 06:53:59 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15597830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.15597830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.761375363 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1119805960 ps |
| CPU time | 29.03 seconds |
| Started | Oct 02 06:52:48 PM UTC 24 |
| Finished | Oct 02 06:53:19 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761375363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.761375363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3053814708 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 239869072 ps |
| CPU time | 84.92 seconds |
| Started | Oct 02 06:52:48 PM UTC 24 |
| Finished | Oct 02 06:54:15 PM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053814708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3053814708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1387736782 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 61599171 ps |
| CPU time | 34.13 seconds |
| Started | Oct 02 06:52:48 PM UTC 24 |
| Finished | Oct 02 06:53:24 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387736782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1387736782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3144210228 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 851590924 ps |
| CPU time | 37.92 seconds |
| Started | Oct 02 06:52:42 PM UTC 24 |
| Finished | Oct 02 06:53:22 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144210228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3144210228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.842175529 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 270857604 ps |
| CPU time | 4.36 seconds |
| Started | Oct 02 06:33:33 PM UTC 24 |
| Finished | Oct 02 06:33:39 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842175529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.842175529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.3490698245 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 90504575 ps |
| CPU time | 10.18 seconds |
| Started | Oct 02 06:33:32 PM UTC 24 |
| Finished | Oct 02 06:33:44 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490698245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3490698245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.1959639215 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1821397867 ps |
| CPU time | 40.56 seconds |
| Started | Oct 02 06:33:27 PM UTC 24 |
| Finished | Oct 02 06:34:09 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959639215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1959639215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.4133714068 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 33505817684 ps |
| CPU time | 288.82 seconds |
| Started | Oct 02 06:33:27 PM UTC 24 |
| Finished | Oct 02 06:38:20 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133714068 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4133714068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3504117785 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 55168013298 ps |
| CPU time | 320.62 seconds |
| Started | Oct 02 06:33:29 PM UTC 24 |
| Finished | Oct 02 06:38:54 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504117785 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3504117785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2739253129 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 532426221 ps |
| CPU time | 27.45 seconds |
| Started | Oct 02 06:33:27 PM UTC 24 |
| Finished | Oct 02 06:33:55 PM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739253129 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2739253129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.451122005 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 107190368 ps |
| CPU time | 8.86 seconds |
| Started | Oct 02 06:33:32 PM UTC 24 |
| Finished | Oct 02 06:33:42 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451122005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.451122005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.2528122907 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 147947611 ps |
| CPU time | 5.77 seconds |
| Started | Oct 02 06:33:23 PM UTC 24 |
| Finished | Oct 02 06:33:30 PM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528122907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2528122907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4142283389 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 7772654304 ps |
| CPU time | 35.65 seconds |
| Started | Oct 02 06:33:23 PM UTC 24 |
| Finished | Oct 02 06:34:00 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142283389 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4142283389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1821387224 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2918710889 ps |
| CPU time | 31.72 seconds |
| Started | Oct 02 06:33:24 PM UTC 24 |
| Finished | Oct 02 06:33:57 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821387224 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1821387224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.592952356 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 25011289 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 06:33:23 PM UTC 24 |
| Finished | Oct 02 06:33:28 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592952356 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.592952356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.4115538006 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4743329864 ps |
| CPU time | 171.87 seconds |
| Started | Oct 02 06:33:35 PM UTC 24 |
| Finished | Oct 02 06:36:30 PM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115538006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4115538006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1171765529 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 12352044527 ps |
| CPU time | 351.1 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:39:35 PM UTC 24 |
| Peak memory | 222604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171765529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1171765529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.3396409765 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 48988120 ps |
| CPU time | 12.43 seconds |
| Started | Oct 02 06:33:32 PM UTC 24 |
| Finished | Oct 02 06:33:46 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396409765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3396409765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2038828553 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 652067266 ps |
| CPU time | 28.67 seconds |
| Started | Oct 02 06:33:43 PM UTC 24 |
| Finished | Oct 02 06:34:13 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038828553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2038828553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2976178251 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 11192424 ps |
| CPU time | 2.34 seconds |
| Started | Oct 02 06:33:45 PM UTC 24 |
| Finished | Oct 02 06:33:49 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976178251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2976178251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2545061753 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1627193452 ps |
| CPU time | 34.09 seconds |
| Started | Oct 02 06:33:44 PM UTC 24 |
| Finished | Oct 02 06:34:20 PM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545061753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2545061753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.232883497 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 461294785 ps |
| CPU time | 13.1 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:33:53 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232883497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.232883497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.74782762 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 6424188233 ps |
| CPU time | 55.11 seconds |
| Started | Oct 02 06:33:40 PM UTC 24 |
| Finished | Oct 02 06:34:37 PM UTC 24 |
| Peak memory | 216176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74782762 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.74782762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3363796875 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11884369648 ps |
| CPU time | 71.67 seconds |
| Started | Oct 02 06:33:41 PM UTC 24 |
| Finished | Oct 02 06:34:56 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363796875 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3363796875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.4056530670 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 69395309 ps |
| CPU time | 9.38 seconds |
| Started | Oct 02 06:33:40 PM UTC 24 |
| Finished | Oct 02 06:33:51 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056530670 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4056530670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.759733722 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 179171671 ps |
| CPU time | 13.12 seconds |
| Started | Oct 02 06:33:44 PM UTC 24 |
| Finished | Oct 02 06:33:59 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759733722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.759733722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.3520295802 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 146156791 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:33:43 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520295802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3520295802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2948649347 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6753357593 ps |
| CPU time | 50.22 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:34:31 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948649347 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2948649347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.970172432 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3726400318 ps |
| CPU time | 38.14 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:34:19 PM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970172432 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.970172432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3123991144 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 30083693 ps |
| CPU time | 2.92 seconds |
| Started | Oct 02 06:33:39 PM UTC 24 |
| Finished | Oct 02 06:33:43 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123991144 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3123991144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.4210012291 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 910627190 ps |
| CPU time | 116.04 seconds |
| Started | Oct 02 06:33:46 PM UTC 24 |
| Finished | Oct 02 06:35:45 PM UTC 24 |
| Peak memory | 217828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210012291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4210012291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3119529783 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 756215581 ps |
| CPU time | 62.95 seconds |
| Started | Oct 02 06:33:47 PM UTC 24 |
| Finished | Oct 02 06:34:52 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119529783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3119529783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.223496954 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 298564068 ps |
| CPU time | 136.87 seconds |
| Started | Oct 02 06:33:46 PM UTC 24 |
| Finished | Oct 02 06:36:06 PM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223496954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.223496954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1531386264 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 8175462911 ps |
| CPU time | 308.33 seconds |
| Started | Oct 02 06:33:48 PM UTC 24 |
| Finished | Oct 02 06:39:01 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531386264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1531386264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.2587311592 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 28097450 ps |
| CPU time | 8.15 seconds |
| Started | Oct 02 06:33:44 PM UTC 24 |
| Finished | Oct 02 06:33:54 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587311592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2587311592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1564253849 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 454239104 ps |
| CPU time | 39.43 seconds |
| Started | Oct 02 06:33:56 PM UTC 24 |
| Finished | Oct 02 06:34:38 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564253849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1564253849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.201478925 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 391139867 ps |
| CPU time | 19.05 seconds |
| Started | Oct 02 06:34:01 PM UTC 24 |
| Finished | Oct 02 06:34:21 PM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201478925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.201478925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2338451233 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1406074512 ps |
| CPU time | 38.95 seconds |
| Started | Oct 02 06:34:01 PM UTC 24 |
| Finished | Oct 02 06:34:42 PM UTC 24 |
| Peak memory | 215964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338451233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2338451233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3939787156 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 19788011 ps |
| CPU time | 3.26 seconds |
| Started | Oct 02 06:33:54 PM UTC 24 |
| Finished | Oct 02 06:33:58 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939787156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3939787156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.230702420 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14991783855 ps |
| CPU time | 102.91 seconds |
| Started | Oct 02 06:33:55 PM UTC 24 |
| Finished | Oct 02 06:35:40 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230702420 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.230702420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1255811515 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 15958486531 ps |
| CPU time | 121.98 seconds |
| Started | Oct 02 06:33:56 PM UTC 24 |
| Finished | Oct 02 06:36:01 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255811515 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1255811515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.2426341266 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 99439496 ps |
| CPU time | 16.33 seconds |
| Started | Oct 02 06:33:55 PM UTC 24 |
| Finished | Oct 02 06:34:13 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426341266 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2426341266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.1261306945 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 273018314 ps |
| CPU time | 24.45 seconds |
| Started | Oct 02 06:33:59 PM UTC 24 |
| Finished | Oct 02 06:34:25 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261306945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1261306945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.988252355 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 266189448 ps |
| CPU time | 5.71 seconds |
| Started | Oct 02 06:33:49 PM UTC 24 |
| Finished | Oct 02 06:33:55 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988252355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.988252355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.579659959 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4922011613 ps |
| CPU time | 34.96 seconds |
| Started | Oct 02 06:33:52 PM UTC 24 |
| Finished | Oct 02 06:34:28 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579659959 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.579659959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.516584083 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5635394617 ps |
| CPU time | 40.75 seconds |
| Started | Oct 02 06:33:53 PM UTC 24 |
| Finished | Oct 02 06:34:35 PM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516584083 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.516584083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3379389646 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 91696240 ps |
| CPU time | 3.27 seconds |
| Started | Oct 02 06:33:50 PM UTC 24 |
| Finished | Oct 02 06:33:54 PM UTC 24 |
| Peak memory | 215692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379389646 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3379389646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1671632068 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 445265657 ps |
| CPU time | 34.87 seconds |
| Started | Oct 02 06:34:01 PM UTC 24 |
| Finished | Oct 02 06:34:37 PM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671632068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1671632068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1253328694 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 201778164 ps |
| CPU time | 29.58 seconds |
| Started | Oct 02 06:34:02 PM UTC 24 |
| Finished | Oct 02 06:34:33 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253328694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1253328694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2552673265 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2421558385 ps |
| CPU time | 276.47 seconds |
| Started | Oct 02 06:34:02 PM UTC 24 |
| Finished | Oct 02 06:38:43 PM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552673265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2552673265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4199939036 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 383575352 ps |
| CPU time | 106.07 seconds |
| Started | Oct 02 06:34:02 PM UTC 24 |
| Finished | Oct 02 06:35:50 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199939036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.4199939036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2559366031 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 135684229 ps |
| CPU time | 31.94 seconds |
| Started | Oct 02 06:34:01 PM UTC 24 |
| Finished | Oct 02 06:34:34 PM UTC 24 |
| Peak memory | 217480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559366031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2559366031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.2277707632 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 694889529 ps |
| CPU time | 27.18 seconds |
| Started | Oct 02 06:34:21 PM UTC 24 |
| Finished | Oct 02 06:34:50 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277707632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2277707632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.472878606 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 313047862 ps |
| CPU time | 19.86 seconds |
| Started | Oct 02 06:34:28 PM UTC 24 |
| Finished | Oct 02 06:34:49 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472878606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.472878606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.774507714 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1189754010 ps |
| CPU time | 25.67 seconds |
| Started | Oct 02 06:34:25 PM UTC 24 |
| Finished | Oct 02 06:34:53 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774507714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.774507714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.2174616142 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 999505180 ps |
| CPU time | 21.75 seconds |
| Started | Oct 02 06:34:15 PM UTC 24 |
| Finished | Oct 02 06:34:38 PM UTC 24 |
| Peak memory | 215980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174616142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2174616142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2398755002 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 20937024939 ps |
| CPU time | 103.44 seconds |
| Started | Oct 02 06:34:15 PM UTC 24 |
| Finished | Oct 02 06:36:00 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398755002 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2398755002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3293755681 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 24333909842 ps |
| CPU time | 126.09 seconds |
| Started | Oct 02 06:34:17 PM UTC 24 |
| Finished | Oct 02 06:36:25 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293755681 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3293755681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.2060088530 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 103292395 ps |
| CPU time | 10.01 seconds |
| Started | Oct 02 06:34:15 PM UTC 24 |
| Finished | Oct 02 06:34:26 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060088530 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2060088530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3227523128 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 237720670 ps |
| CPU time | 22.14 seconds |
| Started | Oct 02 06:34:23 PM UTC 24 |
| Finished | Oct 02 06:34:47 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227523128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3227523128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3371348308 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 73510929 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 06:34:08 PM UTC 24 |
| Finished | Oct 02 06:34:13 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371348308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3371348308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3977042180 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4642720554 ps |
| CPU time | 38.85 seconds |
| Started | Oct 02 06:34:10 PM UTC 24 |
| Finished | Oct 02 06:34:51 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977042180 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3977042180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3659321806 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 6895991014 ps |
| CPU time | 38.01 seconds |
| Started | Oct 02 06:34:13 PM UTC 24 |
| Finished | Oct 02 06:34:52 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659321806 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3659321806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.753006833 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 34921931 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 06:34:10 PM UTC 24 |
| Finished | Oct 02 06:34:14 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753006833 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.753006833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1227609999 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5234739732 ps |
| CPU time | 211.95 seconds |
| Started | Oct 02 06:34:28 PM UTC 24 |
| Finished | Oct 02 06:38:03 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227609999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1227609999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2092146121 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4004033155 ps |
| CPU time | 143.41 seconds |
| Started | Oct 02 06:34:32 PM UTC 24 |
| Finished | Oct 02 06:36:58 PM UTC 24 |
| Peak memory | 219944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092146121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2092146121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4040992399 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 219406925 ps |
| CPU time | 60.08 seconds |
| Started | Oct 02 06:34:30 PM UTC 24 |
| Finished | Oct 02 06:35:32 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040992399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.4040992399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.272965055 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9234629339 ps |
| CPU time | 204.57 seconds |
| Started | Oct 02 06:34:32 PM UTC 24 |
| Finished | Oct 02 06:38:00 PM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272965055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.272965055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1002304240 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 123405008 ps |
| CPU time | 24.96 seconds |
| Started | Oct 02 06:34:28 PM UTC 24 |
| Finished | Oct 02 06:34:54 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002304240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1002304240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.76929402 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1058670216 ps |
| CPU time | 22.49 seconds |
| Started | Oct 02 06:34:40 PM UTC 24 |
| Finished | Oct 02 06:35:04 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76929402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.76929402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2212024569 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 118891072271 ps |
| CPU time | 783.04 seconds |
| Started | Oct 02 06:34:42 PM UTC 24 |
| Finished | Oct 02 06:47:55 PM UTC 24 |
| Peak memory | 219492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212024569 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2212024569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.19835765 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 835500016 ps |
| CPU time | 24.57 seconds |
| Started | Oct 02 06:34:49 PM UTC 24 |
| Finished | Oct 02 06:35:14 PM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19835765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.19835765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3225956188 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 65423340 ps |
| CPU time | 8.27 seconds |
| Started | Oct 02 06:34:44 PM UTC 24 |
| Finished | Oct 02 06:34:54 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225956188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3225956188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.109626927 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 353456060 ps |
| CPU time | 30.45 seconds |
| Started | Oct 02 06:34:40 PM UTC 24 |
| Finished | Oct 02 06:35:12 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109626927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.109626927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.976294704 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 35775334692 ps |
| CPU time | 196.68 seconds |
| Started | Oct 02 06:34:40 PM UTC 24 |
| Finished | Oct 02 06:38:00 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976294704 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.976294704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1316129752 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 55743389061 ps |
| CPU time | 269.28 seconds |
| Started | Oct 02 06:34:40 PM UTC 24 |
| Finished | Oct 02 06:39:13 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316129752 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1316129752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.745373207 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 165562341 ps |
| CPU time | 19.58 seconds |
| Started | Oct 02 06:34:40 PM UTC 24 |
| Finished | Oct 02 06:35:01 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745373207 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.745373207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3815062012 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 153779221 ps |
| CPU time | 14.12 seconds |
| Started | Oct 02 06:34:42 PM UTC 24 |
| Finished | Oct 02 06:34:57 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815062012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3815062012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.4024086862 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 252732841 ps |
| CPU time | 5.1 seconds |
| Started | Oct 02 06:34:34 PM UTC 24 |
| Finished | Oct 02 06:34:40 PM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024086862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4024086862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.913591726 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3843921075 ps |
| CPU time | 44.67 seconds |
| Started | Oct 02 06:34:36 PM UTC 24 |
| Finished | Oct 02 06:35:23 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913591726 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.913591726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2057313876 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 13545066225 ps |
| CPU time | 55.24 seconds |
| Started | Oct 02 06:34:36 PM UTC 24 |
| Finished | Oct 02 06:35:33 PM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057313876 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2057313876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1286326983 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 52050913 ps |
| CPU time | 3.85 seconds |
| Started | Oct 02 06:34:34 PM UTC 24 |
| Finished | Oct 02 06:34:39 PM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286326983 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1286326983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1361983370 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 7160529142 ps |
| CPU time | 223.04 seconds |
| Started | Oct 02 06:34:51 PM UTC 24 |
| Finished | Oct 02 06:38:37 PM UTC 24 |
| Peak memory | 222356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361983370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1361983370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3480649597 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 14868332733 ps |
| CPU time | 283.42 seconds |
| Started | Oct 02 06:34:53 PM UTC 24 |
| Finished | Oct 02 06:39:41 PM UTC 24 |
| Peak memory | 222060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480649597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3480649597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3330824656 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 194629385 ps |
| CPU time | 55.33 seconds |
| Started | Oct 02 06:34:51 PM UTC 24 |
| Finished | Oct 02 06:35:48 PM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330824656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3330824656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3160208317 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 259272065 ps |
| CPU time | 48.37 seconds |
| Started | Oct 02 06:34:53 PM UTC 24 |
| Finished | Oct 02 06:35:43 PM UTC 24 |
| Peak memory | 218092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160208317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3160208317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.2313426921 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 32871116 ps |
| CPU time | 8.1 seconds |
| Started | Oct 02 06:34:46 PM UTC 24 |
| Finished | Oct 02 06:34:56 PM UTC 24 |
| Peak memory | 215976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313426921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2313426921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest |
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