Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1541452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245833

1

T1

29

T2

7

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	606925	1			T1	63		T2	41		T3	45
values[0x0]	573644	1			T1	76		T2	9		T3	37
values[0x1]	606716	1			T1	60		T2	47		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1191281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596004

1

T1

59

T2

37

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27458	1			T2	4		T10	2		T7	5
valid_sources[0x01]	27576	1			T3	2		T11	1		T7	7
valid_sources[0x02]	28924	1			T1	7		T2	2		T10	1
valid_sources[0x03]	28402	1			T11	10		T7	1		T8	1
valid_sources[0x04]	27766	1			T2	2		T3	1		T11	7
valid_sources[0x05]	27983	1			T1	5		T2	2		T10	2
valid_sources[0x06]	27972	1			T2	5		T3	3		T11	4
valid_sources[0x07]	27942	1			T3	7		T11	1		T7	3
valid_sources[0x08]	27791	1			T3	1		T10	5		T11	1
valid_sources[0x09]	27490	1			T2	1		T3	1		T10	6
valid_sources[0x0a]	28462	1			T1	5		T2	1		T7	2
valid_sources[0x0b]	26923	1			T3	1		T10	2		T13	4
valid_sources[0x0c]	27704	1			T1	3		T10	2		T11	3
valid_sources[0x0d]	27787	1			T7	3		T12	1		T8	5
valid_sources[0x0e]	28637	1			T1	5		T2	4		T10	3
valid_sources[0x0f]	27380	1			T2	2		T3	2		T10	5
valid_sources[0x10]	28193	1			T1	6		T7	2		T8	5
valid_sources[0x11]	26836	1			T1	10		T2	1		T3	1
valid_sources[0x12]	27711	1			T1	2		T2	1		T11	4
valid_sources[0x13]	27869	1			T1	1		T2	2		T3	3
valid_sources[0x14]	28472	1			T1	7		T2	2		T7	3
valid_sources[0x15]	27855	1			T2	1		T10	1		T13	2
valid_sources[0x16]	27998	1			T2	2		T3	1		T7	2
valid_sources[0x17]	27188	1			T2	2		T10	14		T11	1
valid_sources[0x18]	27911	1			T3	7		T10	6		T8	3
valid_sources[0x19]	26955	1			T1	5		T3	2		T7	5
valid_sources[0x1a]	28149	1			T1	2		T2	1		T10	1
valid_sources[0x1b]	27787	1			T2	4		T10	1		T7	7
valid_sources[0x1c]	27868	1			T1	18		T3	9		T7	3
valid_sources[0x1d]	27839	1			T1	8		T2	3		T11	2
valid_sources[0x1e]	27986	1			T1	2		T2	1		T3	6
valid_sources[0x1f]	28064	1			T1	3		T2	3		T3	2
valid_sources[0x20]	27894	1			T7	6		T8	2		T9	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25845

1

T1

5

T2

3

T3

1

values[0x0]

all_enables

biggest_size

194220

1

T1

23

T2

2

T3

11

values[0x1]

all_enables

biggest_size

25768

1

T1

1

T2

2

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1556013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253540

1

T1

20

T2

9

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619954	1			T1	42		T2	45		T3	44
values[0x0]	571376	1			T1	49		T2	10		T3	42
values[0x1]	618223	1			T1	65		T2	47		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615801

1

T1

53

T2

31

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27869	1			T2	3		T10	3		T11	2
valid_sources[0x01]	28161	1			T1	2		T2	2		T10	1
valid_sources[0x02]	28430	1			T1	4		T2	2		T11	3
valid_sources[0x03]	28151	1			T11	1		T7	2		T8	6
valid_sources[0x04]	28177	1			T1	1		T2	3		T11	2
valid_sources[0x05]	28162	1			T1	4		T10	6		T13	4
valid_sources[0x06]	28552	1			T1	4		T2	1		T10	7
valid_sources[0x07]	28934	1			T1	1		T2	2		T10	2
valid_sources[0x08]	28697	1			T2	3		T11	4		T8	8
valid_sources[0x09]	28299	1			T1	7		T2	6		T12	2
valid_sources[0x0a]	28600	1			T1	10		T2	1		T10	3
valid_sources[0x0b]	28036	1			T1	2		T2	5		T10	3
valid_sources[0x0c]	28712	1			T1	2		T2	1		T10	1
valid_sources[0x0d]	28588	1			T1	1		T2	1		T11	3
valid_sources[0x0e]	28625	1			T1	5		T10	7		T11	3
valid_sources[0x0f]	28445	1			T2	1		T10	4		T11	1
valid_sources[0x10]	28048	1			T1	1		T2	3		T3	7
valid_sources[0x11]	28447	1			T1	2		T2	1		T10	3
valid_sources[0x12]	28120	1			T1	2		T2	1		T3	13
valid_sources[0x13]	28405	1			T3	8		T10	4		T7	5
valid_sources[0x14]	27231	1			T1	3		T10	2		T11	3
valid_sources[0x15]	28451	1			T1	5		T2	3		T10	1
valid_sources[0x16]	28008	1			T1	8		T2	3		T10	2
valid_sources[0x17]	28667	1			T1	1		T3	1		T10	2
valid_sources[0x18]	28201	1			T1	2		T2	1		T10	1
valid_sources[0x19]	27720	1			T1	7		T2	3		T10	2
valid_sources[0x1a]	28855	1			T1	1		T10	3		T11	1
valid_sources[0x1b]	28611	1			T1	1		T10	4		T11	2
valid_sources[0x1c]	29417	1			T1	4		T2	3		T11	2
valid_sources[0x1d]	27390	1			T2	1		T11	1		T7	2
valid_sources[0x1e]	28252	1			T1	1		T2	1		T10	5
valid_sources[0x1f]	28428	1			T1	5		T2	1		T7	5
valid_sources[0x20]	28440	1			T1	2		T10	2		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26386

1

T1

5

T2

4

T3

1

values[0x0]

all_enables

biggest_size

200638

1

T1

12

T2

3

T3

17

values[0x1]

all_enables

biggest_size

26516

1

T1

3

T2

2

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247476

1

T1

17

T2

14

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614490	1			T1	24		T2	43		T3	59
values[0x0]	578607	1			T1	41		T2	10		T3	55
values[0x1]	612743	1			T1	39		T2	46		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1203852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

601988

1

T1

33

T2

35

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27868	1			T1	1		T10	2		T11	7
valid_sources[0x01]	28036	1			T1	2		T2	2		T11	3
valid_sources[0x02]	28704	1			T2	4		T10	5		T8	2
valid_sources[0x03]	28321	1			T1	5		T2	2		T10	1
valid_sources[0x04]	27989	1			T10	4		T9	16		T22	11
valid_sources[0x05]	27951	1			T3	29		T10	3		T12	1
valid_sources[0x06]	28145	1			T2	1		T3	10		T10	3
valid_sources[0x07]	28944	1			T8	1		T13	1		T14	1
valid_sources[0x08]	28915	1			T1	6		T10	5		T7	2
valid_sources[0x09]	28821	1			T2	1		T10	3		T7	3
valid_sources[0x0a]	28826	1			T7	5		T8	1		T9	9
valid_sources[0x0b]	27911	1			T10	10		T11	4		T7	12
valid_sources[0x0c]	28301	1			T1	1		T7	1		T8	3
valid_sources[0x0d]	28671	1			T2	1		T3	20		T10	3
valid_sources[0x0e]	28159	1			T1	1		T2	2		T3	2
valid_sources[0x0f]	27167	1			T1	2		T2	4		T10	2
valid_sources[0x10]	28231	1			T1	11		T3	5		T7	2
valid_sources[0x11]	28792	1			T2	2		T10	1		T8	2
valid_sources[0x12]	28349	1			T2	2		T10	1		T11	6
valid_sources[0x13]	28614	1			T1	1		T2	1		T10	1
valid_sources[0x14]	27625	1			T1	2		T2	2		T10	5
valid_sources[0x15]	28231	1			T2	3		T3	18		T10	1
valid_sources[0x16]	28618	1			T2	2		T10	2		T12	1
valid_sources[0x17]	27897	1			T2	1		T10	2		T11	2
valid_sources[0x18]	27429	1			T1	2		T2	5		T10	1
valid_sources[0x19]	28039	1			T11	5		T7	12		T8	2
valid_sources[0x1a]	28116	1			T1	2		T2	1		T7	1
valid_sources[0x1b]	28164	1			T2	1		T10	7		T8	6
valid_sources[0x1c]	27951	1			T7	4		T12	1		T8	3
valid_sources[0x1d]	27958	1			T2	5		T3	7		T10	11
valid_sources[0x1e]	28212	1			T1	2		T2	4		T8	2
valid_sources[0x1f]	28927	1			T10	1		T8	1		T13	6
valid_sources[0x20]	28401	1			T2	2		T10	4		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25974

1

T2

4

T3

4

T10

1

values[0x0]

all_enables

biggest_size

195822

1

T1

17

T2

8

T3

19

values[0x1]

all_enables

biggest_size

25680

1

T2

2

T3

1

T10

2