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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.02 99.26 88.92 98.80 95.88 99.28 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T766 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.1982022316 Oct 09 05:05:48 AM UTC 24 Oct 09 05:06:19 AM UTC 24 675891151 ps
T767 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3096008782 Oct 09 05:06:16 AM UTC 24 Oct 09 05:06:20 AM UTC 24 59200644 ps
T768 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3929835016 Oct 09 05:06:16 AM UTC 24 Oct 09 05:06:21 AM UTC 24 99492560 ps
T769 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1692575255 Oct 09 05:04:08 AM UTC 24 Oct 09 05:06:26 AM UTC 24 2320387765 ps
T770 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3715326556 Oct 09 05:05:47 AM UTC 24 Oct 09 05:06:26 AM UTC 24 4462874457 ps
T771 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1895940775 Oct 09 05:06:22 AM UTC 24 Oct 09 05:06:31 AM UTC 24 57796943 ps
T772 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.482485255 Oct 09 05:06:06 AM UTC 24 Oct 09 05:06:32 AM UTC 24 155333126 ps
T773 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1810667334 Oct 09 05:05:12 AM UTC 24 Oct 09 05:06:32 AM UTC 24 23212745483 ps
T774 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2008159181 Oct 09 05:05:47 AM UTC 24 Oct 09 05:06:39 AM UTC 24 7965299454 ps
T775 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1837218759 Oct 09 05:06:02 AM UTC 24 Oct 09 05:06:39 AM UTC 24 1051682888 ps
T776 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2921364485 Oct 09 05:03:52 AM UTC 24 Oct 09 05:06:42 AM UTC 24 19077180202 ps
T777 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2308540743 Oct 09 05:02:49 AM UTC 24 Oct 09 05:06:44 AM UTC 24 9714355242 ps
T778 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1856327442 Oct 09 05:05:24 AM UTC 24 Oct 09 05:06:48 AM UTC 24 9049529012 ps
T779 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.171984216 Oct 09 05:05:32 AM UTC 24 Oct 09 05:06:49 AM UTC 24 1258268471 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.686137027 Oct 09 04:54:41 AM UTC 24 Oct 09 05:06:50 AM UTC 24 135496472936 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.710514747 Oct 09 05:05:54 AM UTC 24 Oct 09 05:06:52 AM UTC 24 2210790506 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2439242171 Oct 09 05:06:40 AM UTC 24 Oct 09 05:06:52 AM UTC 24 76446489 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3131721472 Oct 09 05:06:51 AM UTC 24 Oct 09 05:06:55 AM UTC 24 31690862 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1460992492 Oct 09 05:06:53 AM UTC 24 Oct 09 05:06:58 AM UTC 24 80235352 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.562310222 Oct 09 05:06:17 AM UTC 24 Oct 09 05:06:59 AM UTC 24 6185828085 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3097143701 Oct 09 05:06:20 AM UTC 24 Oct 09 05:07:00 AM UTC 24 1369145820 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.349636685 Oct 09 05:07:01 AM UTC 24 Oct 09 05:07:06 AM UTC 24 59660478 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.456531064 Oct 09 05:03:22 AM UTC 24 Oct 09 05:07:06 AM UTC 24 3127202485 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1421076977 Oct 09 05:00:27 AM UTC 24 Oct 09 05:07:07 AM UTC 24 7540047994 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.33563498 Oct 09 05:06:59 AM UTC 24 Oct 09 05:07:09 AM UTC 24 61133435 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3388228811 Oct 09 05:05:30 AM UTC 24 Oct 09 05:07:10 AM UTC 24 12942949028 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1491826184 Oct 09 05:06:19 AM UTC 24 Oct 09 05:07:11 AM UTC 24 3686884846 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2600388866 Oct 09 05:06:40 AM UTC 24 Oct 09 05:07:13 AM UTC 24 2944155963 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.834770690 Oct 09 05:06:33 AM UTC 24 Oct 09 05:07:15 AM UTC 24 1001051865 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2394079138 Oct 09 05:06:50 AM UTC 24 Oct 09 05:07:15 AM UTC 24 24455794 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1418108333 Oct 09 05:07:12 AM UTC 24 Oct 09 05:07:17 AM UTC 24 16190187 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.684754554 Oct 09 05:06:33 AM UTC 24 Oct 09 05:07:17 AM UTC 24 2165184905 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.818262058 Oct 09 05:03:01 AM UTC 24 Oct 09 05:07:19 AM UTC 24 98442054519 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2500041158 Oct 09 04:52:44 AM UTC 24 Oct 09 05:07:20 AM UTC 24 138703508270 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1169506376 Oct 09 05:03:03 AM UTC 24 Oct 09 05:07:23 AM UTC 24 51954387795 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.320603336 Oct 09 05:07:20 AM UTC 24 Oct 09 05:07:25 AM UTC 24 51447833 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.700529692 Oct 09 05:07:21 AM UTC 24 Oct 09 05:07:27 AM UTC 24 23102434 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2405581454 Oct 09 05:06:53 AM UTC 24 Oct 09 05:07:31 AM UTC 24 8442122661 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2635413132 Oct 09 05:07:15 AM UTC 24 Oct 09 05:07:33 AM UTC 24 216845613 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3419302363 Oct 09 05:06:28 AM UTC 24 Oct 09 05:07:35 AM UTC 24 656386484 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.959599309 Oct 09 05:06:15 AM UTC 24 Oct 09 05:07:39 AM UTC 24 270096139 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1034585014 Oct 09 05:06:56 AM UTC 24 Oct 09 05:07:39 AM UTC 24 5166898207 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.801647448 Oct 09 05:04:46 AM UTC 24 Oct 09 05:07:41 AM UTC 24 25781875416 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3331253521 Oct 09 05:05:51 AM UTC 24 Oct 09 05:07:42 AM UTC 24 21386689483 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2993288881 Oct 09 05:07:28 AM UTC 24 Oct 09 05:07:44 AM UTC 24 372499233 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3409365071 Oct 09 05:07:10 AM UTC 24 Oct 09 05:07:44 AM UTC 24 1453440929 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.221041737 Oct 09 05:07:33 AM UTC 24 Oct 09 05:07:46 AM UTC 24 62307058 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.885117389 Oct 09 05:03:40 AM UTC 24 Oct 09 05:07:47 AM UTC 24 7173217990 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3937312256 Oct 09 05:06:43 AM UTC 24 Oct 09 05:07:48 AM UTC 24 7833613867 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.933806985 Oct 09 05:07:12 AM UTC 24 Oct 09 05:07:49 AM UTC 24 929910669 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4080509363 Oct 09 05:05:21 AM UTC 24 Oct 09 05:07:50 AM UTC 24 18235907503 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.913114799 Oct 09 05:02:35 AM UTC 24 Oct 09 05:07:51 AM UTC 24 95068981197 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.578308326 Oct 09 05:07:45 AM UTC 24 Oct 09 05:07:51 AM UTC 24 38080527 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4126600610 Oct 09 05:07:48 AM UTC 24 Oct 09 05:07:51 AM UTC 24 6773176 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.336364838 Oct 09 05:06:28 AM UTC 24 Oct 09 05:07:52 AM UTC 24 16939811000 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.4270869568 Oct 09 05:07:45 AM UTC 24 Oct 09 05:07:54 AM UTC 24 35094961 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1819651665 Oct 09 05:07:43 AM UTC 24 Oct 09 05:07:56 AM UTC 24 107904042 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.52761840 Oct 09 05:07:26 AM UTC 24 Oct 09 05:07:58 AM UTC 24 3630931013 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2329039340 Oct 09 05:07:54 AM UTC 24 Oct 09 05:08:00 AM UTC 24 29782485 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2578926611 Oct 09 05:05:16 AM UTC 24 Oct 09 05:08:00 AM UTC 24 22646296016 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.292046127 Oct 09 05:07:54 AM UTC 24 Oct 09 05:08:01 AM UTC 24 162908723 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.51369694 Oct 09 05:07:24 AM UTC 24 Oct 09 05:08:04 AM UTC 24 17655762644 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1004735715 Oct 09 05:07:55 AM UTC 24 Oct 09 05:08:05 AM UTC 24 189488616 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1464436274 Oct 09 05:07:57 AM UTC 24 Oct 09 05:08:06 AM UTC 24 35501611 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1387665799 Oct 09 05:04:19 AM UTC 24 Oct 09 05:08:07 AM UTC 24 94183315115 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.240926222 Oct 09 05:08:03 AM UTC 24 Oct 09 05:08:07 AM UTC 24 25077787 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.4121489462 Oct 09 05:07:08 AM UTC 24 Oct 09 05:08:11 AM UTC 24 4127576465 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2129426237 Oct 09 05:05:07 AM UTC 24 Oct 09 05:08:13 AM UTC 24 604612830 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1517907087 Oct 09 05:07:44 AM UTC 24 Oct 09 05:08:15 AM UTC 24 896013630 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2452936608 Oct 09 05:07:55 AM UTC 24 Oct 09 05:08:21 AM UTC 24 2842105757 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.4130758704 Oct 09 05:08:16 AM UTC 24 Oct 09 05:08:22 AM UTC 24 216295186 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2289574182 Oct 09 05:02:10 AM UTC 24 Oct 09 05:08:22 AM UTC 24 126425647694 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2653762098 Oct 09 05:07:50 AM UTC 24 Oct 09 05:08:26 AM UTC 24 1768250020 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4178226594 Oct 09 05:08:05 AM UTC 24 Oct 09 05:08:27 AM UTC 24 1185966798 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1240532118 Oct 09 05:08:22 AM UTC 24 Oct 09 05:08:27 AM UTC 24 43180657 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3764330359 Oct 09 05:08:07 AM UTC 24 Oct 09 05:08:27 AM UTC 24 464714285 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3238393868 Oct 09 05:08:07 AM UTC 24 Oct 09 05:08:27 AM UTC 24 346269831 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2715514943 Oct 09 05:08:12 AM UTC 24 Oct 09 05:08:30 AM UTC 24 177759225 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1790489177 Oct 09 05:07:55 AM UTC 24 Oct 09 05:08:31 AM UTC 24 4827735261 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4245110834 Oct 09 05:08:01 AM UTC 24 Oct 09 05:08:34 AM UTC 24 2816065238 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2361862825 Oct 09 05:07:17 AM UTC 24 Oct 09 05:08:37 AM UTC 24 784996840 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2562853543 Oct 09 05:04:30 AM UTC 24 Oct 09 05:08:41 AM UTC 24 8051837354 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1264046795 Oct 09 05:07:10 AM UTC 24 Oct 09 05:08:42 AM UTC 24 12551119462 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1493272621 Oct 09 05:07:40 AM UTC 24 Oct 09 05:08:45 AM UTC 24 2803138333 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2110287530 Oct 09 05:06:22 AM UTC 24 Oct 09 05:08:50 AM UTC 24 32725284152 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3839869986 Oct 09 05:08:35 AM UTC 24 Oct 09 05:08:52 AM UTC 24 135942103 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.560229046 Oct 09 05:08:28 AM UTC 24 Oct 09 05:08:52 AM UTC 24 198899952 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3720885853 Oct 09 05:08:24 AM UTC 24 Oct 09 05:08:54 AM UTC 24 3852835613 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2402379319 Oct 09 05:08:28 AM UTC 24 Oct 09 05:08:56 AM UTC 24 490943061 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2621007675 Oct 09 04:56:54 AM UTC 24 Oct 09 05:08:58 AM UTC 24 64331189043 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.544055940 Oct 09 05:08:44 AM UTC 24 Oct 09 05:09:00 AM UTC 24 206649453 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1504799529 Oct 09 05:08:32 AM UTC 24 Oct 09 05:09:00 AM UTC 24 1053153819 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2090160778 Oct 09 05:04:49 AM UTC 24 Oct 09 05:09:01 AM UTC 24 44767485923 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3435179605 Oct 09 05:04:19 AM UTC 24 Oct 09 05:09:02 AM UTC 24 85825089167 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2529620058 Oct 09 05:02:22 AM UTC 24 Oct 09 05:09:04 AM UTC 24 9694904837 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.627182872 Oct 09 05:06:50 AM UTC 24 Oct 09 05:09:05 AM UTC 24 11079044815 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.758640331 Oct 09 05:04:33 AM UTC 24 Oct 09 05:09:08 AM UTC 24 870531002 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2106684861 Oct 09 05:06:13 AM UTC 24 Oct 09 05:09:11 AM UTC 24 1550759447 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2670376832 Oct 09 05:08:01 AM UTC 24 Oct 09 05:09:12 AM UTC 24 2114611827 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2160917394 Oct 09 05:08:24 AM UTC 24 Oct 09 05:09:13 AM UTC 24 5720327363 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.987848442 Oct 09 05:08:54 AM UTC 24 Oct 09 05:09:14 AM UTC 24 24476977 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2173445379 Oct 09 05:05:55 AM UTC 24 Oct 09 05:09:16 AM UTC 24 32959121599 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3485017034 Oct 09 05:08:38 AM UTC 24 Oct 09 05:09:18 AM UTC 24 704862175 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.843261096 Oct 09 05:08:29 AM UTC 24 Oct 09 05:09:18 AM UTC 24 1009027258 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2861368333 Oct 09 05:04:31 AM UTC 24 Oct 09 05:09:20 AM UTC 24 11505488505 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2348558607 Oct 09 05:08:29 AM UTC 24 Oct 09 05:09:27 AM UTC 24 7193771732 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1202077613 Oct 09 05:08:10 AM UTC 24 Oct 09 05:09:28 AM UTC 24 345322714 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2163812329 Oct 09 05:08:44 AM UTC 24 Oct 09 05:09:29 AM UTC 24 1481227961 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3386580040 Oct 09 05:03:30 AM UTC 24 Oct 09 05:09:46 AM UTC 24 128712857450 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.637968485 Oct 09 05:07:19 AM UTC 24 Oct 09 05:09:49 AM UTC 24 383634073 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3457652877 Oct 09 04:57:17 AM UTC 24 Oct 09 05:09:52 AM UTC 24 107613961310 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3482821292 Oct 09 05:00:50 AM UTC 24 Oct 09 05:09:52 AM UTC 24 267993475033 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1435452116 Oct 09 05:07:17 AM UTC 24 Oct 09 05:09:57 AM UTC 24 568787030 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2879257991 Oct 09 05:02:47 AM UTC 24 Oct 09 05:10:06 AM UTC 24 9012907391 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2878314686 Oct 09 05:01:38 AM UTC 24 Oct 09 05:10:14 AM UTC 24 70871953468 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4217042274 Oct 09 05:05:35 AM UTC 24 Oct 09 05:10:15 AM UTC 24 8307641994 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3133193757 Oct 09 04:59:13 AM UTC 24 Oct 09 05:10:19 AM UTC 24 219294263475 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3192189410 Oct 09 05:05:04 AM UTC 24 Oct 09 05:10:24 AM UTC 24 8788255568 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.131555485 Oct 09 05:08:51 AM UTC 24 Oct 09 05:10:37 AM UTC 24 975530685 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3153223859 Oct 09 05:06:11 AM UTC 24 Oct 09 05:10:40 AM UTC 24 572064458 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2981333939 Oct 09 05:07:59 AM UTC 24 Oct 09 05:10:41 AM UTC 24 61780314257 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4023954784 Oct 09 05:07:37 AM UTC 24 Oct 09 05:10:55 AM UTC 24 27755876425 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3155592641 Oct 09 05:05:50 AM UTC 24 Oct 09 05:10:58 AM UTC 24 44658971666 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2728438198 Oct 09 05:06:08 AM UTC 24 Oct 09 05:11:01 AM UTC 24 36878686122 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3207532966 Oct 09 05:07:08 AM UTC 24 Oct 09 05:11:07 AM UTC 24 27555305234 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2569978024 Oct 09 05:01:51 AM UTC 24 Oct 09 05:11:08 AM UTC 24 3012163884 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1237225061 Oct 09 05:07:33 AM UTC 24 Oct 09 05:11:08 AM UTC 24 156826874235 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.100501459 Oct 09 05:08:10 AM UTC 24 Oct 09 05:11:09 AM UTC 24 4790126397 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4209489141 Oct 09 05:06:45 AM UTC 24 Oct 09 05:11:15 AM UTC 24 3190994315 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3747808284 Oct 09 05:07:19 AM UTC 24 Oct 09 05:11:23 AM UTC 24 18360285874 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3315161734 Oct 09 05:07:40 AM UTC 24 Oct 09 05:11:31 AM UTC 24 30344560389 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3658733797 Oct 09 05:07:50 AM UTC 24 Oct 09 05:11:36 AM UTC 24 5131082260 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1309986236 Oct 09 05:01:08 AM UTC 24 Oct 09 05:11:36 AM UTC 24 55830202817 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3493845182 Oct 09 05:07:01 AM UTC 24 Oct 09 05:11:37 AM UTC 24 87616590259 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.364842844 Oct 09 05:08:46 AM UTC 24 Oct 09 05:11:54 AM UTC 24 1740477131 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1199025772 Oct 09 05:04:20 AM UTC 24 Oct 09 05:12:05 AM UTC 24 135271160412 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1477212127 Oct 09 05:08:03 AM UTC 24 Oct 09 05:12:25 AM UTC 24 111618851549 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2428497857 Oct 09 05:01:16 AM UTC 24 Oct 09 05:12:27 AM UTC 24 3640443598 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.286298344 Oct 09 05:08:14 AM UTC 24 Oct 09 05:12:39 AM UTC 24 3308841600 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3426963526 Oct 09 05:03:20 AM UTC 24 Oct 09 05:12:55 AM UTC 24 9395754870 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1728885214 Oct 09 05:00:20 AM UTC 24 Oct 09 05:13:17 AM UTC 24 108173374369 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3691581819 Oct 09 05:08:29 AM UTC 24 Oct 09 05:13:31 AM UTC 24 93830314175 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4058285137 Oct 09 04:54:01 AM UTC 24 Oct 09 05:13:57 AM UTC 24 484141557895 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.28884468 Oct 09 05:03:58 AM UTC 24 Oct 09 05:14:13 AM UTC 24 53851107130 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2989447484 Oct 09 05:07:49 AM UTC 24 Oct 09 05:14:49 AM UTC 24 6449228817 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1585305546 Oct 09 04:58:07 AM UTC 24 Oct 09 05:14:53 AM UTC 24 182544353628 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3511900763 Oct 09 05:08:31 AM UTC 24 Oct 09 05:15:40 AM UTC 24 40203373282 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1391128885 Oct 09 05:03:30 AM UTC 24 Oct 09 05:16:00 AM UTC 24 87452577023 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2844015842 Oct 09 05:06:33 AM UTC 24 Oct 09 05:18:20 AM UTC 24 77951756543 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3950065543 Oct 09 05:04:53 AM UTC 24 Oct 09 05:18:54 AM UTC 24 304554821677 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1844201710
Short name T2
Test name
Test status
Simulation time 395277150 ps
CPU time 24.4 seconds
Started Oct 09 04:47:32 AM UTC 24
Finished Oct 09 04:47:58 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844201710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1844201710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.1889436542
Short name T55
Test name
Test status
Simulation time 11212724945 ps
CPU time 85.93 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:47:18 AM UTC 24
Peak memory 217936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889436542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1889436542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.4036102281
Short name T161
Test name
Test status
Simulation time 71618535148 ps
CPU time 416.47 seconds
Started Oct 09 04:46:16 AM UTC 24
Finished Oct 09 04:53:18 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036102281 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.4036102281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.898642034
Short name T97
Test name
Test status
Simulation time 2045149954 ps
CPU time 97.61 seconds
Started Oct 09 04:47:56 AM UTC 24
Finished Oct 09 04:49:36 AM UTC 24
Peak memory 218016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898642034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.898642034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2262551774
Short name T22
Test name
Test status
Simulation time 282519179 ps
CPU time 14.1 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:04 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262551774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2262551774
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1923372261
Short name T305
Test name
Test status
Simulation time 13310537611 ps
CPU time 172.58 seconds
Started Oct 09 04:49:43 AM UTC 24
Finished Oct 09 04:52:39 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923372261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1923372261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.1776267581
Short name T57
Test name
Test status
Simulation time 2352362834 ps
CPU time 83.22 seconds
Started Oct 09 04:47:28 AM UTC 24
Finished Oct 09 04:48:53 AM UTC 24
Peak memory 217936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776267581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1776267581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3002955492
Short name T5
Test name
Test status
Simulation time 3655956738 ps
CPU time 35.13 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:25 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002955492 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3002955492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3332207490
Short name T142
Test name
Test status
Simulation time 53729791796 ps
CPU time 260.97 seconds
Started Oct 09 04:53:12 AM UTC 24
Finished Oct 09 04:57:37 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332207490 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.3332207490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2648517419
Short name T52
Test name
Test status
Simulation time 253201986 ps
CPU time 97.65 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:47:30 AM UTC 24
Peak memory 221980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648517419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2648517419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.2293837977
Short name T20
Test name
Test status
Simulation time 1543634110 ps
CPU time 28.81 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:20 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293837977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2293837977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.383254140
Short name T83
Test name
Test status
Simulation time 7681795370 ps
CPU time 38.31 seconds
Started Oct 09 04:46:10 AM UTC 24
Finished Oct 09 04:46:49 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383254140 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.383254140
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.152909581
Short name T141
Test name
Test status
Simulation time 6359034220 ps
CPU time 468.58 seconds
Started Oct 09 04:48:44 AM UTC 24
Finished Oct 09 04:56:40 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152909581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.152909581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.733306535
Short name T211
Test name
Test status
Simulation time 130913500647 ps
CPU time 491.73 seconds
Started Oct 09 04:51:04 AM UTC 24
Finished Oct 09 04:59:22 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733306535 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.733306535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2360341175
Short name T98
Test name
Test status
Simulation time 5869154571 ps
CPU time 223.18 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:49:38 AM UTC 24
Peak memory 219992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360341175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2360341175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1349565034
Short name T120
Test name
Test status
Simulation time 8617726144 ps
CPU time 207.76 seconds
Started Oct 09 04:49:38 AM UTC 24
Finished Oct 09 04:53:09 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349565034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1349565034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1498859343
Short name T29
Test name
Test status
Simulation time 7946785350 ps
CPU time 386.84 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:52:24 AM UTC 24
Peak memory 222524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498859343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.1498859343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.487619798
Short name T46
Test name
Test status
Simulation time 2581400492 ps
CPU time 417.49 seconds
Started Oct 09 04:46:48 AM UTC 24
Finished Oct 09 04:53:52 AM UTC 24
Peak memory 222040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487619798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.487619798
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2483283582
Short name T41
Test name
Test status
Simulation time 3385139982 ps
CPU time 375.8 seconds
Started Oct 09 04:47:08 AM UTC 24
Finished Oct 09 04:53:30 AM UTC 24
Peak memory 222176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483283582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2483283582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2063861184
Short name T93
Test name
Test status
Simulation time 837998815 ps
CPU time 14.19 seconds
Started Oct 09 04:47:21 AM UTC 24
Finished Oct 09 04:47:36 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063861184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2063861184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.563372497
Short name T147
Test name
Test status
Simulation time 43195526815 ps
CPU time 545.83 seconds
Started Oct 09 04:51:36 AM UTC 24
Finished Oct 09 05:00:49 AM UTC 24
Peak memory 219532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563372497 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.563372497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3658733797
Short name T49
Test name
Test status
Simulation time 5131082260 ps
CPU time 221.74 seconds
Started Oct 09 05:07:50 AM UTC 24
Finished Oct 09 05:11:36 AM UTC 24
Peak memory 232632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658733797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3658733797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2932160509
Short name T38
Test name
Test status
Simulation time 289669798 ps
CPU time 155.08 seconds
Started Oct 09 04:48:10 AM UTC 24
Finished Oct 09 04:50:48 AM UTC 24
Peak memory 220060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932160509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2932160509
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.4120807330
Short name T32
Test name
Test status
Simulation time 624135370 ps
CPU time 196.04 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:49:09 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120807330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4120807330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.1993674764
Short name T15
Test name
Test status
Simulation time 305962965 ps
CPU time 17.42 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:07 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993674764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1993674764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3811130433
Short name T9
Test name
Test status
Simulation time 499415955 ps
CPU time 11 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:01 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811130433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3811130433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2304246551
Short name T96
Test name
Test status
Simulation time 84256832466 ps
CPU time 209.89 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:49:22 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304246551 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2304246551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.280819858
Short name T14
Test name
Test status
Simulation time 160947732 ps
CPU time 7.66 seconds
Started Oct 09 04:45:49 AM UTC 24
Finished Oct 09 04:45:58 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280819858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.280819858
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1979128552
Short name T28
Test name
Test status
Simulation time 1440956601 ps
CPU time 36.7 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:27 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979128552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1979128552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.112419040
Short name T19
Test name
Test status
Simulation time 514724903 ps
CPU time 27.68 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:17 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112419040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.112419040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1004127929
Short name T275
Test name
Test status
Simulation time 40548283156 ps
CPU time 276.9 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:50:29 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004127929 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1004127929
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1583891128
Short name T35
Test name
Test status
Simulation time 23407664760 ps
CPU time 96.29 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:47:27 AM UTC 24
Peak memory 215916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583891128 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1583891128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.4277097499
Short name T4
Test name
Test status
Simulation time 136119417 ps
CPU time 23.08 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:13 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277097499 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4277097499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2694007919
Short name T3
Test name
Test status
Simulation time 105554684 ps
CPU time 2.73 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:45:52 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694007919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2694007919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3950000326
Short name T268
Test name
Test status
Simulation time 5452507799 ps
CPU time 49.55 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:46:39 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950000326 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3950000326
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.55830421
Short name T1
Test name
Test status
Simulation time 25210252 ps
CPU time 2.68 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:45:52 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55830421 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.55830421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.582687837
Short name T94
Test name
Test status
Simulation time 2860317485 ps
CPU time 122.05 seconds
Started Oct 09 04:45:49 AM UTC 24
Finished Oct 09 04:47:54 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582687837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.582687837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.883501214
Short name T311
Test name
Test status
Simulation time 9946801634 ps
CPU time 339.47 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:51:35 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883501214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.883501214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3871938461
Short name T269
Test name
Test status
Simulation time 153032468758 ps
CPU time 459.26 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:53:35 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871938461 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.3871938461
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.604621197
Short name T12
Test name
Test status
Simulation time 20446409 ps
CPU time 3.73 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:45:55 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604621197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.604621197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2162673631
Short name T214
Test name
Test status
Simulation time 986537586 ps
CPU time 41.83 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:34 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162673631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2162673631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.1475888524
Short name T117
Test name
Test status
Simulation time 154887968150 ps
CPU time 370.47 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:52:06 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475888524 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1475888524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1834266698
Short name T84
Test name
Test status
Simulation time 13651653380 ps
CPU time 58.12 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:50 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834266698 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1834266698
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.2749927730
Short name T18
Test name
Test status
Simulation time 396979970 ps
CPU time 23.88 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:15 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749927730 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2749927730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2387468348
Short name T205
Test name
Test status
Simulation time 2036247122 ps
CPU time 45.19 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:37 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387468348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2387468348
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2492090405
Short name T7
Test name
Test status
Simulation time 256703498 ps
CPU time 4.18 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:45:55 AM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492090405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2492090405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1884318241
Short name T207
Test name
Test status
Simulation time 10364647558 ps
CPU time 45.91 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:37 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884318241 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1884318241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2519406486
Short name T86
Test name
Test status
Simulation time 24746133258 ps
CPU time 62.43 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:54 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519406486 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2519406486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2551423634
Short name T10
Test name
Test status
Simulation time 27742767 ps
CPU time 2.97 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:45:54 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551423634 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2551423634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2635599269
Short name T317
Test name
Test status
Simulation time 1644359878 ps
CPU time 167.35 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:48:41 AM UTC 24
Peak memory 218020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635599269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2635599269
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3120653159
Short name T53
Test name
Test status
Simulation time 290922355 ps
CPU time 99.83 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:47:33 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120653159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3120653159
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2545475072
Short name T17
Test name
Test status
Simulation time 140759735 ps
CPU time 21.76 seconds
Started Oct 09 04:45:50 AM UTC 24
Finished Oct 09 04:46:13 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545475072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2545475072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.1767151036
Short name T131
Test name
Test status
Simulation time 425658253 ps
CPU time 26.71 seconds
Started Oct 09 04:49:28 AM UTC 24
Finished Oct 09 04:49:56 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767151036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1767151036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1400404939
Short name T124
Test name
Test status
Simulation time 39209903282 ps
CPU time 325.88 seconds
Started Oct 09 04:49:28 AM UTC 24
Finished Oct 09 04:54:59 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400404939 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1400404939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2219178357
Short name T129
Test name
Test status
Simulation time 406969060 ps
CPU time 12.12 seconds
Started Oct 09 04:49:37 AM UTC 24
Finished Oct 09 04:49:50 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219178357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2219178357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.3782014765
Short name T238
Test name
Test status
Simulation time 1555577529 ps
CPU time 41.8 seconds
Started Oct 09 04:49:34 AM UTC 24
Finished Oct 09 04:50:17 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782014765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3782014765
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3967612337
Short name T192
Test name
Test status
Simulation time 7860455645 ps
CPU time 47.62 seconds
Started Oct 09 04:49:24 AM UTC 24
Finished Oct 09 04:50:13 AM UTC 24
Peak memory 218072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967612337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3967612337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1969425034
Short name T375
Test name
Test status
Simulation time 30308353689 ps
CPU time 203.23 seconds
Started Oct 09 04:49:26 AM UTC 24
Finished Oct 09 04:52:52 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969425034 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1969425034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1002609538
Short name T389
Test name
Test status
Simulation time 25265292645 ps
CPU time 244.52 seconds
Started Oct 09 04:49:27 AM UTC 24
Finished Oct 09 04:53:36 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002609538 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1002609538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.2585000471
Short name T224
Test name
Test status
Simulation time 55102623 ps
CPU time 9.81 seconds
Started Oct 09 04:49:26 AM UTC 24
Finished Oct 09 04:49:37 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585000471 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2585000471
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.404868759
Short name T126
Test name
Test status
Simulation time 90587009 ps
CPU time 12.28 seconds
Started Oct 09 04:49:33 AM UTC 24
Finished Oct 09 04:49:46 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404868759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.404868759
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3097721791
Short name T344
Test name
Test status
Simulation time 35091101 ps
CPU time 2.69 seconds
Started Oct 09 04:49:21 AM UTC 24
Finished Oct 09 04:49:25 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097721791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3097721791
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2789049290
Short name T58
Test name
Test status
Simulation time 6283575371 ps
CPU time 49.84 seconds
Started Oct 09 04:49:23 AM UTC 24
Finished Oct 09 04:50:14 AM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789049290 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2789049290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1078173946
Short name T237
Test name
Test status
Simulation time 3942425884 ps
CPU time 47.17 seconds
Started Oct 09 04:49:23 AM UTC 24
Finished Oct 09 04:50:11 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078173946 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1078173946
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.146446407
Short name T219
Test name
Test status
Simulation time 29200692 ps
CPU time 4.79 seconds
Started Oct 09 04:49:21 AM UTC 24
Finished Oct 09 04:49:27 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146446407 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.146446407
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1031682336
Short name T473
Test name
Test status
Simulation time 8434898037 ps
CPU time 414.03 seconds
Started Oct 09 04:49:39 AM UTC 24
Finished Oct 09 04:56:40 AM UTC 24
Peak memory 222196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031682336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1031682336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1926279036
Short name T236
Test name
Test status
Simulation time 50753928 ps
CPU time 25.27 seconds
Started Oct 09 04:49:45 AM UTC 24
Finished Oct 09 04:50:11 AM UTC 24
Peak memory 217888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926279036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1926279036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.258250027
Short name T189
Test name
Test status
Simulation time 1714614329 ps
CPU time 33.35 seconds
Started Oct 09 04:49:37 AM UTC 24
Finished Oct 09 04:50:12 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258250027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.258250027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.685000674
Short name T134
Test name
Test status
Simulation time 229406804 ps
CPU time 37.08 seconds
Started Oct 09 04:50:10 AM UTC 24
Finished Oct 09 04:50:49 AM UTC 24
Peak memory 218076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685000674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.685000674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2800998233
Short name T315
Test name
Test status
Simulation time 151481900545 ps
CPU time 496 seconds
Started Oct 09 04:50:10 AM UTC 24
Finished Oct 09 04:58:33 AM UTC 24
Peak memory 219720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800998233 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2800998233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2861867013
Short name T239
Test name
Test status
Simulation time 65381859 ps
CPU time 3.47 seconds
Started Oct 09 04:50:13 AM UTC 24
Finished Oct 09 04:50:17 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861867013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2861867013
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1396129956
Short name T346
Test name
Test status
Simulation time 403857939 ps
CPU time 12.41 seconds
Started Oct 09 04:50:11 AM UTC 24
Finished Oct 09 04:50:25 AM UTC 24
Peak memory 216024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396129956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1396129956
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3521032239
Short name T102
Test name
Test status
Simulation time 895853294 ps
CPU time 43.09 seconds
Started Oct 09 04:49:51 AM UTC 24
Finished Oct 09 04:50:36 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521032239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3521032239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2633118845
Short name T437
Test name
Test status
Simulation time 47217437620 ps
CPU time 327.1 seconds
Started Oct 09 04:49:57 AM UTC 24
Finished Oct 09 04:55:29 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633118845 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2633118845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3240420576
Short name T63
Test name
Test status
Simulation time 33215618794 ps
CPU time 273.9 seconds
Started Oct 09 04:50:01 AM UTC 24
Finished Oct 09 04:54:39 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240420576 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3240420576
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.1464478565
Short name T266
Test name
Test status
Simulation time 239694107 ps
CPU time 36.47 seconds
Started Oct 09 04:49:51 AM UTC 24
Finished Oct 09 04:50:29 AM UTC 24
Peak memory 217868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464478565 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1464478565
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.330796718
Short name T347
Test name
Test status
Simulation time 127775949 ps
CPU time 16.41 seconds
Started Oct 09 04:50:11 AM UTC 24
Finished Oct 09 04:50:29 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330796718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.330796718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1052146716
Short name T128
Test name
Test status
Simulation time 42451239 ps
CPU time 3.35 seconds
Started Oct 09 04:49:46 AM UTC 24
Finished Oct 09 04:49:50 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052146716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1052146716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3904672042
Short name T235
Test name
Test status
Simulation time 5730810607 ps
CPU time 43.21 seconds
Started Oct 09 04:49:50 AM UTC 24
Finished Oct 09 04:50:35 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904672042 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3904672042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.275054740
Short name T240
Test name
Test status
Simulation time 2944194829 ps
CPU time 27.94 seconds
Started Oct 09 04:49:51 AM UTC 24
Finished Oct 09 04:50:20 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275054740 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.275054740
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4100042814
Short name T130
Test name
Test status
Simulation time 47682745 ps
CPU time 2.88 seconds
Started Oct 09 04:49:47 AM UTC 24
Finished Oct 09 04:49:51 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100042814 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4100042814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.4238401895
Short name T318
Test name
Test status
Simulation time 1530413651 ps
CPU time 155.63 seconds
Started Oct 09 04:50:13 AM UTC 24
Finished Oct 09 04:52:51 AM UTC 24
Peak memory 221980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238401895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4238401895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2486904308
Short name T386
Test name
Test status
Simulation time 8886878511 ps
CPU time 193.84 seconds
Started Oct 09 04:50:15 AM UTC 24
Finished Oct 09 04:53:32 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486904308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2486904308
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3907571690
Short name T193
Test name
Test status
Simulation time 3416976484 ps
CPU time 128.85 seconds
Started Oct 09 04:50:14 AM UTC 24
Finished Oct 09 04:52:25 AM UTC 24
Peak memory 220000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907571690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3907571690
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1399810622
Short name T577
Test name
Test status
Simulation time 3193942398 ps
CPU time 597.79 seconds
Started Oct 09 04:50:18 AM UTC 24
Finished Oct 09 05:00:24 AM UTC 24
Peak memory 236260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399810622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1399810622
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.869959870
Short name T348
Test name
Test status
Simulation time 130770985 ps
CPU time 15.54 seconds
Started Oct 09 04:50:13 AM UTC 24
Finished Oct 09 04:50:29 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869959870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.869959870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.4046168990
Short name T195
Test name
Test status
Simulation time 488339356 ps
CPU time 30.04 seconds
Started Oct 09 04:50:31 AM UTC 24
Finished Oct 09 04:51:03 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046168990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.4046168990
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1566805189
Short name T320
Test name
Test status
Simulation time 73128958231 ps
CPU time 340.74 seconds
Started Oct 09 04:50:34 AM UTC 24
Finished Oct 09 04:56:20 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566805189 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1566805189
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2400465794
Short name T135
Test name
Test status
Simulation time 77592258 ps
CPU time 6.78 seconds
Started Oct 09 04:50:41 AM UTC 24
Finished Oct 09 04:50:49 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400465794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2400465794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1815093333
Short name T136
Test name
Test status
Simulation time 266138197 ps
CPU time 12.26 seconds
Started Oct 09 04:50:37 AM UTC 24
Finished Oct 09 04:50:50 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815093333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1815093333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1137472589
Short name T132
Test name
Test status
Simulation time 197333996 ps
CPU time 13.91 seconds
Started Oct 09 04:50:27 AM UTC 24
Finished Oct 09 04:50:42 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137472589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1137472589
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.2886954514
Short name T119
Test name
Test status
Simulation time 25839995701 ps
CPU time 140.62 seconds
Started Oct 09 04:50:30 AM UTC 24
Finished Oct 09 04:52:53 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886954514 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2886954514
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4061737231
Short name T272
Test name
Test status
Simulation time 13718637109 ps
CPU time 99.97 seconds
Started Oct 09 04:50:30 AM UTC 24
Finished Oct 09 04:52:12 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061737231 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4061737231
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.1742961048
Short name T133
Test name
Test status
Simulation time 76583817 ps
CPU time 13.6 seconds
Started Oct 09 04:50:30 AM UTC 24
Finished Oct 09 04:50:45 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742961048 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1742961048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.736924560
Short name T201
Test name
Test status
Simulation time 1445302500 ps
CPU time 41.69 seconds
Started Oct 09 04:50:36 AM UTC 24
Finished Oct 09 04:51:19 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736924560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.736924560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1343886774
Short name T345
Test name
Test status
Simulation time 24943711 ps
CPU time 3.29 seconds
Started Oct 09 04:50:18 AM UTC 24
Finished Oct 09 04:50:22 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343886774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1343886774
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2640658873
Short name T356
Test name
Test status
Simulation time 17692877724 ps
CPU time 68.79 seconds
Started Oct 09 04:50:23 AM UTC 24
Finished Oct 09 04:51:34 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640658873 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2640658873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2730138909
Short name T357
Test name
Test status
Simulation time 19394710216 ps
CPU time 68.34 seconds
Started Oct 09 04:50:26 AM UTC 24
Finished Oct 09 04:51:36 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730138909 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2730138909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4218125311
Short name T337
Test name
Test status
Simulation time 70379595 ps
CPU time 3.16 seconds
Started Oct 09 04:50:21 AM UTC 24
Finished Oct 09 04:50:26 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218125311 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4218125311
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3204466845
Short name T383
Test name
Test status
Simulation time 3497537774 ps
CPU time 138.71 seconds
Started Oct 09 04:50:43 AM UTC 24
Finished Oct 09 04:53:04 AM UTC 24
Peak memory 218072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204466845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3204466845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3870993626
Short name T411
Test name
Test status
Simulation time 9880491836 ps
CPU time 204.69 seconds
Started Oct 09 04:50:49 AM UTC 24
Finished Oct 09 04:54:17 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870993626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3870993626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3002785019
Short name T204
Test name
Test status
Simulation time 2778051187 ps
CPU time 410.51 seconds
Started Oct 09 04:50:46 AM UTC 24
Finished Oct 09 04:57:42 AM UTC 24
Peak memory 222064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002785019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.3002785019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1263985044
Short name T324
Test name
Test status
Simulation time 29488961 ps
CPU time 34.55 seconds
Started Oct 09 04:50:49 AM UTC 24
Finished Oct 09 04:51:25 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263985044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1263985044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3271679498
Short name T196
Test name
Test status
Simulation time 120833727 ps
CPU time 23.47 seconds
Started Oct 09 04:50:38 AM UTC 24
Finished Oct 09 04:51:03 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271679498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3271679498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3292176822
Short name T200
Test name
Test status
Simulation time 1095639338 ps
CPU time 13.34 seconds
Started Oct 09 04:51:04 AM UTC 24
Finished Oct 09 04:51:18 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292176822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3292176822
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.442657659
Short name T350
Test name
Test status
Simulation time 89401510 ps
CPU time 8.09 seconds
Started Oct 09 04:51:16 AM UTC 24
Finished Oct 09 04:51:25 AM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442657659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.442657659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.4055944318
Short name T355
Test name
Test status
Simulation time 368076182 ps
CPU time 25.08 seconds
Started Oct 09 04:51:08 AM UTC 24
Finished Oct 09 04:51:34 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055944318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4055944318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.3868839854
Short name T199
Test name
Test status
Simulation time 186714685 ps
CPU time 17.09 seconds
Started Oct 09 04:50:57 AM UTC 24
Finished Oct 09 04:51:15 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868839854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3868839854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.3554578562
Short name T168
Test name
Test status
Simulation time 70189123838 ps
CPU time 293.93 seconds
Started Oct 09 04:51:01 AM UTC 24
Finished Oct 09 04:55:59 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554578562 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3554578562
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.436222866
Short name T423
Test name
Test status
Simulation time 36228162357 ps
CPU time 224.27 seconds
Started Oct 09 04:51:03 AM UTC 24
Finished Oct 09 04:54:50 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436222866 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.436222866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.2533897807
Short name T351
Test name
Test status
Simulation time 248379105 ps
CPU time 27.05 seconds
Started Oct 09 04:50:59 AM UTC 24
Finished Oct 09 04:51:28 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533897807 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2533897807
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1982289101
Short name T198
Test name
Test status
Simulation time 178042023 ps
CPU time 5.43 seconds
Started Oct 09 04:51:08 AM UTC 24
Finished Oct 09 04:51:14 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982289101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1982289101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.291850324
Short name T137
Test name
Test status
Simulation time 150696143 ps
CPU time 3.78 seconds
Started Oct 09 04:50:50 AM UTC 24
Finished Oct 09 04:50:55 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291850324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.291850324
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.966306197
Short name T61
Test name
Test status
Simulation time 11162350808 ps
CPU time 46.34 seconds
Started Oct 09 04:50:56 AM UTC 24
Finished Oct 09 04:51:44 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966306197 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.966306197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.3277285870
Short name T374
Test name
Test status
Simulation time 44309203240 ps
CPU time 111.83 seconds
Started Oct 09 04:50:57 AM UTC 24
Finished Oct 09 04:52:51 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277285870 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3277285870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.869857683
Short name T138
Test name
Test status
Simulation time 40446062 ps
CPU time 3.7 seconds
Started Oct 09 04:50:51 AM UTC 24
Finished Oct 09 04:50:56 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869857683 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.869857683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.2663445366
Short name T118
Test name
Test status
Simulation time 2693580899 ps
CPU time 58.43 seconds
Started Oct 09 04:51:19 AM UTC 24
Finished Oct 09 04:52:19 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663445366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2663445366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4065786742
Short name T358
Test name
Test status
Simulation time 383178349 ps
CPU time 26.99 seconds
Started Oct 09 04:51:22 AM UTC 24
Finished Oct 09 04:51:50 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065786742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4065786742
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1239444004
Short name T169
Test name
Test status
Simulation time 1414331659 ps
CPU time 275.41 seconds
Started Oct 09 04:51:20 AM UTC 24
Finished Oct 09 04:56:00 AM UTC 24
Peak memory 222324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239444004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1239444004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1229568212
Short name T327
Test name
Test status
Simulation time 85669574 ps
CPU time 29.13 seconds
Started Oct 09 04:51:22 AM UTC 24
Finished Oct 09 04:51:52 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229568212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1229568212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3830284947
Short name T60
Test name
Test status
Simulation time 2425971001 ps
CPU time 26.91 seconds
Started Oct 09 04:51:15 AM UTC 24
Finished Oct 09 04:51:43 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830284947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3830284947
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.780883469
Short name T216
Test name
Test status
Simulation time 1288458897 ps
CPU time 34.1 seconds
Started Oct 09 04:51:35 AM UTC 24
Finished Oct 09 04:52:11 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780883469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.780883469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1945276001
Short name T271
Test name
Test status
Simulation time 1434792326 ps
CPU time 24.93 seconds
Started Oct 09 04:51:45 AM UTC 24
Finished Oct 09 04:52:11 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945276001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1945276001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.3908722006
Short name T361
Test name
Test status
Simulation time 318364943 ps
CPU time 21.14 seconds
Started Oct 09 04:51:37 AM UTC 24
Finished Oct 09 04:51:59 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908722006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3908722006
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3788925151
Short name T116
Test name
Test status
Simulation time 1685897162 ps
CPU time 28.91 seconds
Started Oct 09 04:51:30 AM UTC 24
Finished Oct 09 04:52:01 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788925151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3788925151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.107762179
Short name T400
Test name
Test status
Simulation time 25283135322 ps
CPU time 138.43 seconds
Started Oct 09 04:51:33 AM UTC 24
Finished Oct 09 04:53:54 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107762179 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.107762179
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.816081808
Short name T405
Test name
Test status
Simulation time 19812801587 ps
CPU time 142.92 seconds
Started Oct 09 04:51:33 AM UTC 24
Finished Oct 09 04:53:59 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816081808 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.816081808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2123695259
Short name T360
Test name
Test status
Simulation time 147600078 ps
CPU time 22.27 seconds
Started Oct 09 04:51:31 AM UTC 24
Finished Oct 09 04:51:55 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123695259 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2123695259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1876185784
Short name T359
Test name
Test status
Simulation time 444906226 ps
CPU time 17.95 seconds
Started Oct 09 04:51:36 AM UTC 24
Finished Oct 09 04:51:55 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876185784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1876185784
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.3179402431
Short name T352
Test name
Test status
Simulation time 60712365 ps
CPU time 3.09 seconds
Started Oct 09 04:51:25 AM UTC 24
Finished Oct 09 04:51:29 AM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179402431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3179402431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2383958154
Short name T364
Test name
Test status
Simulation time 10480171838 ps
CPU time 39.09 seconds
Started Oct 09 04:51:26 AM UTC 24
Finished Oct 09 04:52:07 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383958154 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2383958154
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2383299426
Short name T365
Test name
Test status
Simulation time 3338229414 ps
CPU time 37.12 seconds
Started Oct 09 04:51:28 AM UTC 24
Finished Oct 09 04:52:07 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383299426 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2383299426
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3050970916
Short name T353
Test name
Test status
Simulation time 29561117 ps
CPU time 3.75 seconds
Started Oct 09 04:51:26 AM UTC 24
Finished Oct 09 04:51:31 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050970916 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3050970916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1604654068
Short name T312
Test name
Test status
Simulation time 2971696703 ps
CPU time 115.09 seconds
Started Oct 09 04:51:51 AM UTC 24
Finished Oct 09 04:53:49 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604654068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1604654068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1958440619
Short name T390
Test name
Test status
Simulation time 3996346368 ps
CPU time 99.37 seconds
Started Oct 09 04:51:56 AM UTC 24
Finished Oct 09 04:53:37 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958440619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1958440619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.299679277
Short name T255
Test name
Test status
Simulation time 4995884284 ps
CPU time 230.7 seconds
Started Oct 09 04:51:53 AM UTC 24
Finished Oct 09 04:55:48 AM UTC 24
Peak memory 219992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299679277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.299679277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2498119376
Short name T310
Test name
Test status
Simulation time 5911130994 ps
CPU time 306.36 seconds
Started Oct 09 04:51:57 AM UTC 24
Finished Oct 09 04:57:08 AM UTC 24
Peak memory 236728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498119376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2498119376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1680803478
Short name T298
Test name
Test status
Simulation time 199877388 ps
CPU time 11.92 seconds
Started Oct 09 04:51:44 AM UTC 24
Finished Oct 09 04:51:57 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680803478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1680803478
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2437729428
Short name T273
Test name
Test status
Simulation time 90742214 ps
CPU time 6.48 seconds
Started Oct 09 04:52:12 AM UTC 24
Finished Oct 09 04:52:20 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437729428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2437729428
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.223463305
Short name T480
Test name
Test status
Simulation time 31867912772 ps
CPU time 283.75 seconds
Started Oct 09 04:52:12 AM UTC 24
Finished Oct 09 04:57:00 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223463305 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.223463305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1663775557
Short name T371
Test name
Test status
Simulation time 348888258 ps
CPU time 19.73 seconds
Started Oct 09 04:52:20 AM UTC 24
Finished Oct 09 04:52:42 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663775557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1663775557
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2337040916
Short name T274
Test name
Test status
Simulation time 47923358 ps
CPU time 3.73 seconds
Started Oct 09 04:52:16 AM UTC 24
Finished Oct 09 04:52:21 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337040916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2337040916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2499213828
Short name T369
Test name
Test status
Simulation time 654644755 ps
CPU time 26.59 seconds
Started Oct 09 04:52:06 AM UTC 24
Finished Oct 09 04:52:34 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499213828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2499213828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1179187585
Short name T453
Test name
Test status
Simulation time 75133811795 ps
CPU time 222.72 seconds
Started Oct 09 04:52:08 AM UTC 24
Finished Oct 09 04:55:54 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179187585 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1179187585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1140370916
Short name T421
Test name
Test status
Simulation time 41543483456 ps
CPU time 157.29 seconds
Started Oct 09 04:52:08 AM UTC 24
Finished Oct 09 04:54:48 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140370916 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1140370916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.973870770
Short name T366
Test name
Test status
Simulation time 322754910 ps
CPU time 19.33 seconds
Started Oct 09 04:52:07 AM UTC 24
Finished Oct 09 04:52:27 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973870770 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.973870770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2010388808
Short name T378
Test name
Test status
Simulation time 2434436481 ps
CPU time 42.83 seconds
Started Oct 09 04:52:13 AM UTC 24
Finished Oct 09 04:52:58 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010388808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2010388808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.201619814
Short name T362
Test name
Test status
Simulation time 49635181 ps
CPU time 3.05 seconds
Started Oct 09 04:51:58 AM UTC 24
Finished Oct 09 04:52:03 AM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201619814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.201619814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1462093186
Short name T373
Test name
Test status
Simulation time 5801368418 ps
CPU time 44.12 seconds
Started Oct 09 04:52:01 AM UTC 24
Finished Oct 09 04:52:47 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462093186 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1462093186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2124490709
Short name T376
Test name
Test status
Simulation time 8079787801 ps
CPU time 51.83 seconds
Started Oct 09 04:52:03 AM UTC 24
Finished Oct 09 04:52:57 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124490709 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2124490709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3795758069
Short name T363
Test name
Test status
Simulation time 23929566 ps
CPU time 3.5 seconds
Started Oct 09 04:52:00 AM UTC 24
Finished Oct 09 04:52:05 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795758069 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3795758069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3057973510
Short name T438
Test name
Test status
Simulation time 2217303950 ps
CPU time 186.2 seconds
Started Oct 09 04:52:20 AM UTC 24
Finished Oct 09 04:55:30 AM UTC 24
Peak memory 220000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057973510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3057973510
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3780335251
Short name T417
Test name
Test status
Simulation time 10498162994 ps
CPU time 119.71 seconds
Started Oct 09 04:52:25 AM UTC 24
Finished Oct 09 04:54:27 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780335251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3780335251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2965327727
Short name T661
Test name
Test status
Simulation time 20523039945 ps
CPU time 644.09 seconds
Started Oct 09 04:52:22 AM UTC 24
Finished Oct 09 05:03:14 AM UTC 24
Peak memory 221576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965327727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2965327727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.558427638
Short name T31
Test name
Test status
Simulation time 7165329921 ps
CPU time 258.24 seconds
Started Oct 09 04:52:26 AM UTC 24
Finished Oct 09 04:56:49 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558427638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.558427638
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3542182412
Short name T372
Test name
Test status
Simulation time 996715476 ps
CPU time 27 seconds
Started Oct 09 04:52:18 AM UTC 24
Finished Oct 09 04:52:47 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542182412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3542182412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.1630034728
Short name T225
Test name
Test status
Simulation time 1246969306 ps
CPU time 49.78 seconds
Started Oct 09 04:52:43 AM UTC 24
Finished Oct 09 04:53:34 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630034728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1630034728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2500041158
Short name T797
Test name
Test status
Simulation time 138703508270 ps
CPU time 864.63 seconds
Started Oct 09 04:52:44 AM UTC 24
Finished Oct 09 05:07:20 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500041158 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2500041158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.608942625
Short name T379
Test name
Test status
Simulation time 64099103 ps
CPU time 7.34 seconds
Started Oct 09 04:52:53 AM UTC 24
Finished Oct 09 04:53:01 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608942625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.608942625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3025569304
Short name T156
Test name
Test status
Simulation time 269353311 ps
CPU time 21.84 seconds
Started Oct 09 04:52:48 AM UTC 24
Finished Oct 09 04:53:11 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025569304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3025569304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1565663713
Short name T380
Test name
Test status
Simulation time 618623487 ps
CPU time 25.26 seconds
Started Oct 09 04:52:35 AM UTC 24
Finished Oct 09 04:53:02 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565663713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1565663713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1257062047
Short name T459
Test name
Test status
Simulation time 34991887130 ps
CPU time 216.51 seconds
Started Oct 09 04:52:39 AM UTC 24
Finished Oct 09 04:56:18 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257062047 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1257062047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2367893799
Short name T394
Test name
Test status
Simulation time 5392753314 ps
CPU time 60.96 seconds
Started Oct 09 04:52:40 AM UTC 24
Finished Oct 09 04:53:42 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367893799 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2367893799
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1470456292
Short name T377
Test name
Test status
Simulation time 229371918 ps
CPU time 15.51 seconds
Started Oct 09 04:52:37 AM UTC 24
Finished Oct 09 04:52:54 AM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470456292 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1470456292
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3045661815
Short name T157
Test name
Test status
Simulation time 2833328803 ps
CPU time 24.53 seconds
Started Oct 09 04:52:47 AM UTC 24
Finished Oct 09 04:53:13 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045661815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3045661815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1252493973
Short name T368
Test name
Test status
Simulation time 157763043 ps
CPU time 3.43 seconds
Started Oct 09 04:52:28 AM UTC 24
Finished Oct 09 04:52:33 AM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252493973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1252493973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3250309058
Short name T384
Test name
Test status
Simulation time 6139470231 ps
CPU time 51.48 seconds
Started Oct 09 04:52:34 AM UTC 24
Finished Oct 09 04:53:27 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250309058 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3250309058
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1176390068
Short name T385
Test name
Test status
Simulation time 4548183333 ps
CPU time 51.84 seconds
Started Oct 09 04:52:34 AM UTC 24
Finished Oct 09 04:53:28 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176390068 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1176390068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2834590695
Short name T370
Test name
Test status
Simulation time 35242868 ps
CPU time 3.63 seconds
Started Oct 09 04:52:33 AM UTC 24
Finished Oct 09 04:52:38 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834590695 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2834590695
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.2131886418
Short name T202
Test name
Test status
Simulation time 8705955465 ps
CPU time 168.55 seconds
Started Oct 09 04:52:54 AM UTC 24
Finished Oct 09 04:55:46 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131886418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2131886418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.782037178
Short name T319
Test name
Test status
Simulation time 4034490764 ps
CPU time 142.79 seconds
Started Oct 09 04:52:56 AM UTC 24
Finished Oct 09 04:55:21 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782037178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.782037178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1334000323
Short name T396
Test name
Test status
Simulation time 127238977 ps
CPU time 52.43 seconds
Started Oct 09 04:52:54 AM UTC 24
Finished Oct 09 04:53:49 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334000323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1334000323
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1307088325
Short name T323
Test name
Test status
Simulation time 389808720 ps
CPU time 153.61 seconds
Started Oct 09 04:52:57 AM UTC 24
Finished Oct 09 04:55:34 AM UTC 24
Peak memory 221984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307088325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1307088325
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.375972093
Short name T162
Test name
Test status
Simulation time 569913473 ps
CPU time 28.8 seconds
Started Oct 09 04:52:52 AM UTC 24
Finished Oct 09 04:53:22 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375972093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.375972093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.332174178
Short name T122
Test name
Test status
Simulation time 1932000811 ps
CPU time 61.09 seconds
Started Oct 09 04:53:10 AM UTC 24
Finished Oct 09 04:54:12 AM UTC 24
Peak memory 217888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332174178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.332174178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3366437139
Short name T393
Test name
Test status
Simulation time 923278143 ps
CPU time 20.93 seconds
Started Oct 09 04:53:18 AM UTC 24
Finished Oct 09 04:53:41 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366437139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3366437139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2737276489
Short name T397
Test name
Test status
Simulation time 372782973 ps
CPU time 30.72 seconds
Started Oct 09 04:53:17 AM UTC 24
Finished Oct 09 04:53:49 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737276489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2737276489
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.4193256224
Short name T160
Test name
Test status
Simulation time 450561090 ps
CPU time 12.01 seconds
Started Oct 09 04:53:04 AM UTC 24
Finished Oct 09 04:53:17 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193256224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4193256224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2222708552
Short name T560
Test name
Test status
Simulation time 145878927004 ps
CPU time 394.28 seconds
Started Oct 09 04:53:05 AM UTC 24
Finished Oct 09 04:59:45 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222708552 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2222708552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4126251113
Short name T471
Test name
Test status
Simulation time 22109079667 ps
CPU time 206.9 seconds
Started Oct 09 04:53:05 AM UTC 24
Finished Oct 09 04:56:35 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126251113 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4126251113
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.3052661464
Short name T163
Test name
Test status
Simulation time 137620792 ps
CPU time 16.63 seconds
Started Oct 09 04:53:05 AM UTC 24
Finished Oct 09 04:53:23 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052661464 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3052661464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.2517883651
Short name T391
Test name
Test status
Simulation time 327558649 ps
CPU time 22.73 seconds
Started Oct 09 04:53:14 AM UTC 24
Finished Oct 09 04:53:38 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517883651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2517883651
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.4124650505
Short name T381
Test name
Test status
Simulation time 23296752 ps
CPU time 3.6 seconds
Started Oct 09 04:52:58 AM UTC 24
Finished Oct 09 04:53:03 AM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124650505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.4124650505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2320695363
Short name T403
Test name
Test status
Simulation time 6311422184 ps
CPU time 52.77 seconds
Started Oct 09 04:53:03 AM UTC 24
Finished Oct 09 04:53:57 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320695363 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2320695363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1335224165
Short name T401
Test name
Test status
Simulation time 4279884391 ps
CPU time 49.86 seconds
Started Oct 09 04:53:03 AM UTC 24
Finished Oct 09 04:53:54 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335224165 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1335224165
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.682004994
Short name T382
Test name
Test status
Simulation time 66577484 ps
CPU time 4.32 seconds
Started Oct 09 04:52:58 AM UTC 24
Finished Oct 09 04:53:04 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682004994 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.682004994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.4178175706
Short name T173
Test name
Test status
Simulation time 3186300419 ps
CPU time 167.14 seconds
Started Oct 09 04:53:20 AM UTC 24
Finished Oct 09 04:56:10 AM UTC 24
Peak memory 220060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178175706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4178175706
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2976040922
Short name T474
Test name
Test status
Simulation time 5493927747 ps
CPU time 206.44 seconds
Started Oct 09 04:53:24 AM UTC 24
Finished Oct 09 04:56:54 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976040922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2976040922
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.159165009
Short name T491
Test name
Test status
Simulation time 5656133227 ps
CPU time 232.99 seconds
Started Oct 09 04:53:23 AM UTC 24
Finished Oct 09 04:57:20 AM UTC 24
Peak memory 222040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159165009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.159165009
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4180348607
Short name T599
Test name
Test status
Simulation time 2471095921 ps
CPU time 457.52 seconds
Started Oct 09 04:53:28 AM UTC 24
Finished Oct 09 05:01:13 AM UTC 24
Peak memory 232632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180348607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.4180348607
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.261794920
Short name T164
Test name
Test status
Simulation time 28284961 ps
CPU time 8.73 seconds
Started Oct 09 04:53:17 AM UTC 24
Finished Oct 09 04:53:27 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261794920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.261794920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.1623258916
Short name T280
Test name
Test status
Simulation time 2013620174 ps
CPU time 87.5 seconds
Started Oct 09 04:53:38 AM UTC 24
Finished Oct 09 04:55:07 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623258916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1623258916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4045561891
Short name T140
Test name
Test status
Simulation time 18815578212 ps
CPU time 134.83 seconds
Started Oct 09 04:53:38 AM UTC 24
Finished Oct 09 04:55:55 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045561891 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.4045561891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.61391723
Short name T407
Test name
Test status
Simulation time 94357393 ps
CPU time 21.78 seconds
Started Oct 09 04:53:43 AM UTC 24
Finished Oct 09 04:54:06 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61391723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.61391723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.775112700
Short name T398
Test name
Test status
Simulation time 323096883 ps
CPU time 10.46 seconds
Started Oct 09 04:53:40 AM UTC 24
Finished Oct 09 04:53:52 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775112700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.775112700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.68556435
Short name T392
Test name
Test status
Simulation time 77476277 ps
CPU time 5.24 seconds
Started Oct 09 04:53:33 AM UTC 24
Finished Oct 09 04:53:40 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68556435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.68556435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.1312765574
Short name T482
Test name
Test status
Simulation time 42710481063 ps
CPU time 210.62 seconds
Started Oct 09 04:53:36 AM UTC 24
Finished Oct 09 04:57:10 AM UTC 24
Peak memory 216036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312765574 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1312765574
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.168913050
Short name T450
Test name
Test status
Simulation time 21443094310 ps
CPU time 131.31 seconds
Started Oct 09 04:53:36 AM UTC 24
Finished Oct 09 04:55:50 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168913050 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.168913050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3718118679
Short name T409
Test name
Test status
Simulation time 908451016 ps
CPU time 37.43 seconds
Started Oct 09 04:53:35 AM UTC 24
Finished Oct 09 04:54:14 AM UTC 24
Peak memory 218004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718118679 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3718118679
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1885252033
Short name T399
Test name
Test status
Simulation time 110832205 ps
CPU time 13.08 seconds
Started Oct 09 04:53:39 AM UTC 24
Finished Oct 09 04:53:53 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885252033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1885252033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2732341991
Short name T387
Test name
Test status
Simulation time 32487590 ps
CPU time 3.34 seconds
Started Oct 09 04:53:28 AM UTC 24
Finished Oct 09 04:53:33 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732341991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2732341991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1691933711
Short name T62
Test name
Test status
Simulation time 11577958597 ps
CPU time 37.77 seconds
Started Oct 09 04:53:31 AM UTC 24
Finished Oct 09 04:54:10 AM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691933711 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1691933711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1587585901
Short name T406
Test name
Test status
Simulation time 3223877298 ps
CPU time 28.23 seconds
Started Oct 09 04:53:33 AM UTC 24
Finished Oct 09 04:54:03 AM UTC 24
Peak memory 216068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587585901 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1587585901
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1447176227
Short name T388
Test name
Test status
Simulation time 33949741 ps
CPU time 3.43 seconds
Started Oct 09 04:53:29 AM UTC 24
Finished Oct 09 04:53:33 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447176227 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1447176227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.494955158
Short name T447
Test name
Test status
Simulation time 2078559068 ps
CPU time 112.8 seconds
Started Oct 09 04:53:48 AM UTC 24
Finished Oct 09 04:55:44 AM UTC 24
Peak memory 219928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494955158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.494955158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1955281404
Short name T420
Test name
Test status
Simulation time 1613125725 ps
CPU time 48.18 seconds
Started Oct 09 04:53:50 AM UTC 24
Finished Oct 09 04:54:39 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955281404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1955281404
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2418942945
Short name T643
Test name
Test status
Simulation time 11314792816 ps
CPU time 518.24 seconds
Started Oct 09 04:53:50 AM UTC 24
Finished Oct 09 05:02:35 AM UTC 24
Peak memory 220352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418942945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2418942945
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3751017701
Short name T418
Test name
Test status
Simulation time 183153661 ps
CPU time 40.14 seconds
Started Oct 09 04:53:50 AM UTC 24
Finished Oct 09 04:54:32 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751017701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3751017701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.2572089104
Short name T395
Test name
Test status
Simulation time 110213571 ps
CPU time 4.46 seconds
Started Oct 09 04:53:42 AM UTC 24
Finished Oct 09 04:53:47 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572089104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2572089104
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.965386446
Short name T408
Test name
Test status
Simulation time 843133254 ps
CPU time 10.28 seconds
Started Oct 09 04:54:00 AM UTC 24
Finished Oct 09 04:54:11 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965386446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.965386446
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.4058285137
Short name T896
Test name
Test status
Simulation time 484141557895 ps
CPU time 1181.02 seconds
Started Oct 09 04:54:01 AM UTC 24
Finished Oct 09 05:13:57 AM UTC 24
Peak memory 219532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058285137 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.4058285137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3488248191
Short name T422
Test name
Test status
Simulation time 822953332 ps
CPU time 33.79 seconds
Started Oct 09 04:54:13 AM UTC 24
Finished Oct 09 04:54:48 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488248191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3488248191
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1564758637
Short name T412
Test name
Test status
Simulation time 889896551 ps
CPU time 11.32 seconds
Started Oct 09 04:54:07 AM UTC 24
Finished Oct 09 04:54:20 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564758637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1564758637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1670354079
Short name T123
Test name
Test status
Simulation time 1708711462 ps
CPU time 21.22 seconds
Started Oct 09 04:53:56 AM UTC 24
Finished Oct 09 04:54:18 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670354079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1670354079
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3994315072
Short name T507
Test name
Test status
Simulation time 101949769461 ps
CPU time 240.9 seconds
Started Oct 09 04:53:58 AM UTC 24
Finished Oct 09 04:58:03 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994315072 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3994315072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2691827762
Short name T184
Test name
Test status
Simulation time 31683550643 ps
CPU time 237.88 seconds
Started Oct 09 04:54:00 AM UTC 24
Finished Oct 09 04:58:02 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691827762 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2691827762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1599718221
Short name T410
Test name
Test status
Simulation time 143905116 ps
CPU time 17.66 seconds
Started Oct 09 04:53:58 AM UTC 24
Finished Oct 09 04:54:17 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599718221 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1599718221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.1729305162
Short name T413
Test name
Test status
Simulation time 206570240 ps
CPU time 16.98 seconds
Started Oct 09 04:54:04 AM UTC 24
Finished Oct 09 04:54:22 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729305162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1729305162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3245993421
Short name T402
Test name
Test status
Simulation time 30186234 ps
CPU time 3.21 seconds
Started Oct 09 04:53:53 AM UTC 24
Finished Oct 09 04:53:57 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245993421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3245993421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.4080617440
Short name T425
Test name
Test status
Simulation time 7227700252 ps
CPU time 57.65 seconds
Started Oct 09 04:53:54 AM UTC 24
Finished Oct 09 04:54:53 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080617440 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4080617440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2458847483
Short name T442
Test name
Test status
Simulation time 37682452308 ps
CPU time 99.23 seconds
Started Oct 09 04:53:56 AM UTC 24
Finished Oct 09 04:55:37 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458847483 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2458847483
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.436165447
Short name T404
Test name
Test status
Simulation time 39385017 ps
CPU time 4.4 seconds
Started Oct 09 04:53:53 AM UTC 24
Finished Oct 09 04:53:58 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436165447 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.436165447
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2802289763
Short name T226
Test name
Test status
Simulation time 488335735 ps
CPU time 59.69 seconds
Started Oct 09 04:54:14 AM UTC 24
Finished Oct 09 04:55:16 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802289763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2802289763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1885934521
Short name T245
Test name
Test status
Simulation time 9343859952 ps
CPU time 144.55 seconds
Started Oct 09 04:54:18 AM UTC 24
Finished Oct 09 04:56:46 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885934521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1885934521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.15696144
Short name T449
Test name
Test status
Simulation time 208978209 ps
CPU time 89.41 seconds
Started Oct 09 04:54:14 AM UTC 24
Finished Oct 09 04:55:46 AM UTC 24
Peak memory 219924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15696144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.15696144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1061193482
Short name T326
Test name
Test status
Simulation time 388236063 ps
CPU time 87.08 seconds
Started Oct 09 04:54:18 AM UTC 24
Finished Oct 09 04:55:48 AM UTC 24
Peak memory 221984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061193482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1061193482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3622132837
Short name T414
Test name
Test status
Simulation time 36207601 ps
CPU time 9.06 seconds
Started Oct 09 04:54:12 AM UTC 24
Finished Oct 09 04:54:22 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622132837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3622132837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1067225321
Short name T16
Test name
Test status
Simulation time 84538661 ps
CPU time 14.2 seconds
Started Oct 09 04:45:54 AM UTC 24
Finished Oct 09 04:46:10 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067225321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1067225321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1654284814
Short name T314
Test name
Test status
Simulation time 50360583938 ps
CPU time 395.69 seconds
Started Oct 09 04:45:55 AM UTC 24
Finished Oct 09 04:52:37 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654284814 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1654284814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3177307211
Short name T27
Test name
Test status
Simulation time 1206118671 ps
CPU time 32.21 seconds
Started Oct 09 04:45:58 AM UTC 24
Finished Oct 09 04:46:31 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177307211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3177307211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1304654914
Short name T25
Test name
Test status
Simulation time 309479337 ps
CPU time 13.61 seconds
Started Oct 09 04:45:57 AM UTC 24
Finished Oct 09 04:46:11 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304654914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1304654914
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.3604693273
Short name T24
Test name
Test status
Simulation time 482437732 ps
CPU time 16.06 seconds
Started Oct 09 04:45:52 AM UTC 24
Finished Oct 09 04:46:09 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604693273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3604693273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1955787152
Short name T191
Test name
Test status
Simulation time 42899350204 ps
CPU time 118.11 seconds
Started Oct 09 04:45:53 AM UTC 24
Finished Oct 09 04:47:53 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955787152 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1955787152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1284152018
Short name T306
Test name
Test status
Simulation time 20241572834 ps
CPU time 144.6 seconds
Started Oct 09 04:45:53 AM UTC 24
Finished Oct 09 04:48:20 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284152018 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1284152018
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.4049897177
Short name T13
Test name
Test status
Simulation time 28633814 ps
CPU time 4.58 seconds
Started Oct 09 04:45:52 AM UTC 24
Finished Oct 09 04:45:57 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049897177 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4049897177
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.757225004
Short name T91
Test name
Test status
Simulation time 4316115737 ps
CPU time 42.99 seconds
Started Oct 09 04:45:55 AM UTC 24
Finished Oct 09 04:46:40 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757225004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.757225004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3249397415
Short name T8
Test name
Test status
Simulation time 160474561 ps
CPU time 4.59 seconds
Started Oct 09 04:45:51 AM UTC 24
Finished Oct 09 04:45:57 AM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249397415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3249397415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2111228291
Short name T87
Test name
Test status
Simulation time 8162118930 ps
CPU time 60.91 seconds
Started Oct 09 04:45:52 AM UTC 24
Finished Oct 09 04:46:54 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111228291 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2111228291
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1000937861
Short name T26
Test name
Test status
Simulation time 3759714763 ps
CPU time 35.86 seconds
Started Oct 09 04:45:52 AM UTC 24
Finished Oct 09 04:46:29 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000937861 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1000937861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3671383992
Short name T11
Test name
Test status
Simulation time 30099468 ps
CPU time 2.35 seconds
Started Oct 09 04:45:52 AM UTC 24
Finished Oct 09 04:45:55 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671383992 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3671383992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.2145765598
Short name T44
Test name
Test status
Simulation time 985500318 ps
CPU time 86.05 seconds
Started Oct 09 04:45:58 AM UTC 24
Finished Oct 09 04:47:26 AM UTC 24
Peak memory 217888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145765598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2145765598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2324989488
Short name T234
Test name
Test status
Simulation time 3232169719 ps
CPU time 169.56 seconds
Started Oct 09 04:46:01 AM UTC 24
Finished Oct 09 04:48:54 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324989488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2324989488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.416518251
Short name T229
Test name
Test status
Simulation time 2904995976 ps
CPU time 247.63 seconds
Started Oct 09 04:45:59 AM UTC 24
Finished Oct 09 04:50:11 AM UTC 24
Peak memory 220120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416518251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.416518251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3923428123
Short name T325
Test name
Test status
Simulation time 734207842 ps
CPU time 138.21 seconds
Started Oct 09 04:46:02 AM UTC 24
Finished Oct 09 04:48:23 AM UTC 24
Peak memory 219940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923428123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3923428123
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1529521685
Short name T40
Test name
Test status
Simulation time 1013080662 ps
CPU time 35.48 seconds
Started Oct 09 04:45:57 AM UTC 24
Finished Oct 09 04:46:34 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529521685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1529521685
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3458312211
Short name T309
Test name
Test status
Simulation time 1795524631 ps
CPU time 76.37 seconds
Started Oct 09 04:54:35 AM UTC 24
Finished Oct 09 04:55:54 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458312211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3458312211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.686137027
Short name T780
Test name
Test status
Simulation time 135496472936 ps
CPU time 719.95 seconds
Started Oct 09 04:54:41 AM UTC 24
Finished Oct 09 05:06:50 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686137027 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.686137027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2307985355
Short name T439
Test name
Test status
Simulation time 713786772 ps
CPU time 38.64 seconds
Started Oct 09 04:54:51 AM UTC 24
Finished Oct 09 04:55:32 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307985355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2307985355
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3396153262
Short name T430
Test name
Test status
Simulation time 972529662 ps
CPU time 19.98 seconds
Started Oct 09 04:54:49 AM UTC 24
Finished Oct 09 04:55:10 AM UTC 24
Peak memory 215748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396153262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3396153262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.2399374219
Short name T426
Test name
Test status
Simulation time 676492817 ps
CPU time 26.52 seconds
Started Oct 09 04:54:26 AM UTC 24
Finished Oct 09 04:54:54 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399374219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2399374219
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2986638657
Short name T481
Test name
Test status
Simulation time 17701132608 ps
CPU time 152 seconds
Started Oct 09 04:54:28 AM UTC 24
Finished Oct 09 04:57:03 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986638657 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2986638657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.994167914
Short name T143
Test name
Test status
Simulation time 29934346996 ps
CPU time 188.3 seconds
Started Oct 09 04:54:33 AM UTC 24
Finished Oct 09 04:57:44 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994167914 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.994167914
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2910021097
Short name T427
Test name
Test status
Simulation time 170641874 ps
CPU time 29.95 seconds
Started Oct 09 04:54:27 AM UTC 24
Finished Oct 09 04:54:59 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910021097 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2910021097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.226935798
Short name T424
Test name
Test status
Simulation time 406498246 ps
CPU time 10.27 seconds
Started Oct 09 04:54:41 AM UTC 24
Finished Oct 09 04:54:52 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226935798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.226935798
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.30347017
Short name T415
Test name
Test status
Simulation time 51040577 ps
CPU time 3.48 seconds
Started Oct 09 04:54:20 AM UTC 24
Finished Oct 09 04:54:24 AM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30347017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.30347017
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3155538366
Short name T433
Test name
Test status
Simulation time 14769957542 ps
CPU time 55.25 seconds
Started Oct 09 04:54:23 AM UTC 24
Finished Oct 09 04:55:21 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155538366 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3155538366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2536578286
Short name T64
Test name
Test status
Simulation time 3281813746 ps
CPU time 36.48 seconds
Started Oct 09 04:54:23 AM UTC 24
Finished Oct 09 04:55:02 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536578286 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2536578286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1207894720
Short name T416
Test name
Test status
Simulation time 22701277 ps
CPU time 3.17 seconds
Started Oct 09 04:54:21 AM UTC 24
Finished Oct 09 04:54:25 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207894720 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1207894720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2962667692
Short name T487
Test name
Test status
Simulation time 5763550282 ps
CPU time 139.72 seconds
Started Oct 09 04:54:53 AM UTC 24
Finished Oct 09 04:57:15 AM UTC 24
Peak memory 220192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962667692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2962667692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2897677939
Short name T435
Test name
Test status
Simulation time 166043430 ps
CPU time 32.57 seconds
Started Oct 09 04:54:54 AM UTC 24
Finished Oct 09 04:55:29 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897677939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2897677939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2270071464
Short name T443
Test name
Test status
Simulation time 35127962 ps
CPU time 41.98 seconds
Started Oct 09 04:54:54 AM UTC 24
Finished Oct 09 04:55:38 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270071464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2270071464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2781542616
Short name T572
Test name
Test status
Simulation time 889643825 ps
CPU time 315.42 seconds
Started Oct 09 04:54:56 AM UTC 24
Finished Oct 09 05:00:17 AM UTC 24
Peak memory 232700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781542616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2781542616
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3956223122
Short name T270
Test name
Test status
Simulation time 107349309 ps
CPU time 2.59 seconds
Started Oct 09 04:54:49 AM UTC 24
Finished Oct 09 04:54:53 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956223122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3956223122
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.30432548
Short name T445
Test name
Test status
Simulation time 184506784 ps
CPU time 29.78 seconds
Started Oct 09 04:55:08 AM UTC 24
Finished Oct 09 04:55:40 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30432548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.30432548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2158805196
Short name T545
Test name
Test status
Simulation time 25817397930 ps
CPU time 242.69 seconds
Started Oct 09 04:55:12 AM UTC 24
Finished Oct 09 04:59:18 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158805196 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2158805196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1275239153
Short name T436
Test name
Test status
Simulation time 214945880 ps
CPU time 6.74 seconds
Started Oct 09 04:55:21 AM UTC 24
Finished Oct 09 04:55:29 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275239153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1275239153
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2434310406
Short name T434
Test name
Test status
Simulation time 63160939 ps
CPU time 3.11 seconds
Started Oct 09 04:55:18 AM UTC 24
Finished Oct 09 04:55:23 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434310406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2434310406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3710841516
Short name T431
Test name
Test status
Simulation time 52434325 ps
CPU time 12.26 seconds
Started Oct 09 04:55:03 AM UTC 24
Finished Oct 09 04:55:17 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710841516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3710841516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2327719766
Short name T478
Test name
Test status
Simulation time 32525041194 ps
CPU time 110.61 seconds
Started Oct 09 04:55:05 AM UTC 24
Finished Oct 09 04:56:58 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327719766 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2327719766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1149296097
Short name T452
Test name
Test status
Simulation time 4099491910 ps
CPU time 46.13 seconds
Started Oct 09 04:55:06 AM UTC 24
Finished Oct 09 04:55:54 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149296097 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1149296097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.2844622946
Short name T432
Test name
Test status
Simulation time 98452448 ps
CPU time 12.41 seconds
Started Oct 09 04:55:05 AM UTC 24
Finished Oct 09 04:55:18 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844622946 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2844622946
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3051257712
Short name T446
Test name
Test status
Simulation time 1553173496 ps
CPU time 25.43 seconds
Started Oct 09 04:55:17 AM UTC 24
Finished Oct 09 04:55:44 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051257712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3051257712
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.1295680273
Short name T429
Test name
Test status
Simulation time 154674813 ps
CPU time 4.98 seconds
Started Oct 09 04:54:59 AM UTC 24
Finished Oct 09 04:55:05 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295680273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1295680273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1509572921
Short name T451
Test name
Test status
Simulation time 6913585116 ps
CPU time 51.05 seconds
Started Oct 09 04:55:00 AM UTC 24
Finished Oct 09 04:55:52 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509572921 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1509572921
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2661836837
Short name T65
Test name
Test status
Simulation time 3258507445 ps
CPU time 22.14 seconds
Started Oct 09 04:55:02 AM UTC 24
Finished Oct 09 04:55:25 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661836837 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2661836837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1568291910
Short name T428
Test name
Test status
Simulation time 44956435 ps
CPU time 3.27 seconds
Started Oct 09 04:54:59 AM UTC 24
Finished Oct 09 04:55:04 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568291910 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1568291910
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.1616993795
Short name T144
Test name
Test status
Simulation time 24385258983 ps
CPU time 246.42 seconds
Started Oct 09 04:55:22 AM UTC 24
Finished Oct 09 04:59:33 AM UTC 24
Peak memory 222040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616993795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1616993795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2115907189
Short name T247
Test name
Test status
Simulation time 1120023165 ps
CPU time 79.74 seconds
Started Oct 09 04:55:26 AM UTC 24
Finished Oct 09 04:56:48 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115907189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2115907189
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1560402860
Short name T228
Test name
Test status
Simulation time 1588380124 ps
CPU time 102.27 seconds
Started Oct 09 04:55:24 AM UTC 24
Finished Oct 09 04:57:08 AM UTC 24
Peak memory 220064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560402860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1560402860
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3072438284
Short name T579
Test name
Test status
Simulation time 1529988101 ps
CPU time 297.54 seconds
Started Oct 09 04:55:30 AM UTC 24
Finished Oct 09 05:00:33 AM UTC 24
Peak memory 232568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072438284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3072438284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.1955711647
Short name T444
Test name
Test status
Simulation time 504323984 ps
CPU time 18.3 seconds
Started Oct 09 04:55:20 AM UTC 24
Finished Oct 09 04:55:40 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955711647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1955711647
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3859663420
Short name T467
Test name
Test status
Simulation time 233596751 ps
CPU time 49.37 seconds
Started Oct 09 04:55:40 AM UTC 24
Finished Oct 09 04:56:31 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859663420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3859663420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.485398541
Short name T547
Test name
Test status
Simulation time 26450064109 ps
CPU time 218.11 seconds
Started Oct 09 04:55:41 AM UTC 24
Finished Oct 09 04:59:23 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485398541 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.485398541
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1746939968
Short name T165
Test name
Test status
Simulation time 215710969 ps
CPU time 10.44 seconds
Started Oct 09 04:55:46 AM UTC 24
Finished Oct 09 04:55:57 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746939968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1746939968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2508163751
Short name T457
Test name
Test status
Simulation time 368825856 ps
CPU time 28.5 seconds
Started Oct 09 04:55:44 AM UTC 24
Finished Oct 09 04:56:14 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508163751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2508163751
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3231854585
Short name T448
Test name
Test status
Simulation time 42450671 ps
CPU time 8.5 seconds
Started Oct 09 04:55:35 AM UTC 24
Finished Oct 09 04:55:45 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231854585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3231854585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2223029267
Short name T503
Test name
Test status
Simulation time 22183962283 ps
CPU time 137.78 seconds
Started Oct 09 04:55:37 AM UTC 24
Finished Oct 09 04:57:57 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223029267 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2223029267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4038519598
Short name T570
Test name
Test status
Simulation time 69899204634 ps
CPU time 271.78 seconds
Started Oct 09 04:55:38 AM UTC 24
Finished Oct 09 05:00:14 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038519598 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4038519598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.714049750
Short name T455
Test name
Test status
Simulation time 142113115 ps
CPU time 33.73 seconds
Started Oct 09 04:55:37 AM UTC 24
Finished Oct 09 04:56:12 AM UTC 24
Peak memory 217864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714049750 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.714049750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.1791061901
Short name T172
Test name
Test status
Simulation time 1034650215 ps
CPU time 27.15 seconds
Started Oct 09 04:55:41 AM UTC 24
Finished Oct 09 04:56:10 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791061901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1791061901
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.114971226
Short name T441
Test name
Test status
Simulation time 143697115 ps
CPU time 4.29 seconds
Started Oct 09 04:55:30 AM UTC 24
Finished Oct 09 04:55:36 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114971226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.114971226
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1291029733
Short name T465
Test name
Test status
Simulation time 5095036064 ps
CPU time 55.94 seconds
Started Oct 09 04:55:32 AM UTC 24
Finished Oct 09 04:56:29 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291029733 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1291029733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3134450799
Short name T458
Test name
Test status
Simulation time 3006665955 ps
CPU time 42.44 seconds
Started Oct 09 04:55:33 AM UTC 24
Finished Oct 09 04:56:17 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134450799 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3134450799
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3084205158
Short name T440
Test name
Test status
Simulation time 35034870 ps
CPU time 3.75 seconds
Started Oct 09 04:55:30 AM UTC 24
Finished Oct 09 04:55:35 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084205158 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3084205158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1718108869
Short name T456
Test name
Test status
Simulation time 123202850 ps
CPU time 24.51 seconds
Started Oct 09 04:55:47 AM UTC 24
Finished Oct 09 04:56:13 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718108869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1718108869
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.721919376
Short name T476
Test name
Test status
Simulation time 1958356022 ps
CPU time 65.58 seconds
Started Oct 09 04:55:48 AM UTC 24
Finished Oct 09 04:56:56 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721919376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.721919376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1747770902
Short name T469
Test name
Test status
Simulation time 116956270 ps
CPU time 43.66 seconds
Started Oct 09 04:55:47 AM UTC 24
Finished Oct 09 04:56:32 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747770902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1747770902
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.33211320
Short name T292
Test name
Test status
Simulation time 1589706209 ps
CPU time 297.92 seconds
Started Oct 09 04:55:50 AM UTC 24
Finished Oct 09 05:00:52 AM UTC 24
Peak memory 232632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33211320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.33211320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3222981469
Short name T454
Test name
Test status
Simulation time 559971165 ps
CPU time 23.63 seconds
Started Oct 09 04:55:45 AM UTC 24
Finished Oct 09 04:56:10 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222981469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3222981469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1821967974
Short name T462
Test name
Test status
Simulation time 91955019 ps
CPU time 19.51 seconds
Started Oct 09 04:56:00 AM UTC 24
Finished Oct 09 04:56:21 AM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821967974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1821967974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3704351254
Short name T546
Test name
Test status
Simulation time 18504077274 ps
CPU time 195.55 seconds
Started Oct 09 04:56:02 AM UTC 24
Finished Oct 09 04:59:21 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704351254 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3704351254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3025547429
Short name T468
Test name
Test status
Simulation time 103241049 ps
CPU time 19.35 seconds
Started Oct 09 04:56:12 AM UTC 24
Finished Oct 09 04:56:32 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025547429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3025547429
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3818463722
Short name T171
Test name
Test status
Simulation time 102856283 ps
CPU time 5.3 seconds
Started Oct 09 04:56:03 AM UTC 24
Finished Oct 09 04:56:10 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818463722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3818463722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.146589763
Short name T170
Test name
Test status
Simulation time 119157483 ps
CPU time 4.63 seconds
Started Oct 09 04:55:56 AM UTC 24
Finished Oct 09 04:56:02 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146589763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.146589763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.3913487345
Short name T493
Test name
Test status
Simulation time 15335761919 ps
CPU time 84.61 seconds
Started Oct 09 04:55:58 AM UTC 24
Finished Oct 09 04:57:25 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913487345 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3913487345
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.483641166
Short name T587
Test name
Test status
Simulation time 26779260731 ps
CPU time 278.49 seconds
Started Oct 09 04:56:00 AM UTC 24
Finished Oct 09 05:00:43 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483641166 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.483641166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.3926125940
Short name T460
Test name
Test status
Simulation time 104570031 ps
CPU time 21.09 seconds
Started Oct 09 04:55:57 AM UTC 24
Finished Oct 09 04:56:20 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926125940 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3926125940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1760447096
Short name T464
Test name
Test status
Simulation time 750712142 ps
CPU time 19.57 seconds
Started Oct 09 04:56:02 AM UTC 24
Finished Oct 09 04:56:23 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760447096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1760447096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.728589109
Short name T166
Test name
Test status
Simulation time 451850345 ps
CPU time 5.89 seconds
Started Oct 09 04:55:51 AM UTC 24
Finished Oct 09 04:55:58 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728589109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.728589109
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.157659283
Short name T472
Test name
Test status
Simulation time 8075440066 ps
CPU time 40.47 seconds
Started Oct 09 04:55:56 AM UTC 24
Finished Oct 09 04:56:38 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157659283 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.157659283
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1614307017
Short name T466
Test name
Test status
Simulation time 4639122925 ps
CPU time 33.17 seconds
Started Oct 09 04:55:56 AM UTC 24
Finished Oct 09 04:56:30 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614307017 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1614307017
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4080691006
Short name T167
Test name
Test status
Simulation time 32474608 ps
CPU time 3.89 seconds
Started Oct 09 04:55:53 AM UTC 24
Finished Oct 09 04:55:58 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080691006 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4080691006
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.804491778
Short name T573
Test name
Test status
Simulation time 1849671729 ps
CPU time 243.7 seconds
Started Oct 09 04:56:12 AM UTC 24
Finished Oct 09 05:00:19 AM UTC 24
Peak memory 221976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804491778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.804491778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.996291952
Short name T282
Test name
Test status
Simulation time 2384112525 ps
CPU time 82.64 seconds
Started Oct 09 04:56:13 AM UTC 24
Finished Oct 09 04:57:38 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996291952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.996291952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3898451362
Short name T43
Test name
Test status
Simulation time 1474117151 ps
CPU time 444.5 seconds
Started Oct 09 04:56:12 AM UTC 24
Finished Oct 09 05:03:43 AM UTC 24
Peak memory 219936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898451362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3898451362
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1252151733
Short name T578
Test name
Test status
Simulation time 1527561457 ps
CPU time 247.63 seconds
Started Oct 09 04:56:14 AM UTC 24
Finished Oct 09 05:00:26 AM UTC 24
Peak memory 232696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252151733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1252151733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1762955912
Short name T470
Test name
Test status
Simulation time 203096267 ps
CPU time 23.61 seconds
Started Oct 09 04:56:10 AM UTC 24
Finished Oct 09 04:56:35 AM UTC 24
Peak memory 217872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762955912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1762955912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1669647337
Short name T227
Test name
Test status
Simulation time 338547844 ps
CPU time 34.23 seconds
Started Oct 09 04:56:24 AM UTC 24
Finished Oct 09 04:57:00 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669647337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1669647337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3543208741
Short name T291
Test name
Test status
Simulation time 27150339962 ps
CPU time 257.9 seconds
Started Oct 09 04:56:31 AM UTC 24
Finished Oct 09 05:00:52 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543208741 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3543208741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2904746542
Short name T249
Test name
Test status
Simulation time 419368998 ps
CPU time 14.89 seconds
Started Oct 09 04:56:36 AM UTC 24
Finished Oct 09 04:56:52 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904746542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2904746542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3420808036
Short name T244
Test name
Test status
Simulation time 80625487 ps
CPU time 10.4 seconds
Started Oct 09 04:56:34 AM UTC 24
Finished Oct 09 04:56:45 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420808036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3420808036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.864560747
Short name T243
Test name
Test status
Simulation time 624516345 ps
CPU time 20.72 seconds
Started Oct 09 04:56:22 AM UTC 24
Finished Oct 09 04:56:44 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864560747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.864560747
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.2582746453
Short name T534
Test name
Test status
Simulation time 58924909384 ps
CPU time 153.6 seconds
Started Oct 09 04:56:23 AM UTC 24
Finished Oct 09 04:58:59 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582746453 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2582746453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3423922415
Short name T488
Test name
Test status
Simulation time 4911823919 ps
CPU time 50.11 seconds
Started Oct 09 04:56:24 AM UTC 24
Finished Oct 09 04:57:16 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423922415 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3423922415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.4047067247
Short name T242
Test name
Test status
Simulation time 128656530 ps
CPU time 20.48 seconds
Started Oct 09 04:56:22 AM UTC 24
Finished Oct 09 04:56:44 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047067247 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.4047067247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1475969913
Short name T475
Test name
Test status
Simulation time 317499743 ps
CPU time 19.64 seconds
Started Oct 09 04:56:34 AM UTC 24
Finished Oct 09 04:56:54 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475969913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1475969913
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3211742158
Short name T461
Test name
Test status
Simulation time 182051640 ps
CPU time 4.71 seconds
Started Oct 09 04:56:15 AM UTC 24
Finished Oct 09 04:56:21 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211742158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3211742158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2519725222
Short name T490
Test name
Test status
Simulation time 34052239227 ps
CPU time 56.85 seconds
Started Oct 09 04:56:20 AM UTC 24
Finished Oct 09 04:57:18 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519725222 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2519725222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2917702005
Short name T66
Test name
Test status
Simulation time 3271087346 ps
CPU time 46.26 seconds
Started Oct 09 04:56:22 AM UTC 24
Finished Oct 09 04:57:10 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917702005 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2917702005
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.441372400
Short name T463
Test name
Test status
Simulation time 34452901 ps
CPU time 2.79 seconds
Started Oct 09 04:56:18 AM UTC 24
Finished Oct 09 04:56:22 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441372400 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.441372400
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.4044027703
Short name T568
Test name
Test status
Simulation time 5927482195 ps
CPU time 211.1 seconds
Started Oct 09 04:56:38 AM UTC 24
Finished Oct 09 05:00:13 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044027703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4044027703
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3379816521
Short name T583
Test name
Test status
Simulation time 11727896355 ps
CPU time 233.44 seconds
Started Oct 09 04:56:41 AM UTC 24
Finished Oct 09 05:00:39 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379816521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3379816521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4117515512
Short name T150
Test name
Test status
Simulation time 8368113116 ps
CPU time 359.83 seconds
Started Oct 09 04:56:38 AM UTC 24
Finished Oct 09 05:02:43 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117515512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.4117515512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.441567507
Short name T532
Test name
Test status
Simulation time 300242266 ps
CPU time 130.2 seconds
Started Oct 09 04:56:41 AM UTC 24
Finished Oct 09 04:58:54 AM UTC 24
Peak memory 222104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441567507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.441567507
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.3643029754
Short name T483
Test name
Test status
Simulation time 672553529 ps
CPU time 35.14 seconds
Started Oct 09 04:56:36 AM UTC 24
Finished Oct 09 04:57:12 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643029754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3643029754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3998043457
Short name T479
Test name
Test status
Simulation time 31021192 ps
CPU time 6.72 seconds
Started Oct 09 04:56:52 AM UTC 24
Finished Oct 09 04:57:00 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998043457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3998043457
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2621007675
Short name T849
Test name
Test status
Simulation time 64331189043 ps
CPU time 714.73 seconds
Started Oct 09 04:56:54 AM UTC 24
Finished Oct 09 05:08:58 AM UTC 24
Peak memory 219532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621007675 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2621007675
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1367848287
Short name T499
Test name
Test status
Simulation time 3859412996 ps
CPU time 34.6 seconds
Started Oct 09 04:57:00 AM UTC 24
Finished Oct 09 04:57:36 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367848287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1367848287
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2226732877
Short name T492
Test name
Test status
Simulation time 694756383 ps
CPU time 25.13 seconds
Started Oct 09 04:56:57 AM UTC 24
Finished Oct 09 04:57:23 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226732877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2226732877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.1442773892
Short name T281
Test name
Test status
Simulation time 1066473105 ps
CPU time 45.97 seconds
Started Oct 09 04:56:49 AM UTC 24
Finished Oct 09 04:57:37 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442773892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1442773892
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.3220025296
Short name T627
Test name
Test status
Simulation time 132459883440 ps
CPU time 317.22 seconds
Started Oct 09 04:56:49 AM UTC 24
Finished Oct 09 05:02:11 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220025296 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3220025296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2574874426
Short name T515
Test name
Test status
Simulation time 8918004751 ps
CPU time 80.1 seconds
Started Oct 09 04:56:52 AM UTC 24
Finished Oct 09 04:58:14 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574874426 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2574874426
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3496563421
Short name T477
Test name
Test status
Simulation time 109169607 ps
CPU time 7.3 seconds
Started Oct 09 04:56:49 AM UTC 24
Finished Oct 09 04:56:57 AM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496563421 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3496563421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.3620158986
Short name T485
Test name
Test status
Simulation time 188631549 ps
CPU time 14.95 seconds
Started Oct 09 04:56:57 AM UTC 24
Finished Oct 09 04:57:13 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620158986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3620158986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2539070072
Short name T246
Test name
Test status
Simulation time 38269555 ps
CPU time 3.81 seconds
Started Oct 09 04:56:41 AM UTC 24
Finished Oct 09 04:56:46 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539070072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2539070072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3516905523
Short name T495
Test name
Test status
Simulation time 10164733472 ps
CPU time 41.72 seconds
Started Oct 09 04:56:46 AM UTC 24
Finished Oct 09 04:57:29 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516905523 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3516905523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.253141141
Short name T501
Test name
Test status
Simulation time 13985800934 ps
CPU time 67.36 seconds
Started Oct 09 04:56:46 AM UTC 24
Finished Oct 09 04:57:55 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253141141 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.253141141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.4130418161
Short name T248
Test name
Test status
Simulation time 32800931 ps
CPU time 3.66 seconds
Started Oct 09 04:56:46 AM UTC 24
Finished Oct 09 04:56:51 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130418161 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4130418161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.615723144
Short name T543
Test name
Test status
Simulation time 1285302928 ps
CPU time 129.35 seconds
Started Oct 09 04:57:00 AM UTC 24
Finished Oct 09 04:59:12 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615723144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.615723144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2247478911
Short name T559
Test name
Test status
Simulation time 4083027896 ps
CPU time 153.08 seconds
Started Oct 09 04:57:02 AM UTC 24
Finished Oct 09 04:59:38 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247478911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2247478911
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.585109583
Short name T533
Test name
Test status
Simulation time 122784445 ps
CPU time 110.06 seconds
Started Oct 09 04:57:02 AM UTC 24
Finished Oct 09 04:58:55 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585109583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.585109583
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2162239944
Short name T494
Test name
Test status
Simulation time 95432102 ps
CPU time 22.37 seconds
Started Oct 09 04:57:03 AM UTC 24
Finished Oct 09 04:57:26 AM UTC 24
Peak memory 217888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162239944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.2162239944
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.935225631
Short name T489
Test name
Test status
Simulation time 446416024 ps
CPU time 19.32 seconds
Started Oct 09 04:56:57 AM UTC 24
Finished Oct 09 04:57:18 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935225631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.935225631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.4216334810
Short name T203
Test name
Test status
Simulation time 1338281590 ps
CPU time 18.15 seconds
Started Oct 09 04:57:17 AM UTC 24
Finished Oct 09 04:57:36 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216334810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4216334810
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3457652877
Short name T178
Test name
Test status
Simulation time 107613961310 ps
CPU time 745.17 seconds
Started Oct 09 04:57:17 AM UTC 24
Finished Oct 09 05:09:52 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457652877 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3457652877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3896945446
Short name T286
Test name
Test status
Simulation time 284849526 ps
CPU time 18.5 seconds
Started Oct 09 04:57:22 AM UTC 24
Finished Oct 09 04:57:42 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896945446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3896945446
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1287799680
Short name T500
Test name
Test status
Simulation time 1245663826 ps
CPU time 29.42 seconds
Started Oct 09 04:57:19 AM UTC 24
Finished Oct 09 04:57:50 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287799680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1287799680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3681619599
Short name T511
Test name
Test status
Simulation time 1648972928 ps
CPU time 48.4 seconds
Started Oct 09 04:57:14 AM UTC 24
Finished Oct 09 04:58:04 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681619599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3681619599
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1208731614
Short name T530
Test name
Test status
Simulation time 20459266896 ps
CPU time 85.34 seconds
Started Oct 09 04:57:14 AM UTC 24
Finished Oct 09 04:58:42 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208731614 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1208731614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1409417734
Short name T498
Test name
Test status
Simulation time 1480455466 ps
CPU time 18.28 seconds
Started Oct 09 04:57:14 AM UTC 24
Finished Oct 09 04:57:34 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409417734 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1409417734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1991827476
Short name T285
Test name
Test status
Simulation time 149155019 ps
CPU time 24.5 seconds
Started Oct 09 04:57:14 AM UTC 24
Finished Oct 09 04:57:40 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991827476 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1991827476
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.1610788128
Short name T496
Test name
Test status
Simulation time 189439228 ps
CPU time 13.08 seconds
Started Oct 09 04:57:17 AM UTC 24
Finished Oct 09 04:57:31 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610788128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1610788128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.76105187
Short name T484
Test name
Test status
Simulation time 142898032 ps
CPU time 6.06 seconds
Started Oct 09 04:57:05 AM UTC 24
Finished Oct 09 04:57:12 AM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76105187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.76105187
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2611758245
Short name T518
Test name
Test status
Simulation time 8350059576 ps
CPU time 61.24 seconds
Started Oct 09 04:57:12 AM UTC 24
Finished Oct 09 04:58:15 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611758245 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2611758245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1969996591
Short name T502
Test name
Test status
Simulation time 3788128451 ps
CPU time 41.4 seconds
Started Oct 09 04:57:14 AM UTC 24
Finished Oct 09 04:57:57 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969996591 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1969996591
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2419738247
Short name T486
Test name
Test status
Simulation time 32060236 ps
CPU time 4.14 seconds
Started Oct 09 04:57:09 AM UTC 24
Finished Oct 09 04:57:15 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419738247 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2419738247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3704508898
Short name T514
Test name
Test status
Simulation time 927102644 ps
CPU time 44.71 seconds
Started Oct 09 04:57:24 AM UTC 24
Finished Oct 09 04:58:11 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704508898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3704508898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3744031618
Short name T575
Test name
Test status
Simulation time 2227149778 ps
CPU time 168.71 seconds
Started Oct 09 04:57:29 AM UTC 24
Finished Oct 09 05:00:21 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744031618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3744031618
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3320141804
Short name T264
Test name
Test status
Simulation time 626062577 ps
CPU time 310.47 seconds
Started Oct 09 04:57:26 AM UTC 24
Finished Oct 09 05:02:42 AM UTC 24
Peak memory 219936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320141804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3320141804
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2575810576
Short name T641
Test name
Test status
Simulation time 1077881337 ps
CPU time 296.44 seconds
Started Oct 09 04:57:31 AM UTC 24
Finished Oct 09 05:02:33 AM UTC 24
Peak memory 222332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575810576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2575810576
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.482054813
Short name T497
Test name
Test status
Simulation time 277465447 ps
CPU time 10.68 seconds
Started Oct 09 04:57:22 AM UTC 24
Finished Oct 09 04:57:34 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482054813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.482054813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.449776928
Short name T521
Test name
Test status
Simulation time 2322898146 ps
CPU time 39.66 seconds
Started Oct 09 04:57:39 AM UTC 24
Finished Oct 09 04:58:20 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449776928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.449776928
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3160647625
Short name T614
Test name
Test status
Simulation time 20685049424 ps
CPU time 240.44 seconds
Started Oct 09 04:57:42 AM UTC 24
Finished Oct 09 05:01:46 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160647625 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3160647625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3731111783
Short name T519
Test name
Test status
Simulation time 1169058462 ps
CPU time 31.61 seconds
Started Oct 09 04:57:44 AM UTC 24
Finished Oct 09 04:58:17 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731111783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3731111783
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2592765320
Short name T506
Test name
Test status
Simulation time 1310318311 ps
CPU time 18.95 seconds
Started Oct 09 04:57:42 AM UTC 24
Finished Oct 09 04:58:02 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592765320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2592765320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3346819049
Short name T504
Test name
Test status
Simulation time 152880085 ps
CPU time 19.83 seconds
Started Oct 09 04:57:37 AM UTC 24
Finished Oct 09 04:57:58 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346819049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3346819049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1034183756
Short name T595
Test name
Test status
Simulation time 76247816967 ps
CPU time 207.15 seconds
Started Oct 09 04:57:39 AM UTC 24
Finished Oct 09 05:01:09 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034183756 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1034183756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.551681822
Short name T68
Test name
Test status
Simulation time 20316529877 ps
CPU time 129.72 seconds
Started Oct 09 04:57:39 AM UTC 24
Finished Oct 09 04:59:51 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551681822 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.551681822
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.3974181655
Short name T505
Test name
Test status
Simulation time 174401319 ps
CPU time 21.07 seconds
Started Oct 09 04:57:37 AM UTC 24
Finished Oct 09 04:57:59 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974181655 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3974181655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1553281563
Short name T508
Test name
Test status
Simulation time 206126365 ps
CPU time 20.4 seconds
Started Oct 09 04:57:42 AM UTC 24
Finished Oct 09 04:58:03 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553281563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1553281563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.2712044655
Short name T283
Test name
Test status
Simulation time 147612903 ps
CPU time 5.45 seconds
Started Oct 09 04:57:33 AM UTC 24
Finished Oct 09 04:57:40 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712044655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2712044655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3672010994
Short name T517
Test name
Test status
Simulation time 6779991678 ps
CPU time 37.45 seconds
Started Oct 09 04:57:36 AM UTC 24
Finished Oct 09 04:58:15 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672010994 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3672010994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3491177474
Short name T513
Test name
Test status
Simulation time 4640321766 ps
CPU time 26.85 seconds
Started Oct 09 04:57:37 AM UTC 24
Finished Oct 09 04:58:05 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491177474 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3491177474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.4137271047
Short name T284
Test name
Test status
Simulation time 43032817 ps
CPU time 3.45 seconds
Started Oct 09 04:57:35 AM UTC 24
Finished Oct 09 04:57:40 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137271047 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4137271047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2983020755
Short name T146
Test name
Test status
Simulation time 4898288281 ps
CPU time 157.95 seconds
Started Oct 09 04:57:44 AM UTC 24
Finished Oct 09 05:00:25 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983020755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2983020755
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3659332201
Short name T662
Test name
Test status
Simulation time 10249820435 ps
CPU time 318.72 seconds
Started Oct 09 04:57:51 AM UTC 24
Finished Oct 09 05:03:14 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659332201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3659332201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3181897659
Short name T537
Test name
Test status
Simulation time 278695997 ps
CPU time 76.08 seconds
Started Oct 09 04:57:46 AM UTC 24
Finished Oct 09 04:59:04 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181897659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3181897659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3660641291
Short name T648
Test name
Test status
Simulation time 954931619 ps
CPU time 285.82 seconds
Started Oct 09 04:57:56 AM UTC 24
Finished Oct 09 05:02:47 AM UTC 24
Peak memory 221988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660641291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3660641291
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.4250575154
Short name T512
Test name
Test status
Simulation time 153927730 ps
CPU time 19.07 seconds
Started Oct 09 04:57:44 AM UTC 24
Finished Oct 09 04:58:05 AM UTC 24
Peak memory 217744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250575154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4250575154
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.215899389
Short name T527
Test name
Test status
Simulation time 683882906 ps
CPU time 30.01 seconds
Started Oct 09 04:58:07 AM UTC 24
Finished Oct 09 04:58:38 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215899389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.215899389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1585305546
Short name T898
Test name
Test status
Simulation time 182544353628 ps
CPU time 993.75 seconds
Started Oct 09 04:58:07 AM UTC 24
Finished Oct 09 05:14:53 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585305546 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1585305546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1481912762
Short name T525
Test name
Test status
Simulation time 448306341 ps
CPU time 20.79 seconds
Started Oct 09 04:58:13 AM UTC 24
Finished Oct 09 04:58:35 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481912762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1481912762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3669287958
Short name T528
Test name
Test status
Simulation time 238432849 ps
CPU time 30.37 seconds
Started Oct 09 04:58:07 AM UTC 24
Finished Oct 09 04:58:39 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669287958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3669287958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.3755606415
Short name T241
Test name
Test status
Simulation time 2361097770 ps
CPU time 34.65 seconds
Started Oct 09 04:58:02 AM UTC 24
Finished Oct 09 04:58:39 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755606415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3755606415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.939431055
Short name T637
Test name
Test status
Simulation time 30559618280 ps
CPU time 258.69 seconds
Started Oct 09 04:58:04 AM UTC 24
Finished Oct 09 05:02:27 AM UTC 24
Peak memory 218072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939431055 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.939431055
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2085917277
Short name T276
Test name
Test status
Simulation time 33437219713 ps
CPU time 174.68 seconds
Started Oct 09 04:58:06 AM UTC 24
Finished Oct 09 05:01:04 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085917277 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2085917277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2373095970
Short name T524
Test name
Test status
Simulation time 145378812 ps
CPU time 27.26 seconds
Started Oct 09 04:58:04 AM UTC 24
Finished Oct 09 04:58:33 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373095970 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2373095970
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2228005204
Short name T520
Test name
Test status
Simulation time 290679572 ps
CPU time 10.81 seconds
Started Oct 09 04:58:07 AM UTC 24
Finished Oct 09 04:58:19 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228005204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2228005204
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.621835917
Short name T510
Test name
Test status
Simulation time 120746877 ps
CPU time 4.47 seconds
Started Oct 09 04:57:59 AM UTC 24
Finished Oct 09 04:58:04 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621835917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.621835917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.34748318
Short name T529
Test name
Test status
Simulation time 3293368503 ps
CPU time 38.64 seconds
Started Oct 09 04:57:59 AM UTC 24
Finished Oct 09 04:58:39 AM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34748318 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.34748318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1796155963
Short name T185
Test name
Test status
Simulation time 3039592301 ps
CPU time 29.06 seconds
Started Oct 09 04:58:00 AM UTC 24
Finished Oct 09 04:58:31 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796155963 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1796155963
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2210643327
Short name T509
Test name
Test status
Simulation time 33491819 ps
CPU time 4.06 seconds
Started Oct 09 04:57:59 AM UTC 24
Finished Oct 09 04:58:04 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210643327 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2210643327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.2924448993
Short name T175
Test name
Test status
Simulation time 7020421948 ps
CPU time 281.17 seconds
Started Oct 09 04:58:15 AM UTC 24
Finished Oct 09 05:03:01 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924448993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2924448993
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.853525095
Short name T542
Test name
Test status
Simulation time 817237938 ps
CPU time 52.74 seconds
Started Oct 09 04:58:16 AM UTC 24
Finished Oct 09 04:59:11 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853525095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.853525095
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4032564134
Short name T47
Test name
Test status
Simulation time 384648320 ps
CPU time 145.62 seconds
Started Oct 09 04:58:16 AM UTC 24
Finished Oct 09 05:00:45 AM UTC 24
Peak memory 219936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032564134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.4032564134
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1164994588
Short name T42
Test name
Test status
Simulation time 2310651688 ps
CPU time 304.56 seconds
Started Oct 09 04:58:19 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164994588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1164994588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.139642900
Short name T526
Test name
Test status
Simulation time 138908406 ps
CPU time 26.76 seconds
Started Oct 09 04:58:08 AM UTC 24
Finished Oct 09 04:58:36 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139642900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.139642900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1189045580
Short name T145
Test name
Test status
Simulation time 6618657730 ps
CPU time 87.3 seconds
Started Oct 09 04:58:37 AM UTC 24
Finished Oct 09 05:00:07 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189045580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1189045580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1658009101
Short name T301
Test name
Test status
Simulation time 16241936545 ps
CPU time 58.05 seconds
Started Oct 09 04:58:39 AM UTC 24
Finished Oct 09 04:59:38 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658009101 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1658009101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1566447634
Short name T541
Test name
Test status
Simulation time 1289718138 ps
CPU time 24.8 seconds
Started Oct 09 04:58:44 AM UTC 24
Finished Oct 09 04:59:10 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566447634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1566447634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.460763717
Short name T535
Test name
Test status
Simulation time 264644460 ps
CPU time 19.22 seconds
Started Oct 09 04:58:41 AM UTC 24
Finished Oct 09 04:59:02 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460763717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.460763717
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.7874213
Short name T516
Test name
Test status
Simulation time 404656865 ps
CPU time 25.72 seconds
Started Oct 09 04:58:32 AM UTC 24
Finished Oct 09 04:58:59 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7874213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T
EST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.7874213
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3046020810
Short name T73
Test name
Test status
Simulation time 49515920057 ps
CPU time 292.37 seconds
Started Oct 09 04:58:34 AM UTC 24
Finished Oct 09 05:03:31 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046020810 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3046020810
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.377028119
Short name T152
Test name
Test status
Simulation time 30937283368 ps
CPU time 286.99 seconds
Started Oct 09 04:58:36 AM UTC 24
Finished Oct 09 05:03:27 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377028119 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.377028119
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.4169542482
Short name T531
Test name
Test status
Simulation time 87675671 ps
CPU time 15.15 seconds
Started Oct 09 04:58:34 AM UTC 24
Finished Oct 09 04:58:51 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169542482 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4169542482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1099275481
Short name T536
Test name
Test status
Simulation time 554278694 ps
CPU time 20.57 seconds
Started Oct 09 04:58:41 AM UTC 24
Finished Oct 09 04:59:03 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099275481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1099275481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.498681766
Short name T523
Test name
Test status
Simulation time 427041039 ps
CPU time 5.43 seconds
Started Oct 09 04:58:20 AM UTC 24
Finished Oct 09 04:58:27 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498681766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.498681766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2327537428
Short name T549
Test name
Test status
Simulation time 9029576065 ps
CPU time 56.5 seconds
Started Oct 09 04:58:27 AM UTC 24
Finished Oct 09 04:59:25 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327537428 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2327537428
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.530246501
Short name T540
Test name
Test status
Simulation time 5466874397 ps
CPU time 36.71 seconds
Started Oct 09 04:58:28 AM UTC 24
Finished Oct 09 04:59:07 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530246501 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.530246501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.922082930
Short name T522
Test name
Test status
Simulation time 29051550 ps
CPU time 3.03 seconds
Started Oct 09 04:58:22 AM UTC 24
Finished Oct 09 04:58:26 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922082930 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.922082930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.4099814475
Short name T620
Test name
Test status
Simulation time 2228655183 ps
CPU time 188.01 seconds
Started Oct 09 04:58:52 AM UTC 24
Finished Oct 09 05:02:03 AM UTC 24
Peak memory 220060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099814475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4099814475
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2938165196
Short name T619
Test name
Test status
Simulation time 1266211243 ps
CPU time 182.65 seconds
Started Oct 09 04:58:56 AM UTC 24
Finished Oct 09 05:02:02 AM UTC 24
Peak memory 222176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938165196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2938165196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3578998390
Short name T693
Test name
Test status
Simulation time 714620961 ps
CPU time 308.67 seconds
Started Oct 09 04:58:56 AM UTC 24
Finished Oct 09 05:04:09 AM UTC 24
Peak memory 219936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578998390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.3578998390
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3323549535
Short name T633
Test name
Test status
Simulation time 2536846764 ps
CPU time 196.91 seconds
Started Oct 09 04:59:00 AM UTC 24
Finished Oct 09 05:02:20 AM UTC 24
Peak memory 222180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323549535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3323549535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2159748817
Short name T544
Test name
Test status
Simulation time 2077085050 ps
CPU time 30.04 seconds
Started Oct 09 04:58:41 AM UTC 24
Finished Oct 09 04:59:13 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159748817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2159748817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.1681222556
Short name T76
Test name
Test status
Simulation time 193892620 ps
CPU time 9.29 seconds
Started Oct 09 04:46:14 AM UTC 24
Finished Oct 09 04:46:25 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681222556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1681222556
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3988623836
Short name T215
Test name
Test status
Simulation time 716672583 ps
CPU time 16.65 seconds
Started Oct 09 04:46:21 AM UTC 24
Finished Oct 09 04:46:39 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988623836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3988623836
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.3722059593
Short name T78
Test name
Test status
Simulation time 90867976 ps
CPU time 5.09 seconds
Started Oct 09 04:46:19 AM UTC 24
Finished Oct 09 04:46:25 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722059593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3722059593
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.515449299
Short name T82
Test name
Test status
Simulation time 1633302329 ps
CPU time 36.8 seconds
Started Oct 09 04:46:11 AM UTC 24
Finished Oct 09 04:46:49 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515449299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.515449299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1268400252
Short name T110
Test name
Test status
Simulation time 17379956648 ps
CPU time 112.29 seconds
Started Oct 09 04:46:14 AM UTC 24
Finished Oct 09 04:48:09 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268400252 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1268400252
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2835644824
Short name T299
Test name
Test status
Simulation time 101515384730 ps
CPU time 230.9 seconds
Started Oct 09 04:46:14 AM UTC 24
Finished Oct 09 04:50:09 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835644824 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2835644824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3510718697
Short name T21
Test name
Test status
Simulation time 67032483 ps
CPU time 12.43 seconds
Started Oct 09 04:46:12 AM UTC 24
Finished Oct 09 04:46:25 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510718697 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3510718697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.836743815
Short name T80
Test name
Test status
Simulation time 1420534821 ps
CPU time 24.28 seconds
Started Oct 09 04:46:19 AM UTC 24
Finished Oct 09 04:46:45 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836743815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.836743815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3068489419
Short name T23
Test name
Test status
Simulation time 32368119 ps
CPU time 4.67 seconds
Started Oct 09 04:46:04 AM UTC 24
Finished Oct 09 04:46:10 AM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068489419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3068489419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3939973143
Short name T81
Test name
Test status
Simulation time 5806424889 ps
CPU time 34.95 seconds
Started Oct 09 04:46:11 AM UTC 24
Finished Oct 09 04:46:47 AM UTC 24
Peak memory 216076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939973143 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3939973143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3807909985
Short name T75
Test name
Test status
Simulation time 32729555 ps
CPU time 3.25 seconds
Started Oct 09 04:46:08 AM UTC 24
Finished Oct 09 04:46:13 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807909985 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3807909985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3314135964
Short name T6
Test name
Test status
Simulation time 1091562801 ps
CPU time 176.95 seconds
Started Oct 09 04:46:25 AM UTC 24
Finished Oct 09 04:49:25 AM UTC 24
Peak memory 222320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314135964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3314135964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3706439588
Short name T45
Test name
Test status
Simulation time 27414956655 ps
CPU time 154.44 seconds
Started Oct 09 04:46:27 AM UTC 24
Finished Oct 09 04:49:04 AM UTC 24
Peak memory 220132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706439588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3706439588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3057612580
Short name T33
Test name
Test status
Simulation time 883332647 ps
CPU time 344.48 seconds
Started Oct 09 04:46:25 AM UTC 24
Finished Oct 09 04:52:15 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057612580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3057612580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3164355388
Short name T197
Test name
Test status
Simulation time 9216462826 ps
CPU time 275.1 seconds
Started Oct 09 04:46:27 AM UTC 24
Finished Oct 09 04:51:06 AM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164355388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3164355388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1677560369
Short name T77
Test name
Test status
Simulation time 48300024 ps
CPU time 10.83 seconds
Started Oct 09 04:46:19 AM UTC 24
Finished Oct 09 04:46:31 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677560369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1677560369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.579564701
Short name T548
Test name
Test status
Simulation time 177296003 ps
CPU time 10.75 seconds
Started Oct 09 04:59:12 AM UTC 24
Finished Oct 09 04:59:24 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579564701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.579564701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3133193757
Short name T873
Test name
Test status
Simulation time 219294263475 ps
CPU time 656.97 seconds
Started Oct 09 04:59:13 AM UTC 24
Finished Oct 09 05:10:19 AM UTC 24
Peak memory 221516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133193757 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3133193757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3751449492
Short name T556
Test name
Test status
Simulation time 97396294 ps
CPU time 12.53 seconds
Started Oct 09 04:59:23 AM UTC 24
Finished Oct 09 04:59:37 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751449492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3751449492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.2849631488
Short name T550
Test name
Test status
Simulation time 34683697 ps
CPU time 7.35 seconds
Started Oct 09 04:59:20 AM UTC 24
Finished Oct 09 04:59:28 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849631488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2849631488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.575349450
Short name T552
Test name
Test status
Simulation time 310852728 ps
CPU time 19.12 seconds
Started Oct 09 04:59:08 AM UTC 24
Finished Oct 09 04:59:29 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575349450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.575349450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1858570932
Short name T616
Test name
Test status
Simulation time 20111503292 ps
CPU time 157.67 seconds
Started Oct 09 04:59:08 AM UTC 24
Finished Oct 09 05:01:49 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858570932 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1858570932
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3080649796
Short name T553
Test name
Test status
Simulation time 2676715429 ps
CPU time 17.84 seconds
Started Oct 09 04:59:10 AM UTC 24
Finished Oct 09 04:59:30 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080649796 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3080649796
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.4167625518
Short name T551
Test name
Test status
Simulation time 174787831 ps
CPU time 19.04 seconds
Started Oct 09 04:59:08 AM UTC 24
Finished Oct 09 04:59:29 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167625518 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4167625518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.4267672482
Short name T554
Test name
Test status
Simulation time 497441124 ps
CPU time 14.82 seconds
Started Oct 09 04:59:13 AM UTC 24
Finished Oct 09 04:59:30 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267672482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4267672482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1619978972
Short name T538
Test name
Test status
Simulation time 295121629 ps
CPU time 5.29 seconds
Started Oct 09 04:59:00 AM UTC 24
Finished Oct 09 04:59:06 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619978972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1619978972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3418390384
Short name T557
Test name
Test status
Simulation time 5282224468 ps
CPU time 32.79 seconds
Started Oct 09 04:59:04 AM UTC 24
Finished Oct 09 04:59:38 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418390384 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3418390384
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.954037828
Short name T67
Test name
Test status
Simulation time 3213514649 ps
CPU time 30.82 seconds
Started Oct 09 04:59:05 AM UTC 24
Finished Oct 09 04:59:37 AM UTC 24
Peak memory 216072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954037828 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.954037828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1963145762
Short name T539
Test name
Test status
Simulation time 32090661 ps
CPU time 3.24 seconds
Started Oct 09 04:59:02 AM UTC 24
Finished Oct 09 04:59:07 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963145762 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1963145762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1805601441
Short name T615
Test name
Test status
Simulation time 4034308107 ps
CPU time 140.64 seconds
Started Oct 09 04:59:25 AM UTC 24
Finished Oct 09 05:01:48 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805601441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1805601441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.880212048
Short name T657
Test name
Test status
Simulation time 21938553153 ps
CPU time 209.24 seconds
Started Oct 09 04:59:27 AM UTC 24
Finished Oct 09 05:03:00 AM UTC 24
Peak memory 220192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880212048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.880212048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3698824711
Short name T180
Test name
Test status
Simulation time 578042726 ps
CPU time 55.41 seconds
Started Oct 09 04:59:26 AM UTC 24
Finished Oct 09 05:00:23 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698824711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.3698824711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.841394091
Short name T611
Test name
Test status
Simulation time 964059319 ps
CPU time 129.25 seconds
Started Oct 09 04:59:29 AM UTC 24
Finished Oct 09 05:01:41 AM UTC 24
Peak memory 221980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841394091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.841394091
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3882593038
Short name T562
Test name
Test status
Simulation time 1945509917 ps
CPU time 31.41 seconds
Started Oct 09 04:59:22 AM UTC 24
Finished Oct 09 04:59:55 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882593038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3882593038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2415983959
Short name T148
Test name
Test status
Simulation time 2136256485 ps
CPU time 68.14 seconds
Started Oct 09 04:59:40 AM UTC 24
Finished Oct 09 05:00:50 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415983959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2415983959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.188858290
Short name T757
Test name
Test status
Simulation time 96099505331 ps
CPU time 382 seconds
Started Oct 09 04:59:40 AM UTC 24
Finished Oct 09 05:06:07 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188858290 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.188858290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.4071682092
Short name T581
Test name
Test status
Simulation time 1551811152 ps
CPU time 40.27 seconds
Started Oct 09 04:59:52 AM UTC 24
Finished Oct 09 05:00:34 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071682092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4071682092
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.738429988
Short name T561
Test name
Test status
Simulation time 376825954 ps
CPU time 11.64 seconds
Started Oct 09 04:59:40 AM UTC 24
Finished Oct 09 04:59:53 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738429988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.738429988
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.3995568023
Short name T576
Test name
Test status
Simulation time 965963432 ps
CPU time 45.88 seconds
Started Oct 09 04:59:33 AM UTC 24
Finished Oct 09 05:00:21 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995568023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3995568023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.1448420646
Short name T666
Test name
Test status
Simulation time 55211986241 ps
CPU time 221.58 seconds
Started Oct 09 04:59:38 AM UTC 24
Finished Oct 09 05:03:23 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448420646 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1448420646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2369896551
Short name T639
Test name
Test status
Simulation time 25835849616 ps
CPU time 164.88 seconds
Started Oct 09 04:59:40 AM UTC 24
Finished Oct 09 05:02:27 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369896551 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2369896551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3906312139
Short name T563
Test name
Test status
Simulation time 336972722 ps
CPU time 22.49 seconds
Started Oct 09 04:59:37 AM UTC 24
Finished Oct 09 05:00:00 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906312139 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3906312139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.4197255285
Short name T574
Test name
Test status
Simulation time 1711448474 ps
CPU time 38.61 seconds
Started Oct 09 04:59:40 AM UTC 24
Finished Oct 09 05:00:20 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197255285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4197255285
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.2248347507
Short name T558
Test name
Test status
Simulation time 224306297 ps
CPU time 5.74 seconds
Started Oct 09 04:59:31 AM UTC 24
Finished Oct 09 04:59:38 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248347507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2248347507
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2550859278
Short name T564
Test name
Test status
Simulation time 4895816361 ps
CPU time 28.93 seconds
Started Oct 09 04:59:31 AM UTC 24
Finished Oct 09 05:00:01 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550859278 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2550859278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3949643734
Short name T566
Test name
Test status
Simulation time 3240912157 ps
CPU time 38.74 seconds
Started Oct 09 04:59:31 AM UTC 24
Finished Oct 09 05:00:12 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949643734 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3949643734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.597974952
Short name T555
Test name
Test status
Simulation time 30851948 ps
CPU time 3.35 seconds
Started Oct 09 04:59:31 AM UTC 24
Finished Oct 09 04:59:35 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597974952 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.597974952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3815881581
Short name T628
Test name
Test status
Simulation time 5200246781 ps
CPU time 135.43 seconds
Started Oct 09 04:59:54 AM UTC 24
Finished Oct 09 05:02:12 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815881581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3815881581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3960608980
Short name T636
Test name
Test status
Simulation time 13062196621 ps
CPU time 136.71 seconds
Started Oct 09 05:00:01 AM UTC 24
Finished Oct 09 05:02:26 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960608980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3960608980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4142028209
Short name T567
Test name
Test status
Simulation time 87921702 ps
CPU time 14.63 seconds
Started Oct 09 04:59:56 AM UTC 24
Finished Oct 09 05:00:12 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142028209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.4142028209
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3527509091
Short name T686
Test name
Test status
Simulation time 1175501713 ps
CPU time 223.67 seconds
Started Oct 09 05:00:02 AM UTC 24
Finished Oct 09 05:03:54 AM UTC 24
Peak memory 232568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527509091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3527509091
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1106260335
Short name T565
Test name
Test status
Simulation time 305737068 ps
CPU time 19.38 seconds
Started Oct 09 04:59:46 AM UTC 24
Finished Oct 09 05:00:07 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106260335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1106260335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1254528796
Short name T256
Test name
Test status
Simulation time 542561780 ps
CPU time 44.02 seconds
Started Oct 09 05:00:19 AM UTC 24
Finished Oct 09 05:01:04 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254528796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1254528796
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1728885214
Short name T894
Test name
Test status
Simulation time 108173374369 ps
CPU time 768.06 seconds
Started Oct 09 05:00:20 AM UTC 24
Finished Oct 09 05:13:17 AM UTC 24
Peak memory 219532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728885214 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1728885214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2481497161
Short name T589
Test name
Test status
Simulation time 565607619 ps
CPU time 22.64 seconds
Started Oct 09 05:00:24 AM UTC 24
Finished Oct 09 05:00:48 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481497161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2481497161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1459941523
Short name T584
Test name
Test status
Simulation time 230014716 ps
CPU time 16.42 seconds
Started Oct 09 05:00:22 AM UTC 24
Finished Oct 09 05:00:39 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459941523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1459941523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.1247958442
Short name T588
Test name
Test status
Simulation time 294150119 ps
CPU time 31.6 seconds
Started Oct 09 05:00:14 AM UTC 24
Finished Oct 09 05:00:48 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247958442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1247958442
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.3684055500
Short name T692
Test name
Test status
Simulation time 42676117165 ps
CPU time 226.32 seconds
Started Oct 09 05:00:17 AM UTC 24
Finished Oct 09 05:04:07 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684055500 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3684055500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4072489909
Short name T69
Test name
Test status
Simulation time 4246651501 ps
CPU time 36 seconds
Started Oct 09 05:00:17 AM UTC 24
Finished Oct 09 05:00:54 AM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072489909 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.4072489909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2731270180
Short name T580
Test name
Test status
Simulation time 761943800 ps
CPU time 17.74 seconds
Started Oct 09 05:00:15 AM UTC 24
Finished Oct 09 05:00:34 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731270180 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2731270180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1094737354
Short name T290
Test name
Test status
Simulation time 1425168673 ps
CPU time 27.79 seconds
Started Oct 09 05:00:22 AM UTC 24
Finished Oct 09 05:00:51 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094737354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1094737354
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3633684961
Short name T571
Test name
Test status
Simulation time 37108662 ps
CPU time 3.87 seconds
Started Oct 09 05:00:10 AM UTC 24
Finished Oct 09 05:00:15 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633684961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3633684961
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.757032244
Short name T592
Test name
Test status
Simulation time 16777912918 ps
CPU time 50 seconds
Started Oct 09 05:00:13 AM UTC 24
Finished Oct 09 05:01:05 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757032244 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.757032244
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2714076103
Short name T293
Test name
Test status
Simulation time 3585604171 ps
CPU time 40.66 seconds
Started Oct 09 05:00:13 AM UTC 24
Finished Oct 09 05:00:55 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714076103 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2714076103
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.354503616
Short name T569
Test name
Test status
Simulation time 31168811 ps
CPU time 2.32 seconds
Started Oct 09 05:00:10 AM UTC 24
Finished Oct 09 05:00:13 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354503616 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.354503616
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.539613751
Short name T613
Test name
Test status
Simulation time 630546494 ps
CPU time 78.54 seconds
Started Oct 09 05:00:25 AM UTC 24
Finished Oct 09 05:01:46 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539613751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.539613751
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3739911272
Short name T607
Test name
Test status
Simulation time 2245692051 ps
CPU time 60.11 seconds
Started Oct 09 05:00:27 AM UTC 24
Finished Oct 09 05:01:29 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739911272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3739911272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1421076977
Short name T788
Test name
Test status
Simulation time 7540047994 ps
CPU time 394.49 seconds
Started Oct 09 05:00:27 AM UTC 24
Finished Oct 09 05:07:07 AM UTC 24
Peak memory 220128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421076977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1421076977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2976667719
Short name T667
Test name
Test status
Simulation time 2741963828 ps
CPU time 170.22 seconds
Started Oct 09 05:00:34 AM UTC 24
Finished Oct 09 05:03:27 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976667719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2976667719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1719012707
Short name T295
Test name
Test status
Simulation time 678003764 ps
CPU time 35.76 seconds
Started Oct 09 05:00:22 AM UTC 24
Finished Oct 09 05:00:59 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719012707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1719012707
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.2858064303
Short name T149
Test name
Test status
Simulation time 1648130104 ps
CPU time 59.72 seconds
Started Oct 09 05:00:46 AM UTC 24
Finished Oct 09 05:01:48 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858064303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2858064303
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3482821292
Short name T869
Test name
Test status
Simulation time 267993475033 ps
CPU time 535.24 seconds
Started Oct 09 05:00:50 AM UTC 24
Finished Oct 09 05:09:52 AM UTC 24
Peak memory 218320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482821292 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3482821292
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2818426114
Short name T294
Test name
Test status
Simulation time 121529510 ps
CPU time 5.64 seconds
Started Oct 09 05:00:52 AM UTC 24
Finished Oct 09 05:00:59 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818426114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2818426114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3730759157
Short name T601
Test name
Test status
Simulation time 1181856819 ps
CPU time 24.76 seconds
Started Oct 09 05:00:50 AM UTC 24
Finished Oct 09 05:01:16 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730759157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3730759157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3654309488
Short name T289
Test name
Test status
Simulation time 350406408 ps
CPU time 6.9 seconds
Started Oct 09 05:00:41 AM UTC 24
Finished Oct 09 05:00:49 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654309488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3654309488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.4245687354
Short name T596
Test name
Test status
Simulation time 3634241166 ps
CPU time 26.32 seconds
Started Oct 09 05:00:43 AM UTC 24
Finished Oct 09 05:01:10 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245687354 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4245687354
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3998776346
Short name T712
Test name
Test status
Simulation time 20807630647 ps
CPU time 230.59 seconds
Started Oct 09 05:00:45 AM UTC 24
Finished Oct 09 05:04:39 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998776346 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3998776346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.3053054021
Short name T598
Test name
Test status
Simulation time 445424110 ps
CPU time 27.71 seconds
Started Oct 09 05:00:43 AM UTC 24
Finished Oct 09 05:01:12 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053054021 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3053054021
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.459234836
Short name T591
Test name
Test status
Simulation time 930117900 ps
CPU time 10.22 seconds
Started Oct 09 05:00:50 AM UTC 24
Finished Oct 09 05:01:02 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459234836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.459234836
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.296619232
Short name T585
Test name
Test status
Simulation time 144434862 ps
CPU time 4.55 seconds
Started Oct 09 05:00:35 AM UTC 24
Finished Oct 09 05:00:41 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296619232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.296619232
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1259379984
Short name T608
Test name
Test status
Simulation time 10073553528 ps
CPU time 52.05 seconds
Started Oct 09 05:00:38 AM UTC 24
Finished Oct 09 05:01:32 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259379984 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1259379984
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1797068672
Short name T277
Test name
Test status
Simulation time 3990363572 ps
CPU time 34.61 seconds
Started Oct 09 05:00:39 AM UTC 24
Finished Oct 09 05:01:15 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797068672 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1797068672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3109922178
Short name T586
Test name
Test status
Simulation time 63877957 ps
CPU time 3.78 seconds
Started Oct 09 05:00:36 AM UTC 24
Finished Oct 09 05:00:41 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109922178 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3109922178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3730244087
Short name T715
Test name
Test status
Simulation time 1915143590 ps
CPU time 226.43 seconds
Started Oct 09 05:00:52 AM UTC 24
Finished Oct 09 05:04:42 AM UTC 24
Peak memory 222320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730244087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3730244087
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3919365752
Short name T625
Test name
Test status
Simulation time 1032151334 ps
CPU time 72.05 seconds
Started Oct 09 05:00:54 AM UTC 24
Finished Oct 09 05:02:08 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919365752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3919365752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1970371549
Short name T597
Test name
Test status
Simulation time 92367448 ps
CPU time 14.81 seconds
Started Oct 09 05:00:54 AM UTC 24
Finished Oct 09 05:01:11 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970371549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1970371549
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1456619588
Short name T742
Test name
Test status
Simulation time 3278649751 ps
CPU time 269.84 seconds
Started Oct 09 05:00:56 AM UTC 24
Finished Oct 09 05:05:30 AM UTC 24
Peak memory 232636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456619588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1456619588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.2747808966
Short name T590
Test name
Test status
Simulation time 255136590 ps
CPU time 9.47 seconds
Started Oct 09 05:00:50 AM UTC 24
Finished Oct 09 05:01:01 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747808966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2747808966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.728637392
Short name T602
Test name
Test status
Simulation time 28017814 ps
CPU time 7.45 seconds
Started Oct 09 05:01:08 AM UTC 24
Finished Oct 09 05:01:16 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728637392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.728637392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1309986236
Short name T886
Test name
Test status
Simulation time 55830202817 ps
CPU time 620.27 seconds
Started Oct 09 05:01:08 AM UTC 24
Finished Oct 09 05:11:36 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309986236 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1309986236
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1315365725
Short name T605
Test name
Test status
Simulation time 179855850 ps
CPU time 11.44 seconds
Started Oct 09 05:01:16 AM UTC 24
Finished Oct 09 05:01:28 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315365725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1315365725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3958831976
Short name T603
Test name
Test status
Simulation time 124200884 ps
CPU time 6.44 seconds
Started Oct 09 05:01:13 AM UTC 24
Finished Oct 09 05:01:21 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958831976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3958831976
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.2751206398
Short name T612
Test name
Test status
Simulation time 1206986425 ps
CPU time 38.75 seconds
Started Oct 09 05:01:03 AM UTC 24
Finished Oct 09 05:01:43 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751206398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2751206398
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1432603734
Short name T718
Test name
Test status
Simulation time 37729676135 ps
CPU time 218.16 seconds
Started Oct 09 05:01:06 AM UTC 24
Finished Oct 09 05:04:48 AM UTC 24
Peak memory 217956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432603734 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1432603734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.4252423110
Short name T727
Test name
Test status
Simulation time 25086811000 ps
CPU time 236.08 seconds
Started Oct 09 05:01:06 AM UTC 24
Finished Oct 09 05:05:06 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252423110 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4252423110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3491860540
Short name T600
Test name
Test status
Simulation time 52425151 ps
CPU time 5.66 seconds
Started Oct 09 05:01:06 AM UTC 24
Finished Oct 09 05:01:13 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491860540 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3491860540
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.1799505366
Short name T606
Test name
Test status
Simulation time 571722534 ps
CPU time 16.37 seconds
Started Oct 09 05:01:10 AM UTC 24
Finished Oct 09 05:01:29 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799505366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1799505366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.2628473711
Short name T594
Test name
Test status
Simulation time 418393490 ps
CPU time 6.62 seconds
Started Oct 09 05:00:58 AM UTC 24
Finished Oct 09 05:01:06 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628473711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2628473711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3787407019
Short name T610
Test name
Test status
Simulation time 4956555814 ps
CPU time 34.56 seconds
Started Oct 09 05:01:01 AM UTC 24
Finished Oct 09 05:01:37 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787407019 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3787407019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1644390215
Short name T609
Test name
Test status
Simulation time 16195386806 ps
CPU time 32.11 seconds
Started Oct 09 05:01:03 AM UTC 24
Finished Oct 09 05:01:36 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644390215 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1644390215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1383121846
Short name T593
Test name
Test status
Simulation time 27781294 ps
CPU time 3.05 seconds
Started Oct 09 05:01:01 AM UTC 24
Finished Oct 09 05:01:05 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383121846 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1383121846
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.2022786762
Short name T151
Test name
Test status
Simulation time 9584698899 ps
CPU time 121.1 seconds
Started Oct 09 05:01:16 AM UTC 24
Finished Oct 09 05:03:19 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022786762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2022786762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.441180682
Short name T658
Test name
Test status
Simulation time 18936245284 ps
CPU time 105.81 seconds
Started Oct 09 05:01:18 AM UTC 24
Finished Oct 09 05:03:06 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441180682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.441180682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2428497857
Short name T891
Test name
Test status
Simulation time 3640443598 ps
CPU time 661.64 seconds
Started Oct 09 05:01:16 AM UTC 24
Finished Oct 09 05:12:27 AM UTC 24
Peak memory 236260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428497857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2428497857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2671071449
Short name T678
Test name
Test status
Simulation time 377681062 ps
CPU time 139.67 seconds
Started Oct 09 05:01:18 AM UTC 24
Finished Oct 09 05:03:40 AM UTC 24
Peak memory 221984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671071449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2671071449
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3879830270
Short name T617
Test name
Test status
Simulation time 1207555108 ps
CPU time 35.78 seconds
Started Oct 09 05:01:13 AM UTC 24
Finished Oct 09 05:01:50 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879830270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3879830270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.189984170
Short name T174
Test name
Test status
Simulation time 2875490214 ps
CPU time 62.68 seconds
Started Oct 09 05:01:37 AM UTC 24
Finished Oct 09 05:02:41 AM UTC 24
Peak memory 218076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189984170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.189984170
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2878314686
Short name T871
Test name
Test status
Simulation time 70871953468 ps
CPU time 509.73 seconds
Started Oct 09 05:01:38 AM UTC 24
Finished Oct 09 05:10:14 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878314686 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2878314686
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3344041954
Short name T629
Test name
Test status
Simulation time 3128121244 ps
CPU time 23.9 seconds
Started Oct 09 05:01:47 AM UTC 24
Finished Oct 09 05:02:12 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344041954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3344041954
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1163162141
Short name T630
Test name
Test status
Simulation time 2695404472 ps
CPU time 30.05 seconds
Started Oct 09 05:01:44 AM UTC 24
Finished Oct 09 05:02:16 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163162141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1163162141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3379025981
Short name T622
Test name
Test status
Simulation time 2455221443 ps
CPU time 32.73 seconds
Started Oct 09 05:01:31 AM UTC 24
Finished Oct 09 05:02:05 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379025981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3379025981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.802037469
Short name T741
Test name
Test status
Simulation time 34412621365 ps
CPU time 233.18 seconds
Started Oct 09 05:01:33 AM UTC 24
Finished Oct 09 05:05:29 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802037469 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.802037469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.4164928996
Short name T760
Test name
Test status
Simulation time 28965635569 ps
CPU time 275.27 seconds
Started Oct 09 05:01:33 AM UTC 24
Finished Oct 09 05:06:12 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164928996 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4164928996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.1501949147
Short name T618
Test name
Test status
Simulation time 265547077 ps
CPU time 21.94 seconds
Started Oct 09 05:01:31 AM UTC 24
Finished Oct 09 05:01:55 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501949147 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1501949147
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1788326704
Short name T623
Test name
Test status
Simulation time 1181271845 ps
CPU time 21.9 seconds
Started Oct 09 05:01:43 AM UTC 24
Finished Oct 09 05:02:06 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788326704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1788326704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3241127277
Short name T604
Test name
Test status
Simulation time 349967971 ps
CPU time 5.24 seconds
Started Oct 09 05:01:18 AM UTC 24
Finished Oct 09 05:01:25 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241127277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3241127277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1472495237
Short name T638
Test name
Test status
Simulation time 6295473217 ps
CPU time 57.78 seconds
Started Oct 09 05:01:27 AM UTC 24
Finished Oct 09 05:02:27 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472495237 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1472495237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1285562525
Short name T626
Test name
Test status
Simulation time 3188944193 ps
CPU time 36.43 seconds
Started Oct 09 05:01:31 AM UTC 24
Finished Oct 09 05:02:09 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285562525 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1285562525
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3109593257
Short name T70
Test name
Test status
Simulation time 29719733 ps
CPU time 3.78 seconds
Started Oct 09 05:01:23 AM UTC 24
Finished Oct 09 05:01:28 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109593257 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3109593257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2961041534
Short name T267
Test name
Test status
Simulation time 3154043134 ps
CPU time 59.69 seconds
Started Oct 09 05:01:49 AM UTC 24
Finished Oct 09 05:02:51 AM UTC 24
Peak memory 218076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961041534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2961041534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4001660078
Short name T687
Test name
Test status
Simulation time 1223054050 ps
CPU time 122.67 seconds
Started Oct 09 05:01:52 AM UTC 24
Finished Oct 09 05:03:57 AM UTC 24
Peak memory 217888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001660078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4001660078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2569978024
Short name T881
Test name
Test status
Simulation time 3012163884 ps
CPU time 548.77 seconds
Started Oct 09 05:01:51 AM UTC 24
Finished Oct 09 05:11:08 AM UTC 24
Peak memory 232760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569978024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2569978024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1794033748
Short name T689
Test name
Test status
Simulation time 3622961422 ps
CPU time 125.31 seconds
Started Oct 09 05:01:52 AM UTC 24
Finished Oct 09 05:03:59 AM UTC 24
Peak memory 220000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794033748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1794033748
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.4044806380
Short name T632
Test name
Test status
Simulation time 944933903 ps
CPU time 31.2 seconds
Started Oct 09 05:01:47 AM UTC 24
Finished Oct 09 05:02:20 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044806380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4044806380
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.831615863
Short name T634
Test name
Test status
Simulation time 420021605 ps
CPU time 9.99 seconds
Started Oct 09 05:02:10 AM UTC 24
Finished Oct 09 05:02:22 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831615863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.831615863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1592250052
Short name T731
Test name
Test status
Simulation time 62653212738 ps
CPU time 173.9 seconds
Started Oct 09 05:02:12 AM UTC 24
Finished Oct 09 05:05:08 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592250052 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1592250052
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3608867517
Short name T644
Test name
Test status
Simulation time 483769269 ps
CPU time 16.49 seconds
Started Oct 09 05:02:19 AM UTC 24
Finished Oct 09 05:02:37 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608867517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3608867517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.270021030
Short name T651
Test name
Test status
Simulation time 1096126951 ps
CPU time 38.18 seconds
Started Oct 09 05:02:13 AM UTC 24
Finished Oct 09 05:02:53 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270021030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.270021030
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.2407870606
Short name T635
Test name
Test status
Simulation time 175894066 ps
CPU time 16.65 seconds
Started Oct 09 05:02:06 AM UTC 24
Finished Oct 09 05:02:24 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407870606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2407870606
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2134262552
Short name T649
Test name
Test status
Simulation time 7792082209 ps
CPU time 37.35 seconds
Started Oct 09 05:02:09 AM UTC 24
Finished Oct 09 05:02:48 AM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134262552 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2134262552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2289574182
Short name T832
Test name
Test status
Simulation time 126425647694 ps
CPU time 367.08 seconds
Started Oct 09 05:02:10 AM UTC 24
Finished Oct 09 05:08:22 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289574182 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2289574182
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3708179757
Short name T645
Test name
Test status
Simulation time 185213622 ps
CPU time 33.96 seconds
Started Oct 09 05:02:07 AM UTC 24
Finished Oct 09 05:02:43 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708179757 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3708179757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.2890442376
Short name T631
Test name
Test status
Simulation time 55150879 ps
CPU time 3.78 seconds
Started Oct 09 05:02:13 AM UTC 24
Finished Oct 09 05:02:18 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890442376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2890442376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.2594712764
Short name T621
Test name
Test status
Simulation time 235331129 ps
CPU time 6.05 seconds
Started Oct 09 05:01:56 AM UTC 24
Finished Oct 09 05:02:04 AM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594712764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2594712764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.4137364817
Short name T646
Test name
Test status
Simulation time 16757588103 ps
CPU time 39.2 seconds
Started Oct 09 05:02:05 AM UTC 24
Finished Oct 09 05:02:45 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137364817 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4137364817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4014544561
Short name T642
Test name
Test status
Simulation time 11411594739 ps
CPU time 27.79 seconds
Started Oct 09 05:02:05 AM UTC 24
Finished Oct 09 05:02:34 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014544561 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4014544561
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2731987903
Short name T624
Test name
Test status
Simulation time 45671255 ps
CPU time 3.34 seconds
Started Oct 09 05:02:03 AM UTC 24
Finished Oct 09 05:02:07 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731987903 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2731987903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1992599460
Short name T756
Test name
Test status
Simulation time 6393840714 ps
CPU time 216.56 seconds
Started Oct 09 05:02:21 AM UTC 24
Finished Oct 09 05:06:01 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992599460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1992599460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.4220400845
Short name T708
Test name
Test status
Simulation time 3208496208 ps
CPU time 124.26 seconds
Started Oct 09 05:02:22 AM UTC 24
Finished Oct 09 05:04:29 AM UTC 24
Peak memory 220192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220400845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4220400845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2529620058
Short name T177
Test name
Test status
Simulation time 9694904837 ps
CPU time 395.55 seconds
Started Oct 09 05:02:22 AM UTC 24
Finished Oct 09 05:09:04 AM UTC 24
Peak memory 222520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529620058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2529620058
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.379505805
Short name T650
Test name
Test status
Simulation time 12061473 ps
CPU time 25.85 seconds
Started Oct 09 05:02:25 AM UTC 24
Finished Oct 09 05:02:52 AM UTC 24
Peak memory 217868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379505805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.379505805
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.680515000
Short name T647
Test name
Test status
Simulation time 1429035168 ps
CPU time 27.33 seconds
Started Oct 09 05:02:17 AM UTC 24
Finished Oct 09 05:02:46 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680515000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.680515000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.2009363272
Short name T212
Test name
Test status
Simulation time 1354102272 ps
CPU time 43.08 seconds
Started Oct 09 05:02:37 AM UTC 24
Finished Oct 09 05:03:22 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009363272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2009363272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.306376446
Short name T754
Test name
Test status
Simulation time 25938770916 ps
CPU time 190.89 seconds
Started Oct 09 05:02:39 AM UTC 24
Finished Oct 09 05:05:53 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306376446 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.306376446
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.25568546
Short name T656
Test name
Test status
Simulation time 336702229 ps
CPU time 12.12 seconds
Started Oct 09 05:02:45 AM UTC 24
Finished Oct 09 05:02:59 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25568546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.25568546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2836861559
Short name T669
Test name
Test status
Simulation time 1144931744 ps
CPU time 40.9 seconds
Started Oct 09 05:02:45 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836861559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2836861559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3514438406
Short name T655
Test name
Test status
Simulation time 179559920 ps
CPU time 25.03 seconds
Started Oct 09 05:02:33 AM UTC 24
Finished Oct 09 05:02:59 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514438406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3514438406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.913114799
Short name T265
Test name
Test status
Simulation time 95068981197 ps
CPU time 311.24 seconds
Started Oct 09 05:02:35 AM UTC 24
Finished Oct 09 05:07:51 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913114799 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.913114799
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1150396058
Short name T736
Test name
Test status
Simulation time 23400618479 ps
CPU time 162.61 seconds
Started Oct 09 05:02:35 AM UTC 24
Finished Oct 09 05:05:21 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150396058 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1150396058
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.1778884612
Short name T652
Test name
Test status
Simulation time 123273491 ps
CPU time 18.94 seconds
Started Oct 09 05:02:35 AM UTC 24
Finished Oct 09 05:02:55 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778884612 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1778884612
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1046768805
Short name T664
Test name
Test status
Simulation time 2137296644 ps
CPU time 35.23 seconds
Started Oct 09 05:02:43 AM UTC 24
Finished Oct 09 05:03:20 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046768805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1046768805
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.4171695130
Short name T71
Test name
Test status
Simulation time 36118350 ps
CPU time 3.2 seconds
Started Oct 09 05:02:28 AM UTC 24
Finished Oct 09 05:02:32 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171695130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.4171695130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3848964197
Short name T663
Test name
Test status
Simulation time 18494408871 ps
CPU time 49.4 seconds
Started Oct 09 05:02:28 AM UTC 24
Finished Oct 09 05:03:19 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848964197 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3848964197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.966070788
Short name T660
Test name
Test status
Simulation time 10523564138 ps
CPU time 41.89 seconds
Started Oct 09 05:02:29 AM UTC 24
Finished Oct 09 05:03:12 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966070788 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.966070788
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2832031681
Short name T640
Test name
Test status
Simulation time 39971744 ps
CPU time 2.44 seconds
Started Oct 09 05:02:28 AM UTC 24
Finished Oct 09 05:02:31 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832031681 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2832031681
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.3635335097
Short name T702
Test name
Test status
Simulation time 4151950413 ps
CPU time 87.84 seconds
Started Oct 09 05:02:47 AM UTC 24
Finished Oct 09 05:04:17 AM UTC 24
Peak memory 220124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635335097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3635335097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2308540743
Short name T777
Test name
Test status
Simulation time 9714355242 ps
CPU time 230.38 seconds
Started Oct 09 05:02:49 AM UTC 24
Finished Oct 09 05:06:44 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308540743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2308540743
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2879257991
Short name T181
Test name
Test status
Simulation time 9012907391 ps
CPU time 432.13 seconds
Started Oct 09 05:02:47 AM UTC 24
Finished Oct 09 05:10:06 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879257991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2879257991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1716484917
Short name T764
Test name
Test status
Simulation time 11700809437 ps
CPU time 202.85 seconds
Started Oct 09 05:02:49 AM UTC 24
Finished Oct 09 05:06:15 AM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716484917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1716484917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1495264412
Short name T659
Test name
Test status
Simulation time 606139743 ps
CPU time 25.33 seconds
Started Oct 09 05:02:45 AM UTC 24
Finished Oct 09 05:03:12 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495264412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1495264412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3464376570
Short name T688
Test name
Test status
Simulation time 1221156866 ps
CPU time 55.18 seconds
Started Oct 09 05:03:02 AM UTC 24
Finished Oct 09 05:03:59 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464376570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3464376570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1169506376
Short name T798
Test name
Test status
Simulation time 51954387795 ps
CPU time 256.23 seconds
Started Oct 09 05:03:03 AM UTC 24
Finished Oct 09 05:07:23 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169506376 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1169506376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1353524336
Short name T673
Test name
Test status
Simulation time 620575692 ps
CPU time 13.11 seconds
Started Oct 09 05:03:16 AM UTC 24
Finished Oct 09 05:03:30 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353524336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1353524336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2510795222
Short name T679
Test name
Test status
Simulation time 3658618921 ps
CPU time 27 seconds
Started Oct 09 05:03:14 AM UTC 24
Finished Oct 09 05:03:42 AM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510795222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2510795222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2263878671
Short name T668
Test name
Test status
Simulation time 259810293 ps
CPU time 28.73 seconds
Started Oct 09 05:02:58 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263878671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2263878671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.818262058
Short name T278
Test name
Test status
Simulation time 98442054519 ps
CPU time 254.16 seconds
Started Oct 09 05:03:01 AM UTC 24
Finished Oct 09 05:07:19 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818262058 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.818262058
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1994501657
Short name T716
Test name
Test status
Simulation time 54099392672 ps
CPU time 101.45 seconds
Started Oct 09 05:03:01 AM UTC 24
Finished Oct 09 05:04:45 AM UTC 24
Peak memory 216092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994501657 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1994501657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.2221868536
Short name T674
Test name
Test status
Simulation time 294105523 ps
CPU time 29.67 seconds
Started Oct 09 05:02:59 AM UTC 24
Finished Oct 09 05:03:31 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221868536 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2221868536
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.3901449421
Short name T665
Test name
Test status
Simulation time 757453164 ps
CPU time 12.64 seconds
Started Oct 09 05:03:07 AM UTC 24
Finished Oct 09 05:03:21 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901449421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3901449421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.2351943186
Short name T653
Test name
Test status
Simulation time 44393511 ps
CPU time 3.69 seconds
Started Oct 09 05:02:52 AM UTC 24
Finished Oct 09 05:02:57 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351943186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2351943186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3301879935
Short name T684
Test name
Test status
Simulation time 23473385742 ps
CPU time 55.19 seconds
Started Oct 09 05:02:55 AM UTC 24
Finished Oct 09 05:03:52 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301879935 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3301879935
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.468902267
Short name T72
Test name
Test status
Simulation time 6387649803 ps
CPU time 21.17 seconds
Started Oct 09 05:02:56 AM UTC 24
Finished Oct 09 05:03:19 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468902267 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.468902267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1958043815
Short name T654
Test name
Test status
Simulation time 63904188 ps
CPU time 3.12 seconds
Started Oct 09 05:02:53 AM UTC 24
Finished Oct 09 05:02:57 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958043815 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1958043815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.741004201
Short name T762
Test name
Test status
Simulation time 7651377678 ps
CPU time 175.83 seconds
Started Oct 09 05:03:16 AM UTC 24
Finished Oct 09 05:06:15 AM UTC 24
Peak memory 220188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741004201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.741004201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1558328457
Short name T705
Test name
Test status
Simulation time 422606668 ps
CPU time 58.64 seconds
Started Oct 09 05:03:20 AM UTC 24
Finished Oct 09 05:04:21 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558328457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1558328457
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3426963526
Short name T893
Test name
Test status
Simulation time 9395754870 ps
CPU time 567.17 seconds
Started Oct 09 05:03:20 AM UTC 24
Finished Oct 09 05:12:55 AM UTC 24
Peak memory 223688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426963526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3426963526
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.456531064
Short name T787
Test name
Test status
Simulation time 3127202485 ps
CPU time 220.8 seconds
Started Oct 09 05:03:22 AM UTC 24
Finished Oct 09 05:07:06 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456531064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.456531064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1958878041
Short name T671
Test name
Test status
Simulation time 106331597 ps
CPU time 13.02 seconds
Started Oct 09 05:03:14 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 217872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958878041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1958878041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.55085765
Short name T677
Test name
Test status
Simulation time 32790828 ps
CPU time 7.11 seconds
Started Oct 09 05:03:30 AM UTC 24
Finished Oct 09 05:03:38 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55085765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.55085765
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1391128885
Short name T899
Test name
Test status
Simulation time 87452577023 ps
CPU time 741.64 seconds
Started Oct 09 05:03:30 AM UTC 24
Finished Oct 09 05:16:00 AM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391128885 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1391128885
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3167374093
Short name T676
Test name
Test status
Simulation time 114684488 ps
CPU time 3.21 seconds
Started Oct 09 05:03:32 AM UTC 24
Finished Oct 09 05:03:36 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167374093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3167374093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.3176815532
Short name T680
Test name
Test status
Simulation time 92974169 ps
CPU time 9.65 seconds
Started Oct 09 05:03:32 AM UTC 24
Finished Oct 09 05:03:43 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176815532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3176815532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.971606078
Short name T213
Test name
Test status
Simulation time 1882369872 ps
CPU time 33.9 seconds
Started Oct 09 05:03:29 AM UTC 24
Finished Oct 09 05:04:05 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971606078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.971606078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3386580040
Short name T867
Test name
Test status
Simulation time 128712857450 ps
CPU time 371.36 seconds
Started Oct 09 05:03:30 AM UTC 24
Finished Oct 09 05:09:46 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386580040 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3386580040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.863443339
Short name T763
Test name
Test status
Simulation time 69907848955 ps
CPU time 162.46 seconds
Started Oct 09 05:03:30 AM UTC 24
Finished Oct 09 05:06:15 AM UTC 24
Peak memory 216088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863443339 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.863443339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.848145460
Short name T685
Test name
Test status
Simulation time 264032749 ps
CPU time 22.45 seconds
Started Oct 09 05:03:29 AM UTC 24
Finished Oct 09 05:03:53 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848145460 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.848145460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.368540429
Short name T675
Test name
Test status
Simulation time 95958862 ps
CPU time 3.52 seconds
Started Oct 09 05:03:30 AM UTC 24
Finished Oct 09 05:03:34 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368540429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.368540429
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.3381813683
Short name T672
Test name
Test status
Simulation time 232384100 ps
CPU time 5.29 seconds
Started Oct 09 05:03:22 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381813683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3381813683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.985980773
Short name T694
Test name
Test status
Simulation time 4987903065 ps
CPU time 45.44 seconds
Started Oct 09 05:03:24 AM UTC 24
Finished Oct 09 05:04:11 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985980773 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.985980773
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.342827261
Short name T690
Test name
Test status
Simulation time 12293435194 ps
CPU time 33.66 seconds
Started Oct 09 05:03:25 AM UTC 24
Finished Oct 09 05:04:00 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342827261 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.342827261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1029049242
Short name T670
Test name
Test status
Simulation time 37344713 ps
CPU time 3.53 seconds
Started Oct 09 05:03:24 AM UTC 24
Finished Oct 09 05:03:28 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029049242 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1029049242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.168160687
Short name T153
Test name
Test status
Simulation time 4317861973 ps
CPU time 108.09 seconds
Started Oct 09 05:03:33 AM UTC 24
Finished Oct 09 05:05:24 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168160687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.168160687
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.81869406
Short name T723
Test name
Test status
Simulation time 844368439 ps
CPU time 77.89 seconds
Started Oct 09 05:03:38 AM UTC 24
Finished Oct 09 05:04:58 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81869406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.81869406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4143400672
Short name T683
Test name
Test status
Simulation time 12869252 ps
CPU time 12.77 seconds
Started Oct 09 05:03:35 AM UTC 24
Finished Oct 09 05:03:50 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143400672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.4143400672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.885117389
Short name T811
Test name
Test status
Simulation time 7173217990 ps
CPU time 243.59 seconds
Started Oct 09 05:03:40 AM UTC 24
Finished Oct 09 05:07:47 AM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885117389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.885117389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1434469895
Short name T691
Test name
Test status
Simulation time 3038162143 ps
CPU time 28.94 seconds
Started Oct 09 05:03:32 AM UTC 24
Finished Oct 09 05:04:02 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434469895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1434469895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.751362772
Short name T253
Test name
Test status
Simulation time 145593170 ps
CPU time 22.32 seconds
Started Oct 09 04:46:37 AM UTC 24
Finished Oct 09 04:47:00 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751362772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.751362772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4214346395
Short name T287
Test name
Test status
Simulation time 89862045507 ps
CPU time 656.73 seconds
Started Oct 09 04:46:38 AM UTC 24
Finished Oct 09 04:57:42 AM UTC 24
Peak memory 219464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214346395 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.4214346395
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1794152778
Short name T89
Test name
Test status
Simulation time 444019741 ps
CPU time 13.7 seconds
Started Oct 09 04:46:41 AM UTC 24
Finished Oct 09 04:46:56 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794152778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1794152778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.3999572076
Short name T329
Test name
Test status
Simulation time 535043397 ps
CPU time 24.62 seconds
Started Oct 09 04:46:40 AM UTC 24
Finished Oct 09 04:47:06 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999572076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3999572076
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.988053163
Short name T328
Test name
Test status
Simulation time 733134071 ps
CPU time 31.03 seconds
Started Oct 09 04:46:32 AM UTC 24
Finished Oct 09 04:47:05 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988053163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.988053163
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.2930885953
Short name T88
Test name
Test status
Simulation time 4167261939 ps
CPU time 19.96 seconds
Started Oct 09 04:46:35 AM UTC 24
Finished Oct 09 04:46:56 AM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930885953 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2930885953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1131271719
Short name T308
Test name
Test status
Simulation time 3439574544 ps
CPU time 40.38 seconds
Started Oct 09 04:46:35 AM UTC 24
Finished Oct 09 04:47:17 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131271719 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1131271719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.3101153860
Short name T186
Test name
Test status
Simulation time 207939909 ps
CPU time 23.13 seconds
Started Oct 09 04:46:34 AM UTC 24
Finished Oct 09 04:46:59 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101153860 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3101153860
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.2433261790
Short name T85
Test name
Test status
Simulation time 97866010 ps
CPU time 13.33 seconds
Started Oct 09 04:46:38 AM UTC 24
Finished Oct 09 04:46:53 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433261790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2433261790
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1567604178
Short name T206
Test name
Test status
Simulation time 1089203856 ps
CPU time 6.24 seconds
Started Oct 09 04:46:28 AM UTC 24
Finished Oct 09 04:46:36 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567604178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1567604178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2729852644
Short name T302
Test name
Test status
Simulation time 7606271608 ps
CPU time 40.66 seconds
Started Oct 09 04:46:30 AM UTC 24
Finished Oct 09 04:47:12 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729852644 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2729852644
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1402575540
Short name T54
Test name
Test status
Simulation time 2925426150 ps
CPU time 33.47 seconds
Started Oct 09 04:46:32 AM UTC 24
Finished Oct 09 04:47:07 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402575540 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1402575540
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3454088040
Short name T79
Test name
Test status
Simulation time 28028727 ps
CPU time 3.7 seconds
Started Oct 09 04:46:28 AM UTC 24
Finished Oct 09 04:46:33 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454088040 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3454088040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.783483703
Short name T194
Test name
Test status
Simulation time 6919648154 ps
CPU time 251.65 seconds
Started Oct 09 04:46:46 AM UTC 24
Finished Oct 09 04:51:01 AM UTC 24
Peak memory 222172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783483703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.783483703
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1788668004
Short name T263
Test name
Test status
Simulation time 1171033464 ps
CPU time 147.81 seconds
Started Oct 09 04:46:50 AM UTC 24
Finished Oct 09 04:49:21 AM UTC 24
Peak memory 217892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788668004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1788668004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.531712999
Short name T30
Test name
Test status
Simulation time 7793791430 ps
CPU time 480.49 seconds
Started Oct 09 04:46:50 AM UTC 24
Finished Oct 09 04:54:58 AM UTC 24
Peak memory 236736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531712999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.531712999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.578787974
Short name T331
Test name
Test status
Simulation time 234571385 ps
CPU time 35.7 seconds
Started Oct 09 04:46:40 AM UTC 24
Finished Oct 09 04:47:17 AM UTC 24
Peak memory 215792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578787974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.578787974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3145086829
Short name T726
Test name
Test status
Simulation time 2250316447 ps
CPU time 64.97 seconds
Started Oct 09 05:03:55 AM UTC 24
Finished Oct 09 05:05:02 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145086829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3145086829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.28884468
Short name T897
Test name
Test status
Simulation time 53851107130 ps
CPU time 608.32 seconds
Started Oct 09 05:03:58 AM UTC 24
Finished Oct 09 05:14:13 AM UTC 24
Peak memory 218304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28884468 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
8/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.28884468
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2773408821
Short name T700
Test name
Test status
Simulation time 106768189 ps
CPU time 12.44 seconds
Started Oct 09 05:04:03 AM UTC 24
Finished Oct 09 05:04:17 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773408821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2773408821
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.802221418
Short name T697
Test name
Test status
Simulation time 355763070 ps
CPU time 13.06 seconds
Started Oct 09 05:04:01 AM UTC 24
Finished Oct 09 05:04:15 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802221418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.802221418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.991749314
Short name T711
Test name
Test status
Simulation time 1003751450 ps
CPU time 43.45 seconds
Started Oct 09 05:03:48 AM UTC 24
Finished Oct 09 05:04:33 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991749314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.991749314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2527683047
Short name T696
Test name
Test status
Simulation time 2392641122 ps
CPU time 22.39 seconds
Started Oct 09 05:03:51 AM UTC 24
Finished Oct 09 05:04:15 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527683047 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2527683047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2921364485
Short name T776
Test name
Test status
Simulation time 19077180202 ps
CPU time 166.86 seconds
Started Oct 09 05:03:52 AM UTC 24
Finished Oct 09 05:06:42 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921364485 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2921364485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2499226388
Short name T695
Test name
Test status
Simulation time 153203700 ps
CPU time 21.38 seconds
Started Oct 09 05:03:50 AM UTC 24
Finished Oct 09 05:04:12 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499226388 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2499226388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1792127313
Short name T701
Test name
Test status
Simulation time 347026502 ps
CPU time 17.61 seconds
Started Oct 09 05:03:58 AM UTC 24
Finished Oct 09 05:04:16 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792127313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1792127313
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.342033152
Short name T681
Test name
Test status
Simulation time 34454472 ps
CPU time 3.82 seconds
Started Oct 09 05:03:42 AM UTC 24
Finished Oct 09 05:03:47 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342033152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.342033152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3717489801
Short name T74
Test name
Test status
Simulation time 6641473034 ps
CPU time 34.86 seconds
Started Oct 09 05:03:44 AM UTC 24
Finished Oct 09 05:04:21 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717489801 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3717489801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.82584396
Short name T707
Test name
Test status
Simulation time 5402673563 ps
CPU time 42.32 seconds
Started Oct 09 05:03:44 AM UTC 24
Finished Oct 09 05:04:28 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82584396 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.82584396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1143617146
Short name T682
Test name
Test status
Simulation time 30530033 ps
CPU time 2.47 seconds
Started Oct 09 05:03:44 AM UTC 24
Finished Oct 09 05:03:48 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143617146 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1143617146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1125393894
Short name T176
Test name
Test status
Simulation time 3313404103 ps
CPU time 119.5 seconds
Started Oct 09 05:04:03 AM UTC 24
Finished Oct 09 05:06:05 AM UTC 24
Peak memory 218012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125393894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1125393894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1692575255
Short name T769
Test name
Test status
Simulation time 2320387765 ps
CPU time 135.72 seconds
Started Oct 09 05:04:08 AM UTC 24
Finished Oct 09 05:06:26 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692575255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1692575255
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1991210003
Short name T730
Test name
Test status
Simulation time 144627617 ps
CPU time 59.29 seconds
Started Oct 09 05:04:06 AM UTC 24
Finished Oct 09 05:05:07 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991210003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1991210003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2118188869
Short name T704
Test name
Test status
Simulation time 20072924 ps
CPU time 8.17 seconds
Started Oct 09 05:04:11 AM UTC 24
Finished Oct 09 05:04:20 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118188869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2118188869
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1812277102
Short name T698
Test name
Test status
Simulation time 924490496 ps
CPU time 13.47 seconds
Started Oct 09 05:04:01 AM UTC 24
Finished Oct 09 05:04:16 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812277102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1812277102
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1472212226
Short name T721
Test name
Test status
Simulation time 199458719 ps
CPU time 32.44 seconds
Started Oct 09 05:04:20 AM UTC 24
Finished Oct 09 05:04:54 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472212226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1472212226
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1199025772
Short name T889
Test name
Test status
Simulation time 135271160412 ps
CPU time 458.48 seconds
Started Oct 09 05:04:20 AM UTC 24
Finished Oct 09 05:12:05 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199025772 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1199025772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.985436212
Short name T710
Test name
Test status
Simulation time 125782549 ps
CPU time 5.4 seconds
Started Oct 09 05:04:25 AM UTC 24
Finished Oct 09 05:04:32 AM UTC 24
Peak memory 215972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985436212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.985436212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1723546673
Short name T713
Test name
Test status
Simulation time 429761274 ps
CPU time 15.7 seconds
Started Oct 09 05:04:22 AM UTC 24
Finished Oct 09 05:04:40 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723546673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1723546673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.3980448734
Short name T722
Test name
Test status
Simulation time 365246780 ps
CPU time 34.78 seconds
Started Oct 09 05:04:18 AM UTC 24
Finished Oct 09 05:04:55 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980448734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3980448734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3435179605
Short name T853
Test name
Test status
Simulation time 85825089167 ps
CPU time 279.3 seconds
Started Oct 09 05:04:19 AM UTC 24
Finished Oct 09 05:09:02 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435179605 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3435179605
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1387665799
Short name T300
Test name
Test status
Simulation time 94183315115 ps
CPU time 224.61 seconds
Started Oct 09 05:04:19 AM UTC 24
Finished Oct 09 05:08:07 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387665799 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1387665799
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1014524619
Short name T706
Test name
Test status
Simulation time 21784602 ps
CPU time 3.41 seconds
Started Oct 09 05:04:19 AM UTC 24
Finished Oct 09 05:04:23 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014524619 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1014524619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.4157265682
Short name T724
Test name
Test status
Simulation time 1493151818 ps
CPU time 34.24 seconds
Started Oct 09 05:04:22 AM UTC 24
Finished Oct 09 05:04:58 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157265682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4157265682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3069027051
Short name T699
Test name
Test status
Simulation time 22864632 ps
CPU time 2.85 seconds
Started Oct 09 05:04:12 AM UTC 24
Finished Oct 09 05:04:16 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069027051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3069027051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.363582117
Short name T719
Test name
Test status
Simulation time 7178482296 ps
CPU time 32.66 seconds
Started Oct 09 05:04:16 AM UTC 24
Finished Oct 09 05:04:50 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363582117 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.363582117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3307532662
Short name T728
Test name
Test status
Simulation time 6979691662 ps
CPU time 45.87 seconds
Started Oct 09 05:04:18 AM UTC 24
Finished Oct 09 05:05:06 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307532662 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3307532662
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2437035732
Short name T703
Test name
Test status
Simulation time 44384332 ps
CPU time 3.03 seconds
Started Oct 09 05:04:13 AM UTC 24
Finished Oct 09 05:04:18 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437035732 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2437035732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2562853543
Short name T155
Test name
Test status
Simulation time 8051837354 ps
CPU time 247.19 seconds
Started Oct 09 05:04:30 AM UTC 24
Finished Oct 09 05:08:41 AM UTC 24
Peak memory 222040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562853543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2562853543
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2861368333
Short name T863
Test name
Test status
Simulation time 11505488505 ps
CPU time 284.39 seconds
Started Oct 09 05:04:31 AM UTC 24
Finished Oct 09 05:09:20 AM UTC 24
Peak memory 222384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861368333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2861368333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1772466926
Short name T755
Test name
Test status
Simulation time 208424060 ps
CPU time 85.45 seconds
Started Oct 09 05:04:31 AM UTC 24
Finished Oct 09 05:05:59 AM UTC 24
Peak memory 219928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772466926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1772466926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.758640331
Short name T855
Test name
Test status
Simulation time 870531002 ps
CPU time 270.65 seconds
Started Oct 09 05:04:33 AM UTC 24
Finished Oct 09 05:09:08 AM UTC 24
Peak memory 232532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758640331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.758640331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3912164135
Short name T709
Test name
Test status
Simulation time 102542240 ps
CPU time 5.49 seconds
Started Oct 09 05:04:23 AM UTC 24
Finished Oct 09 05:04:29 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912164135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3912164135
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2338675918
Short name T725
Test name
Test status
Simulation time 405042084 ps
CPU time 8.78 seconds
Started Oct 09 05:04:51 AM UTC 24
Finished Oct 09 05:05:01 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338675918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2338675918
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3950065543
Short name T900
Test name
Test status
Simulation time 304554821677 ps
CPU time 830.73 seconds
Started Oct 09 05:04:53 AM UTC 24
Finished Oct 09 05:18:54 AM UTC 24
Peak memory 219468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950065543 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.3950065543
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.452344913
Short name T735
Test name
Test status
Simulation time 136975639 ps
CPU time 13.54 seconds
Started Oct 09 05:05:00 AM UTC 24
Finished Oct 09 05:05:15 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452344913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.452344913
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1865948767
Short name T743
Test name
Test status
Simulation time 882141845 ps
CPU time 34.59 seconds
Started Oct 09 05:04:57 AM UTC 24
Finished Oct 09 05:05:33 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865948767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1865948767
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.3672701297
Short name T720
Test name
Test status
Simulation time 165113955 ps
CPU time 6.97 seconds
Started Oct 09 05:04:44 AM UTC 24
Finished Oct 09 05:04:52 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672701297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3672701297
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.801647448
Short name T806
Test name
Test status
Simulation time 25781875416 ps
CPU time 172.14 seconds
Started Oct 09 05:04:46 AM UTC 24
Finished Oct 09 05:07:41 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801647448 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.801647448
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2090160778
Short name T852
Test name
Test status
Simulation time 44767485923 ps
CPU time 247.84 seconds
Started Oct 09 05:04:49 AM UTC 24
Finished Oct 09 05:09:01 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090160778 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2090160778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.1222521202
Short name T732
Test name
Test status
Simulation time 124239277 ps
CPU time 22.32 seconds
Started Oct 09 05:04:46 AM UTC 24
Finished Oct 09 05:05:10 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222521202 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1222521202
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.466192218
Short name T739
Test name
Test status
Simulation time 2803717505 ps
CPU time 30.19 seconds
Started Oct 09 05:04:55 AM UTC 24
Finished Oct 09 05:05:27 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466192218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.466192218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3824532237
Short name T714
Test name
Test status
Simulation time 244224176 ps
CPU time 5.01 seconds
Started Oct 09 05:04:35 AM UTC 24
Finished Oct 09 05:04:41 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824532237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3824532237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1117168450
Short name T737
Test name
Test status
Simulation time 8129360502 ps
CPU time 39.98 seconds
Started Oct 09 05:04:41 AM UTC 24
Finished Oct 09 05:05:22 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117168450 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1117168450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.737829678
Short name T740
Test name
Test status
Simulation time 2897992532 ps
CPU time 43.49 seconds
Started Oct 09 05:04:42 AM UTC 24
Finished Oct 09 05:05:27 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737829678 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.737829678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1401264033
Short name T717
Test name
Test status
Simulation time 35896890 ps
CPU time 3.6 seconds
Started Oct 09 05:04:41 AM UTC 24
Finished Oct 09 05:04:45 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401264033 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1401264033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2425606339
Short name T297
Test name
Test status
Simulation time 476632499 ps
CPU time 18.4 seconds
Started Oct 09 05:05:02 AM UTC 24
Finished Oct 09 05:05:22 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425606339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2425606339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.267495905
Short name T747
Test name
Test status
Simulation time 403830985 ps
CPU time 37.12 seconds
Started Oct 09 05:05:07 AM UTC 24
Finished Oct 09 05:05:46 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267495905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.267495905
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3192189410
Short name T874
Test name
Test status
Simulation time 8788255568 ps
CPU time 315.2 seconds
Started Oct 09 05:05:04 AM UTC 24
Finished Oct 09 05:10:24 AM UTC 24
Peak memory 222392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192189410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.3192189410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2129426237
Short name T828
Test name
Test status
Simulation time 604612830 ps
CPU time 182.34 seconds
Started Oct 09 05:05:07 AM UTC 24
Finished Oct 09 05:08:13 AM UTC 24
Peak memory 221980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129426237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2129426237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3175206405
Short name T729
Test name
Test status
Simulation time 760890942 ps
CPU time 5.94 seconds
Started Oct 09 05:05:00 AM UTC 24
Finished Oct 09 05:05:07 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175206405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3175206405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.926494761
Short name T759
Test name
Test status
Simulation time 1525700733 ps
CPU time 44.23 seconds
Started Oct 09 05:05:24 AM UTC 24
Finished Oct 09 05:06:10 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926494761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.926494761
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1856327442
Short name T778
Test name
Test status
Simulation time 9049529012 ps
CPU time 82.42 seconds
Started Oct 09 05:05:24 AM UTC 24
Finished Oct 09 05:06:48 AM UTC 24
Peak memory 216032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856327442 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1856327442
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2397539407
Short name T749
Test name
Test status
Simulation time 646676781 ps
CPU time 16.85 seconds
Started Oct 09 05:05:29 AM UTC 24
Finished Oct 09 05:05:47 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397539407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2397539407
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.92280952
Short name T746
Test name
Test status
Simulation time 362628678 ps
CPU time 14.24 seconds
Started Oct 09 05:05:29 AM UTC 24
Finished Oct 09 05:05:44 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92280952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.92280952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1719834892
Short name T751
Test name
Test status
Simulation time 713402373 ps
CPU time 32.62 seconds
Started Oct 09 05:05:14 AM UTC 24
Finished Oct 09 05:05:48 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719834892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1719834892
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2578926611
Short name T822
Test name
Test status
Simulation time 22646296016 ps
CPU time 161.62 seconds
Started Oct 09 05:05:16 AM UTC 24
Finished Oct 09 05:08:00 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578926611 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2578926611
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.4080509363
Short name T814
Test name
Test status
Simulation time 18235907503 ps
CPU time 146.03 seconds
Started Oct 09 05:05:21 AM UTC 24
Finished Oct 09 05:07:50 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080509363 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.4080509363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.1318992828
Short name T738
Test name
Test status
Simulation time 87685776 ps
CPU time 10.9 seconds
Started Oct 09 05:05:14 AM UTC 24
Finished Oct 09 05:05:26 AM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318992828 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1318992828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.67933535
Short name T744
Test name
Test status
Simulation time 48083907 ps
CPU time 6.25 seconds
Started Oct 09 05:05:25 AM UTC 24
Finished Oct 09 05:05:33 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67933535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.67933535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2889104086
Short name T733
Test name
Test status
Simulation time 38380383 ps
CPU time 3.47 seconds
Started Oct 09 05:05:09 AM UTC 24
Finished Oct 09 05:05:13 AM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889104086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2889104086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2716230572
Short name T748
Test name
Test status
Simulation time 4219828875 ps
CPU time 34.02 seconds
Started Oct 09 05:05:10 AM UTC 24
Finished Oct 09 05:05:46 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716230572 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2716230572
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1810667334
Short name T773
Test name
Test status
Simulation time 23212745483 ps
CPU time 78.12 seconds
Started Oct 09 05:05:12 AM UTC 24
Finished Oct 09 05:06:32 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810667334 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1810667334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1246993410
Short name T734
Test name
Test status
Simulation time 27238844 ps
CPU time 3.5 seconds
Started Oct 09 05:05:09 AM UTC 24
Finished Oct 09 05:05:13 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246993410 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1246993410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.3388228811
Short name T790
Test name
Test status
Simulation time 12942949028 ps
CPU time 98.04 seconds
Started Oct 09 05:05:30 AM UTC 24
Finished Oct 09 05:07:10 AM UTC 24
Peak memory 220124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388228811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3388228811
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1340306539
Short name T745
Test name
Test status
Simulation time 226293901 ps
CPU time 4.57 seconds
Started Oct 09 05:05:34 AM UTC 24
Finished Oct 09 05:05:40 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340306539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1340306539
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.171984216
Short name T779
Test name
Test status
Simulation time 1258268471 ps
CPU time 75.46 seconds
Started Oct 09 05:05:32 AM UTC 24
Finished Oct 09 05:06:49 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171984216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.171984216
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4217042274
Short name T872
Test name
Test status
Simulation time 8307641994 ps
CPU time 276.09 seconds
Started Oct 09 05:05:35 AM UTC 24
Finished Oct 09 05:10:15 AM UTC 24
Peak memory 222048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217042274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.4217042274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.233534296
Short name T753
Test name
Test status
Simulation time 448057988 ps
CPU time 22.91 seconds
Started Oct 09 05:05:29 AM UTC 24
Finished Oct 09 05:05:53 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233534296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.233534296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.710514747
Short name T154
Test name
Test status
Simulation time 2210790506 ps
CPU time 56.7 seconds
Started Oct 09 05:05:54 AM UTC 24
Finished Oct 09 05:06:52 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710514747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.710514747
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2173445379
Short name T860
Test name
Test status
Simulation time 32959121599 ps
CPU time 197.95 seconds
Started Oct 09 05:05:55 AM UTC 24
Finished Oct 09 05:09:16 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173445379 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2173445379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.293883875
Short name T765
Test name
Test status
Simulation time 428795486 ps
CPU time 8.85 seconds
Started Oct 09 05:06:08 AM UTC 24
Finished Oct 09 05:06:18 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293883875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.293883875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1837218759
Short name T775
Test name
Test status
Simulation time 1051682888 ps
CPU time 35.43 seconds
Started Oct 09 05:06:02 AM UTC 24
Finished Oct 09 05:06:39 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837218759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1837218759
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.1982022316
Short name T766
Test name
Test status
Simulation time 675891151 ps
CPU time 28.88 seconds
Started Oct 09 05:05:48 AM UTC 24
Finished Oct 09 05:06:19 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982022316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1982022316
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.3155592641
Short name T879
Test name
Test status
Simulation time 44658971666 ps
CPU time 304.39 seconds
Started Oct 09 05:05:50 AM UTC 24
Finished Oct 09 05:10:58 AM UTC 24
Peak memory 215908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155592641 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3155592641
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3331253521
Short name T807
Test name
Test status
Simulation time 21386689483 ps
CPU time 108.38 seconds
Started Oct 09 05:05:51 AM UTC 24
Finished Oct 09 05:07:42 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331253521 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3331253521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.852827886
Short name T758
Test name
Test status
Simulation time 165049876 ps
CPU time 17.28 seconds
Started Oct 09 05:05:48 AM UTC 24
Finished Oct 09 05:06:07 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852827886 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.852827886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2296721704
Short name T761
Test name
Test status
Simulation time 267590702 ps
CPU time 12.49 seconds
Started Oct 09 05:05:59 AM UTC 24
Finished Oct 09 05:06:13 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296721704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2296721704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.546491686
Short name T750
Test name
Test status
Simulation time 175874389 ps
CPU time 5.62 seconds
Started Oct 09 05:05:41 AM UTC 24
Finished Oct 09 05:05:48 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546491686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.546491686
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2008159181
Short name T774
Test name
Test status
Simulation time 7965299454 ps
CPU time 50.07 seconds
Started Oct 09 05:05:47 AM UTC 24
Finished Oct 09 05:06:39 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008159181 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2008159181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3715326556
Short name T770
Test name
Test status
Simulation time 4462874457 ps
CPU time 37.95 seconds
Started Oct 09 05:05:47 AM UTC 24
Finished Oct 09 05:06:26 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715326556 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3715326556
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3434506343
Short name T752
Test name
Test status
Simulation time 29773582 ps
CPU time 3.57 seconds
Started Oct 09 05:05:45 AM UTC 24
Finished Oct 09 05:05:50 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434506343 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3434506343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2728438198
Short name T179
Test name
Test status
Simulation time 36878686122 ps
CPU time 288.19 seconds
Started Oct 09 05:06:08 AM UTC 24
Finished Oct 09 05:11:01 AM UTC 24
Peak memory 222040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728438198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2728438198
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2106684861
Short name T856
Test name
Test status
Simulation time 1550759447 ps
CPU time 174.67 seconds
Started Oct 09 05:06:13 AM UTC 24
Finished Oct 09 05:09:11 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106684861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2106684861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3153223859
Short name T876
Test name
Test status
Simulation time 572064458 ps
CPU time 264.91 seconds
Started Oct 09 05:06:11 AM UTC 24
Finished Oct 09 05:10:40 AM UTC 24
Peak memory 221984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153223859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3153223859
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.959599309
Short name T804
Test name
Test status
Simulation time 270096139 ps
CPU time 81.92 seconds
Started Oct 09 05:06:15 AM UTC 24
Finished Oct 09 05:07:39 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959599309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.959599309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.482485255
Short name T772
Test name
Test status
Simulation time 155333126 ps
CPU time 23.82 seconds
Started Oct 09 05:06:06 AM UTC 24
Finished Oct 09 05:06:32 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482485255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.482485255
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3419302363
Short name T803
Test name
Test status
Simulation time 656386484 ps
CPU time 65.39 seconds
Started Oct 09 05:06:28 AM UTC 24
Finished Oct 09 05:07:35 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419302363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3419302363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2844015842
Short name T182
Test name
Test status
Simulation time 77951756543 ps
CPU time 698.1 seconds
Started Oct 09 05:06:33 AM UTC 24
Finished Oct 09 05:18:20 AM UTC 24
Peak memory 219596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844015842 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2844015842
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2600388866
Short name T792
Test name
Test status
Simulation time 2944155963 ps
CPU time 31.14 seconds
Started Oct 09 05:06:40 AM UTC 24
Finished Oct 09 05:07:13 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600388866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2600388866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.834770690
Short name T793
Test name
Test status
Simulation time 1001051865 ps
CPU time 39.83 seconds
Started Oct 09 05:06:33 AM UTC 24
Finished Oct 09 05:07:15 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834770690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.834770690
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3097143701
Short name T785
Test name
Test status
Simulation time 1369145820 ps
CPU time 38.04 seconds
Started Oct 09 05:06:20 AM UTC 24
Finished Oct 09 05:07:00 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097143701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3097143701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2110287530
Short name T844
Test name
Test status
Simulation time 32725284152 ps
CPU time 145.25 seconds
Started Oct 09 05:06:22 AM UTC 24
Finished Oct 09 05:08:50 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110287530 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2110287530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.336364838
Short name T817
Test name
Test status
Simulation time 16939811000 ps
CPU time 81.91 seconds
Started Oct 09 05:06:28 AM UTC 24
Finished Oct 09 05:07:52 AM UTC 24
Peak memory 216084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336364838 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.336364838
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1895940775
Short name T771
Test name
Test status
Simulation time 57796943 ps
CPU time 7.75 seconds
Started Oct 09 05:06:22 AM UTC 24
Finished Oct 09 05:06:31 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895940775 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1895940775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.684754554
Short name T796
Test name
Test status
Simulation time 2165184905 ps
CPU time 42.54 seconds
Started Oct 09 05:06:33 AM UTC 24
Finished Oct 09 05:07:17 AM UTC 24
Peak memory 216024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684754554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.684754554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3929835016
Short name T768
Test name
Test status
Simulation time 99492560 ps
CPU time 3.24 seconds
Started Oct 09 05:06:16 AM UTC 24
Finished Oct 09 05:06:21 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929835016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3929835016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.562310222
Short name T784
Test name
Test status
Simulation time 6185828085 ps
CPU time 40.89 seconds
Started Oct 09 05:06:17 AM UTC 24
Finished Oct 09 05:06:59 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562310222 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.562310222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1491826184
Short name T791
Test name
Test status
Simulation time 3686884846 ps
CPU time 49.59 seconds
Started Oct 09 05:06:19 AM UTC 24
Finished Oct 09 05:07:11 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491826184 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1491826184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3096008782
Short name T767
Test name
Test status
Simulation time 59200644 ps
CPU time 2.83 seconds
Started Oct 09 05:06:16 AM UTC 24
Finished Oct 09 05:06:20 AM UTC 24
Peak memory 215688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096008782 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3096008782
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3937312256
Short name T812
Test name
Test status
Simulation time 7833613867 ps
CPU time 62.89 seconds
Started Oct 09 05:06:43 AM UTC 24
Finished Oct 09 05:07:48 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937312256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3937312256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.627182872
Short name T854
Test name
Test status
Simulation time 11079044815 ps
CPU time 131.61 seconds
Started Oct 09 05:06:50 AM UTC 24
Finished Oct 09 05:09:05 AM UTC 24
Peak memory 218080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627182872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.627182872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4209489141
Short name T884
Test name
Test status
Simulation time 3190994315 ps
CPU time 265.68 seconds
Started Oct 09 05:06:45 AM UTC 24
Finished Oct 09 05:11:15 AM UTC 24
Peak memory 222112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209489141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.4209489141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2394079138
Short name T794
Test name
Test status
Simulation time 24455794 ps
CPU time 23.33 seconds
Started Oct 09 05:06:50 AM UTC 24
Finished Oct 09 05:07:15 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394079138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2394079138
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2439242171
Short name T781
Test name
Test status
Simulation time 76446489 ps
CPU time 10.94 seconds
Started Oct 09 05:06:40 AM UTC 24
Finished Oct 09 05:06:52 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439242171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2439242171
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.4121489462
Short name T250
Test name
Test status
Simulation time 4127576465 ps
CPU time 61.03 seconds
Started Oct 09 05:07:08 AM UTC 24
Finished Oct 09 05:08:11 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121489462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.4121489462
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1264046795
Short name T842
Test name
Test status
Simulation time 12551119462 ps
CPU time 89.21 seconds
Started Oct 09 05:07:10 AM UTC 24
Finished Oct 09 05:08:42 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264046795 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1264046795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2635413132
Short name T802
Test name
Test status
Simulation time 216845613 ps
CPU time 16.66 seconds
Started Oct 09 05:07:15 AM UTC 24
Finished Oct 09 05:07:33 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635413132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2635413132
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1418108333
Short name T795
Test name
Test status
Simulation time 16190187 ps
CPU time 3.3 seconds
Started Oct 09 05:07:12 AM UTC 24
Finished Oct 09 05:07:17 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418108333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1418108333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.33563498
Short name T789
Test name
Test status
Simulation time 61133435 ps
CPU time 9.07 seconds
Started Oct 09 05:06:59 AM UTC 24
Finished Oct 09 05:07:09 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33563498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.33563498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3493845182
Short name T887
Test name
Test status
Simulation time 87616590259 ps
CPU time 271.74 seconds
Started Oct 09 05:07:01 AM UTC 24
Finished Oct 09 05:11:37 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493845182 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3493845182
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3207532966
Short name T880
Test name
Test status
Simulation time 27555305234 ps
CPU time 235.21 seconds
Started Oct 09 05:07:08 AM UTC 24
Finished Oct 09 05:11:07 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207532966 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3207532966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.349636685
Short name T786
Test name
Test status
Simulation time 59660478 ps
CPU time 3.75 seconds
Started Oct 09 05:07:01 AM UTC 24
Finished Oct 09 05:07:06 AM UTC 24
Peak memory 215948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349636685 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.349636685
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3409365071
Short name T809
Test name
Test status
Simulation time 1453440929 ps
CPU time 32.49 seconds
Started Oct 09 05:07:10 AM UTC 24
Finished Oct 09 05:07:44 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409365071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3409365071
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3131721472
Short name T782
Test name
Test status
Simulation time 31690862 ps
CPU time 3.34 seconds
Started Oct 09 05:06:51 AM UTC 24
Finished Oct 09 05:06:55 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131721472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3131721472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2405581454
Short name T801
Test name
Test status
Simulation time 8442122661 ps
CPU time 36.79 seconds
Started Oct 09 05:06:53 AM UTC 24
Finished Oct 09 05:07:31 AM UTC 24
Peak memory 216004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405581454 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2405581454
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1034585014
Short name T805
Test name
Test status
Simulation time 5166898207 ps
CPU time 42.22 seconds
Started Oct 09 05:06:56 AM UTC 24
Finished Oct 09 05:07:39 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034585014 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1034585014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1460992492
Short name T783
Test name
Test status
Simulation time 80235352 ps
CPU time 3.22 seconds
Started Oct 09 05:06:53 AM UTC 24
Finished Oct 09 05:06:58 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460992492 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1460992492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2361862825
Short name T841
Test name
Test status
Simulation time 784996840 ps
CPU time 78.03 seconds
Started Oct 09 05:07:17 AM UTC 24
Finished Oct 09 05:08:37 AM UTC 24
Peak memory 219928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361862825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2361862825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3747808284
Short name T885
Test name
Test status
Simulation time 18360285874 ps
CPU time 240.81 seconds
Started Oct 09 05:07:19 AM UTC 24
Finished Oct 09 05:11:23 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747808284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3747808284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1435452116
Short name T870
Test name
Test status
Simulation time 568787030 ps
CPU time 157.54 seconds
Started Oct 09 05:07:17 AM UTC 24
Finished Oct 09 05:09:57 AM UTC 24
Peak memory 220064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435452116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1435452116
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.637968485
Short name T868
Test name
Test status
Simulation time 383634073 ps
CPU time 147.26 seconds
Started Oct 09 05:07:19 AM UTC 24
Finished Oct 09 05:09:49 AM UTC 24
Peak memory 222104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637968485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.637968485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.933806985
Short name T813
Test name
Test status
Simulation time 929910669 ps
CPU time 35.18 seconds
Started Oct 09 05:07:12 AM UTC 24
Finished Oct 09 05:07:49 AM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933806985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.933806985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1493272621
Short name T843
Test name
Test status
Simulation time 2803138333 ps
CPU time 62.83 seconds
Started Oct 09 05:07:40 AM UTC 24
Finished Oct 09 05:08:45 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493272621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1493272621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3315161734
Short name T251
Test name
Test status
Simulation time 30344560389 ps
CPU time 227.02 seconds
Started Oct 09 05:07:40 AM UTC 24
Finished Oct 09 05:11:31 AM UTC 24
Peak memory 218144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315161734 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.3315161734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.578308326
Short name T815
Test name
Test status
Simulation time 38080527 ps
CPU time 4.26 seconds
Started Oct 09 05:07:45 AM UTC 24
Finished Oct 09 05:07:51 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578308326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.578308326
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1517907087
Short name T829
Test name
Test status
Simulation time 896013630 ps
CPU time 29.97 seconds
Started Oct 09 05:07:44 AM UTC 24
Finished Oct 09 05:08:15 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517907087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1517907087
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.2993288881
Short name T808
Test name
Test status
Simulation time 372499233 ps
CPU time 14.79 seconds
Started Oct 09 05:07:28 AM UTC 24
Finished Oct 09 05:07:44 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993288881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2993288881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1237225061
Short name T882
Test name
Test status
Simulation time 156826874235 ps
CPU time 211.73 seconds
Started Oct 09 05:07:33 AM UTC 24
Finished Oct 09 05:11:08 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237225061 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1237225061
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.4023954784
Short name T878
Test name
Test status
Simulation time 27755876425 ps
CPU time 194.3 seconds
Started Oct 09 05:07:37 AM UTC 24
Finished Oct 09 05:10:55 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023954784 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4023954784
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.221041737
Short name T810
Test name
Test status
Simulation time 62307058 ps
CPU time 11.6 seconds
Started Oct 09 05:07:33 AM UTC 24
Finished Oct 09 05:07:46 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221041737 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.221041737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1819651665
Short name T819
Test name
Test status
Simulation time 107904042 ps
CPU time 11.37 seconds
Started Oct 09 05:07:43 AM UTC 24
Finished Oct 09 05:07:56 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819651665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1819651665
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.320603336
Short name T799
Test name
Test status
Simulation time 51447833 ps
CPU time 3.51 seconds
Started Oct 09 05:07:20 AM UTC 24
Finished Oct 09 05:07:25 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320603336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.320603336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.51369694
Short name T824
Test name
Test status
Simulation time 17655762644 ps
CPU time 38.85 seconds
Started Oct 09 05:07:24 AM UTC 24
Finished Oct 09 05:08:04 AM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51369694 -assert nopostproc +UVM_TESTNAME=xbar_base_
test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.51369694
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.52761840
Short name T820
Test name
Test status
Simulation time 3630931013 ps
CPU time 30.38 seconds
Started Oct 09 05:07:26 AM UTC 24
Finished Oct 09 05:07:58 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52761840 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.52761840
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.700529692
Short name T800
Test name
Test status
Simulation time 23102434 ps
CPU time 3.41 seconds
Started Oct 09 05:07:21 AM UTC 24
Finished Oct 09 05:07:27 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700529692 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.700529692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4126600610
Short name T816
Test name
Test status
Simulation time 6773176 ps
CPU time 1.4 seconds
Started Oct 09 05:07:48 AM UTC 24
Finished Oct 09 05:07:51 AM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126600610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4126600610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2653762098
Short name T833
Test name
Test status
Simulation time 1768250020 ps
CPU time 34.14 seconds
Started Oct 09 05:07:50 AM UTC 24
Finished Oct 09 05:08:26 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653762098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2653762098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2989447484
Short name T288
Test name
Test status
Simulation time 6449228817 ps
CPU time 414.05 seconds
Started Oct 09 05:07:49 AM UTC 24
Finished Oct 09 05:14:49 AM UTC 24
Peak memory 222520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989447484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2989447484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.4270869568
Short name T818
Test name
Test status
Simulation time 35094961 ps
CPU time 7.32 seconds
Started Oct 09 05:07:45 AM UTC 24
Finished Oct 09 05:07:54 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270869568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4270869568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2670376832
Short name T857
Test name
Test status
Simulation time 2114611827 ps
CPU time 68.93 seconds
Started Oct 09 05:08:01 AM UTC 24
Finished Oct 09 05:09:12 AM UTC 24
Peak memory 218072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670376832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2670376832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1477212127
Short name T890
Test name
Test status
Simulation time 111618851549 ps
CPU time 258.67 seconds
Started Oct 09 05:08:03 AM UTC 24
Finished Oct 09 05:12:25 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477212127 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1477212127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3764330359
Short name T836
Test name
Test status
Simulation time 464714285 ps
CPU time 18.5 seconds
Started Oct 09 05:08:07 AM UTC 24
Finished Oct 09 05:08:27 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764330359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3764330359
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4178226594
Short name T834
Test name
Test status
Simulation time 1185966798 ps
CPU time 20.11 seconds
Started Oct 09 05:08:05 AM UTC 24
Finished Oct 09 05:08:27 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178226594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4178226594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.1004735715
Short name T825
Test name
Test status
Simulation time 189488616 ps
CPU time 9.26 seconds
Started Oct 09 05:07:55 AM UTC 24
Finished Oct 09 05:08:05 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004735715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1004735715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2981333939
Short name T877
Test name
Test status
Simulation time 61780314257 ps
CPU time 159.6 seconds
Started Oct 09 05:07:59 AM UTC 24
Finished Oct 09 05:10:41 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981333939 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2981333939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4245110834
Short name T840
Test name
Test status
Simulation time 2816065238 ps
CPU time 31.57 seconds
Started Oct 09 05:08:01 AM UTC 24
Finished Oct 09 05:08:34 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245110834 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4245110834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1464436274
Short name T826
Test name
Test status
Simulation time 35501611 ps
CPU time 7.78 seconds
Started Oct 09 05:07:57 AM UTC 24
Finished Oct 09 05:08:06 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464436274 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1464436274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.240926222
Short name T827
Test name
Test status
Simulation time 25077787 ps
CPU time 3.46 seconds
Started Oct 09 05:08:03 AM UTC 24
Finished Oct 09 05:08:07 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240926222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.240926222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.292046127
Short name T823
Test name
Test status
Simulation time 162908723 ps
CPU time 4.85 seconds
Started Oct 09 05:07:54 AM UTC 24
Finished Oct 09 05:08:01 AM UTC 24
Peak memory 215940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292046127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.292046127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1790489177
Short name T839
Test name
Test status
Simulation time 4827735261 ps
CPU time 33.59 seconds
Started Oct 09 05:07:55 AM UTC 24
Finished Oct 09 05:08:31 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790489177 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1790489177
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2452936608
Short name T830
Test name
Test status
Simulation time 2842105757 ps
CPU time 24.63 seconds
Started Oct 09 05:07:55 AM UTC 24
Finished Oct 09 05:08:21 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452936608 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2452936608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2329039340
Short name T821
Test name
Test status
Simulation time 29782485 ps
CPU time 3.86 seconds
Started Oct 09 05:07:54 AM UTC 24
Finished Oct 09 05:08:00 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329039340 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2329039340
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.100501459
Short name T883
Test name
Test status
Simulation time 4790126397 ps
CPU time 176.25 seconds
Started Oct 09 05:08:10 AM UTC 24
Finished Oct 09 05:11:09 AM UTC 24
Peak memory 219992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100501459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.100501459
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2715514943
Short name T838
Test name
Test status
Simulation time 177759225 ps
CPU time 16.7 seconds
Started Oct 09 05:08:12 AM UTC 24
Finished Oct 09 05:08:30 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715514943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2715514943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1202077613
Short name T865
Test name
Test status
Simulation time 345322714 ps
CPU time 76.5 seconds
Started Oct 09 05:08:10 AM UTC 24
Finished Oct 09 05:09:28 AM UTC 24
Peak memory 220060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202077613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.1202077613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.286298344
Short name T892
Test name
Test status
Simulation time 3308841600 ps
CPU time 260.87 seconds
Started Oct 09 05:08:14 AM UTC 24
Finished Oct 09 05:12:39 AM UTC 24
Peak memory 232628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286298344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.286298344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3238393868
Short name T837
Test name
Test status
Simulation time 346269831 ps
CPU time 18.78 seconds
Started Oct 09 05:08:07 AM UTC 24
Finished Oct 09 05:08:27 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238393868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3238393868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.843261096
Short name T862
Test name
Test status
Simulation time 1009027258 ps
CPU time 47.63 seconds
Started Oct 09 05:08:29 AM UTC 24
Finished Oct 09 05:09:18 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843261096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.843261096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3511900763
Short name T183
Test name
Test status
Simulation time 40203373282 ps
CPU time 422.83 seconds
Started Oct 09 05:08:31 AM UTC 24
Finished Oct 09 05:15:40 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511900763 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3511900763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.544055940
Short name T850
Test name
Test status
Simulation time 206649453 ps
CPU time 15.16 seconds
Started Oct 09 05:08:44 AM UTC 24
Finished Oct 09 05:09:00 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544055940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.544055940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3839869986
Short name T845
Test name
Test status
Simulation time 135942103 ps
CPU time 15.11 seconds
Started Oct 09 05:08:35 AM UTC 24
Finished Oct 09 05:08:52 AM UTC 24
Peak memory 216024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839869986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3839869986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2402379319
Short name T848
Test name
Test status
Simulation time 490943061 ps
CPU time 26.06 seconds
Started Oct 09 05:08:28 AM UTC 24
Finished Oct 09 05:08:56 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402379319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2402379319
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3691581819
Short name T895
Test name
Test status
Simulation time 93830314175 ps
CPU time 298.2 seconds
Started Oct 09 05:08:29 AM UTC 24
Finished Oct 09 05:13:31 AM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691581819 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3691581819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2348558607
Short name T864
Test name
Test status
Simulation time 7193771732 ps
CPU time 56.88 seconds
Started Oct 09 05:08:29 AM UTC 24
Finished Oct 09 05:09:27 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348558607 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2348558607
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.560229046
Short name T846
Test name
Test status
Simulation time 198899952 ps
CPU time 21.89 seconds
Started Oct 09 05:08:28 AM UTC 24
Finished Oct 09 05:08:52 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560229046 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.560229046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1504799529
Short name T851
Test name
Test status
Simulation time 1053153819 ps
CPU time 26 seconds
Started Oct 09 05:08:32 AM UTC 24
Finished Oct 09 05:09:00 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504799529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1504799529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.4130758704
Short name T831
Test name
Test status
Simulation time 216295186 ps
CPU time 4.72 seconds
Started Oct 09 05:08:16 AM UTC 24
Finished Oct 09 05:08:22 AM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130758704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4130758704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2160917394
Short name T858
Test name
Test status
Simulation time 5720327363 ps
CPU time 47.05 seconds
Started Oct 09 05:08:24 AM UTC 24
Finished Oct 09 05:09:13 AM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160917394 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2160917394
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3720885853
Short name T847
Test name
Test status
Simulation time 3852835613 ps
CPU time 29.31 seconds
Started Oct 09 05:08:24 AM UTC 24
Finished Oct 09 05:08:54 AM UTC 24
Peak memory 216008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720885853 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3720885853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1240532118
Short name T835
Test name
Test status
Simulation time 43180657 ps
CPU time 3.47 seconds
Started Oct 09 05:08:22 AM UTC 24
Finished Oct 09 05:08:27 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240532118 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1240532118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2163812329
Short name T866
Test name
Test status
Simulation time 1481227961 ps
CPU time 43.86 seconds
Started Oct 09 05:08:44 AM UTC 24
Finished Oct 09 05:09:29 AM UTC 24
Peak memory 217880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163812329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2163812329
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.131555485
Short name T875
Test name
Test status
Simulation time 975530685 ps
CPU time 104.01 seconds
Started Oct 09 05:08:51 AM UTC 24
Finished Oct 09 05:10:37 AM UTC 24
Peak memory 219936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131555485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.131555485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.364842844
Short name T888
Test name
Test status
Simulation time 1740477131 ps
CPU time 184.6 seconds
Started Oct 09 05:08:46 AM UTC 24
Finished Oct 09 05:11:54 AM UTC 24
Peak memory 221980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364842844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.364842844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.987848442
Short name T859
Test name
Test status
Simulation time 24476977 ps
CPU time 18.85 seconds
Started Oct 09 05:08:54 AM UTC 24
Finished Oct 09 05:09:14 AM UTC 24
Peak memory 217868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987848442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.987848442
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.3485017034
Short name T861
Test name
Test status
Simulation time 704862175 ps
CPU time 38.54 seconds
Started Oct 09 05:08:38 AM UTC 24
Finished Oct 09 05:09:18 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485017034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3485017034
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1256752389
Short name T92
Test name
Test status
Simulation time 885984544 ps
CPU time 23.49 seconds
Started Oct 09 04:47:00 AM UTC 24
Finished Oct 09 04:47:25 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256752389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1256752389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3500283049
Short name T322
Test name
Test status
Simulation time 10502669439 ps
CPU time 91.49 seconds
Started Oct 09 04:47:00 AM UTC 24
Finished Oct 09 04:48:34 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500283049 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.3500283049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.829000151
Short name T304
Test name
Test status
Simulation time 769300313 ps
CPU time 34.33 seconds
Started Oct 09 04:47:07 AM UTC 24
Finished Oct 09 04:47:43 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829000151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.829000151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1097633727
Short name T104
Test name
Test status
Simulation time 531160478 ps
CPU time 15.65 seconds
Started Oct 09 04:47:04 AM UTC 24
Finished Oct 09 04:47:21 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097633727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1097633727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.584239850
Short name T217
Test name
Test status
Simulation time 31556391 ps
CPU time 5.92 seconds
Started Oct 09 04:46:56 AM UTC 24
Finished Oct 09 04:47:03 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584239850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.584239850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.4036671618
Short name T354
Test name
Test status
Simulation time 63959337525 ps
CPU time 270.48 seconds
Started Oct 09 04:46:57 AM UTC 24
Finished Oct 09 04:51:32 AM UTC 24
Peak memory 217940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036671618 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4036671618
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1537714331
Short name T190
Test name
Test status
Simulation time 16356727237 ps
CPU time 50.61 seconds
Started Oct 09 04:47:00 AM UTC 24
Finished Oct 09 04:47:53 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537714331 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1537714331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4151589289
Short name T330
Test name
Test status
Simulation time 211195668 ps
CPU time 11.79 seconds
Started Oct 09 04:46:57 AM UTC 24
Finished Oct 09 04:47:10 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151589289 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4151589289
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.490488508
Short name T333
Test name
Test status
Simulation time 2041372312 ps
CPU time 29.91 seconds
Started Oct 09 04:47:01 AM UTC 24
Finished Oct 09 04:47:33 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490488508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.490488508
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3915403146
Short name T208
Test name
Test status
Simulation time 934691783 ps
CPU time 7.45 seconds
Started Oct 09 04:46:51 AM UTC 24
Finished Oct 09 04:47:00 AM UTC 24
Peak memory 216000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915403146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3915403146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.419895399
Short name T335
Test name
Test status
Simulation time 11086715176 ps
CPU time 45.06 seconds
Started Oct 09 04:46:56 AM UTC 24
Finished Oct 09 04:47:42 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419895399 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.419895399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1206346514
Short name T107
Test name
Test status
Simulation time 9041032929 ps
CPU time 34.54 seconds
Started Oct 09 04:46:56 AM UTC 24
Finished Oct 09 04:47:32 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206346514 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1206346514
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.33696025
Short name T90
Test name
Test status
Simulation time 34040082 ps
CPU time 4.29 seconds
Started Oct 09 04:46:53 AM UTC 24
Finished Oct 09 04:46:59 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33696025 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.33696025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.4168410580
Short name T101
Test name
Test status
Simulation time 3222431566 ps
CPU time 178.03 seconds
Started Oct 09 04:47:08 AM UTC 24
Finished Oct 09 04:50:10 AM UTC 24
Peak memory 219992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168410580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4168410580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2453447930
Short name T316
Test name
Test status
Simulation time 6045691639 ps
CPU time 165.46 seconds
Started Oct 09 04:47:10 AM UTC 24
Finished Oct 09 04:49:59 AM UTC 24
Peak memory 220000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453447930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2453447930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3058413188
Short name T48
Test name
Test status
Simulation time 6132501389 ps
CPU time 195.6 seconds
Started Oct 09 04:47:14 AM UTC 24
Finished Oct 09 04:50:33 AM UTC 24
Peak memory 222044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058413188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3058413188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.3303099201
Short name T56
Test name
Test status
Simulation time 232068720 ps
CPU time 12.52 seconds
Started Oct 09 04:47:06 AM UTC 24
Finished Oct 09 04:47:19 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303099201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3303099201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.905079245
Short name T582
Test name
Test status
Simulation time 112034903150 ps
CPU time 778.98 seconds
Started Oct 09 04:47:28 AM UTC 24
Finished Oct 09 05:00:36 AM UTC 24
Peak memory 221576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905079245 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.905079245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4051137131
Short name T108
Test name
Test status
Simulation time 463456904 ps
CPU time 22.76 seconds
Started Oct 09 04:47:33 AM UTC 24
Finished Oct 09 04:47:57 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051137131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4051137131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1867259559
Short name T159
Test name
Test status
Simulation time 39768594997 ps
CPU time 344.89 seconds
Started Oct 09 04:47:26 AM UTC 24
Finished Oct 09 04:53:16 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867259559 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1867259559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.908596509
Short name T254
Test name
Test status
Simulation time 19059200949 ps
CPU time 89.06 seconds
Started Oct 09 04:47:26 AM UTC 24
Finished Oct 09 04:48:58 AM UTC 24
Peak memory 216024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908596509 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.908596509
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.1041048910
Short name T332
Test name
Test status
Simulation time 43636744 ps
CPU time 6.48 seconds
Started Oct 09 04:47:25 AM UTC 24
Finished Oct 09 04:47:33 AM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041048910 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1041048910
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1733660767
Short name T114
Test name
Test status
Simulation time 6072202404 ps
CPU time 44.65 seconds
Started Oct 09 04:47:31 AM UTC 24
Finished Oct 09 04:48:17 AM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733660767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1733660767
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2396100955
Short name T106
Test name
Test status
Simulation time 248465419 ps
CPU time 6.25 seconds
Started Oct 09 04:47:18 AM UTC 24
Finished Oct 09 04:47:25 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396100955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2396100955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2707033038
Short name T109
Test name
Test status
Simulation time 7107284922 ps
CPU time 40.78 seconds
Started Oct 09 04:47:19 AM UTC 24
Finished Oct 09 04:48:01 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707033038 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2707033038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.406448469
Short name T340
Test name
Test status
Simulation time 5847024298 ps
CPU time 73.13 seconds
Started Oct 09 04:47:20 AM UTC 24
Finished Oct 09 04:48:35 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406448469 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.406448469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2563453031
Short name T105
Test name
Test status
Simulation time 153494978 ps
CPU time 3.82 seconds
Started Oct 09 04:47:19 AM UTC 24
Finished Oct 09 04:47:24 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563453031 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2563453031
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.192418844
Short name T59
Test name
Test status
Simulation time 7592425418 ps
CPU time 222.21 seconds
Started Oct 09 04:47:35 AM UTC 24
Finished Oct 09 04:51:21 AM UTC 24
Peak memory 219992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192418844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.192418844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.861206670
Short name T37
Test name
Test status
Simulation time 457670957 ps
CPU time 70.99 seconds
Started Oct 09 04:47:41 AM UTC 24
Finished Oct 09 04:48:54 AM UTC 24
Peak memory 219932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861206670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.861206670
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2309712220
Short name T334
Test name
Test status
Simulation time 7178171 ps
CPU time 1.44 seconds
Started Oct 09 04:47:38 AM UTC 24
Finished Oct 09 04:47:40 AM UTC 24
Peak memory 203356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309712220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2309712220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.339804236
Short name T51
Test name
Test status
Simulation time 1095124005 ps
CPU time 295.63 seconds
Started Oct 09 04:47:42 AM UTC 24
Finished Oct 09 04:52:42 AM UTC 24
Peak memory 222016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339804236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.339804236
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.155559065
Short name T36
Test name
Test status
Simulation time 2397807164 ps
CPU time 33.59 seconds
Started Oct 09 04:47:33 AM UTC 24
Finished Oct 09 04:48:08 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155559065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.155559065
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.167599788
Short name T307
Test name
Test status
Simulation time 77406871333 ps
CPU time 301.8 seconds
Started Oct 09 04:47:58 AM UTC 24
Finished Oct 09 04:53:04 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167599788 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.167599788
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3927711323
Short name T113
Test name
Test status
Simulation time 43668675 ps
CPU time 3.84 seconds
Started Oct 09 04:48:10 AM UTC 24
Finished Oct 09 04:48:15 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927711323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3927711323
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.4124116259
Short name T232
Test name
Test status
Simulation time 1043796760 ps
CPU time 47.52 seconds
Started Oct 09 04:48:02 AM UTC 24
Finished Oct 09 04:48:51 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124116259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4124116259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1606371445
Short name T112
Test name
Test status
Simulation time 132604468 ps
CPU time 19.3 seconds
Started Oct 09 04:47:52 AM UTC 24
Finished Oct 09 04:48:13 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606371445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1606371445
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.1401401869
Short name T296
Test name
Test status
Simulation time 35091127280 ps
CPU time 131.77 seconds
Started Oct 09 04:47:54 AM UTC 24
Finished Oct 09 04:50:09 AM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401401869 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1401401869
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4184636310
Short name T209
Test name
Test status
Simulation time 2664865499 ps
CPU time 48.03 seconds
Started Oct 09 04:47:56 AM UTC 24
Finished Oct 09 04:48:45 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184636310 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4184636310
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3598203124
Short name T111
Test name
Test status
Simulation time 135969628 ps
CPU time 14.53 seconds
Started Oct 09 04:47:53 AM UTC 24
Finished Oct 09 04:48:09 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598203124 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3598203124
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.783976938
Short name T115
Test name
Test status
Simulation time 1068832906 ps
CPU time 19.49 seconds
Started Oct 09 04:47:59 AM UTC 24
Finished Oct 09 04:48:20 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783976938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.783976938
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.638198151
Short name T303
Test name
Test status
Simulation time 296410218 ps
CPU time 6.96 seconds
Started Oct 09 04:47:43 AM UTC 24
Finished Oct 09 04:47:51 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638198151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.638198151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.498558126
Short name T338
Test name
Test status
Simulation time 14553273303 ps
CPU time 34.65 seconds
Started Oct 09 04:47:48 AM UTC 24
Finished Oct 09 04:48:24 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498558126 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.498558126
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2754984004
Short name T321
Test name
Test status
Simulation time 4627604177 ps
CPU time 49.84 seconds
Started Oct 09 04:47:49 AM UTC 24
Finished Oct 09 04:48:40 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754984004 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2754984004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.299192380
Short name T336
Test name
Test status
Simulation time 22331927 ps
CPU time 3.49 seconds
Started Oct 09 04:47:43 AM UTC 24
Finished Oct 09 04:47:48 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299192380 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.299192380
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1342576397
Short name T103
Test name
Test status
Simulation time 8594922863 ps
CPU time 167.18 seconds
Started Oct 09 04:48:10 AM UTC 24
Finished Oct 09 04:51:00 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342576397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1342576397
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.278762322
Short name T258
Test name
Test status
Simulation time 3156310707 ps
CPU time 44.2 seconds
Started Oct 09 04:48:14 AM UTC 24
Finished Oct 09 04:49:00 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278762322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.278762322
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2064657714
Short name T34
Test name
Test status
Simulation time 5395766723 ps
CPU time 238 seconds
Started Oct 09 04:48:15 AM UTC 24
Finished Oct 09 04:52:17 AM UTC 24
Peak memory 222516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064657714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2064657714
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.3292565112
Short name T230
Test name
Test status
Simulation time 259954061 ps
CPU time 37.44 seconds
Started Oct 09 04:48:07 AM UTC 24
Finished Oct 09 04:48:46 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292565112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3292565112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1294061736
Short name T95
Test name
Test status
Simulation time 1174466015 ps
CPU time 53.44 seconds
Started Oct 09 04:48:26 AM UTC 24
Finished Oct 09 04:49:21 AM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294061736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1294061736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.904811269
Short name T139
Test name
Test status
Simulation time 19627622052 ps
CPU time 139.2 seconds
Started Oct 09 04:48:35 AM UTC 24
Finished Oct 09 04:50:58 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904811269 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.904811269
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3080740965
Short name T231
Test name
Test status
Simulation time 41698454 ps
CPU time 3.7 seconds
Started Oct 09 04:48:41 AM UTC 24
Finished Oct 09 04:48:46 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080740965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3080740965
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.4050966671
Short name T342
Test name
Test status
Simulation time 51388636 ps
CPU time 3.96 seconds
Started Oct 09 04:48:37 AM UTC 24
Finished Oct 09 04:48:43 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050966671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.4050966671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1017183102
Short name T341
Test name
Test status
Simulation time 191322959 ps
CPU time 13.93 seconds
Started Oct 09 04:48:21 AM UTC 24
Finished Oct 09 04:48:37 AM UTC 24
Peak memory 216028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017183102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1017183102
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.3927089862
Short name T257
Test name
Test status
Simulation time 3110757633 ps
CPU time 31.33 seconds
Started Oct 09 04:48:25 AM UTC 24
Finished Oct 09 04:48:58 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927089862 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3927089862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3747270957
Short name T367
Test name
Test status
Simulation time 28027316039 ps
CPU time 243.85 seconds
Started Oct 09 04:48:25 AM UTC 24
Finished Oct 09 04:52:33 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747270957 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3747270957
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.2877367517
Short name T218
Test name
Test status
Simulation time 791260621 ps
CPU time 25.01 seconds
Started Oct 09 04:48:25 AM UTC 24
Finished Oct 09 04:48:51 AM UTC 24
Peak memory 216020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877367517 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2877367517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.1500464713
Short name T343
Test name
Test status
Simulation time 203033209 ps
CPU time 6.77 seconds
Started Oct 09 04:48:36 AM UTC 24
Finished Oct 09 04:48:45 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500464713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1500464713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3327266965
Short name T252
Test name
Test status
Simulation time 159413890 ps
CPU time 4.81 seconds
Started Oct 09 04:48:18 AM UTC 24
Finished Oct 09 04:48:24 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327266965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3327266965
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1766285383
Short name T220
Test name
Test status
Simulation time 12633060770 ps
CPU time 64.5 seconds
Started Oct 09 04:48:21 AM UTC 24
Finished Oct 09 04:49:28 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766285383 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1766285383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2857638521
Short name T260
Test name
Test status
Simulation time 4150224299 ps
CPU time 45.22 seconds
Started Oct 09 04:48:21 AM UTC 24
Finished Oct 09 04:49:08 AM UTC 24
Peak memory 216076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857638521 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2857638521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3019699745
Short name T339
Test name
Test status
Simulation time 36981879 ps
CPU time 3.51 seconds
Started Oct 09 04:48:20 AM UTC 24
Finished Oct 09 04:48:24 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019699745 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3019699745
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.3860223174
Short name T313
Test name
Test status
Simulation time 18610102590 ps
CPU time 373.55 seconds
Started Oct 09 04:48:42 AM UTC 24
Finished Oct 09 04:55:01 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860223174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3860223174
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.414784829
Short name T223
Test name
Test status
Simulation time 219876355 ps
CPU time 48.84 seconds
Started Oct 09 04:48:45 AM UTC 24
Finished Oct 09 04:49:36 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414784829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.414784829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3988179866
Short name T50
Test name
Test status
Simulation time 880746079 ps
CPU time 221.12 seconds
Started Oct 09 04:48:47 AM UTC 24
Finished Oct 09 04:52:32 AM UTC 24
Peak memory 232568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988179866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3988179866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1316638710
Short name T259
Test name
Test status
Simulation time 109128455 ps
CPU time 20.34 seconds
Started Oct 09 04:48:41 AM UTC 24
Finished Oct 09 04:49:03 AM UTC 24
Peak memory 217876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316638710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1316638710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1875535304
Short name T100
Test name
Test status
Simulation time 4865536780 ps
CPU time 47.64 seconds
Started Oct 09 04:48:56 AM UTC 24
Finished Oct 09 04:49:45 AM UTC 24
Peak memory 217944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875535304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1875535304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2627914758
Short name T279
Test name
Test status
Simulation time 110956471485 ps
CPU time 359.49 seconds
Started Oct 09 04:48:59 AM UTC 24
Finished Oct 09 04:55:03 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627914758 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2627914758
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3755946844
Short name T221
Test name
Test status
Simulation time 492144137 ps
CPU time 25.15 seconds
Started Oct 09 04:49:05 AM UTC 24
Finished Oct 09 04:49:32 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755946844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3755946844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.932479719
Short name T125
Test name
Test status
Simulation time 1420600444 ps
CPU time 41.32 seconds
Started Oct 09 04:49:01 AM UTC 24
Finished Oct 09 04:49:44 AM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932479719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.932479719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.3185518827
Short name T188
Test name
Test status
Simulation time 819532957 ps
CPU time 31.4 seconds
Started Oct 09 04:48:53 AM UTC 24
Finished Oct 09 04:49:26 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185518827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3185518827
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1090909063
Short name T419
Test name
Test status
Simulation time 51423924306 ps
CPU time 334.19 seconds
Started Oct 09 04:48:54 AM UTC 24
Finished Oct 09 04:54:34 AM UTC 24
Peak memory 218072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090909063 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1090909063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2019889939
Short name T158
Test name
Test status
Simulation time 28237290960 ps
CPU time 255.74 seconds
Started Oct 09 04:48:56 AM UTC 24
Finished Oct 09 04:53:16 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019889939 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2019889939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.2057237758
Short name T262
Test name
Test status
Simulation time 164546120 ps
CPU time 23.95 seconds
Started Oct 09 04:48:54 AM UTC 24
Finished Oct 09 04:49:20 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057237758 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2057237758
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3217530939
Short name T99
Test name
Test status
Simulation time 1905861853 ps
CPU time 41.93 seconds
Started Oct 09 04:48:59 AM UTC 24
Finished Oct 09 04:49:42 AM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217530939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3217530939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2616111285
Short name T187
Test name
Test status
Simulation time 145493304 ps
CPU time 5.11 seconds
Started Oct 09 04:48:47 AM UTC 24
Finished Oct 09 04:48:53 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616111285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2616111285
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4068238242
Short name T222
Test name
Test status
Simulation time 6209549219 ps
CPU time 38.74 seconds
Started Oct 09 04:48:52 AM UTC 24
Finished Oct 09 04:49:32 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068238242 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4068238242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1810903175
Short name T210
Test name
Test status
Simulation time 8561515993 ps
CPU time 29.71 seconds
Started Oct 09 04:48:52 AM UTC 24
Finished Oct 09 04:49:23 AM UTC 24
Peak memory 215880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810903175 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1810903175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3251174878
Short name T233
Test name
Test status
Simulation time 49279966 ps
CPU time 4.37 seconds
Started Oct 09 04:48:47 AM UTC 24
Finished Oct 09 04:48:52 AM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251174878 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3251174878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1025737887
Short name T121
Test name
Test status
Simulation time 8302587832 ps
CPU time 286.12 seconds
Started Oct 09 04:49:09 AM UTC 24
Finished Oct 09 04:54:00 AM UTC 24
Peak memory 219996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025737887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1025737887
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2438840834
Short name T349
Test name
Test status
Simulation time 3682712317 ps
CPU time 130.64 seconds
Started Oct 09 04:49:11 AM UTC 24
Finished Oct 09 04:51:24 AM UTC 24
Peak memory 220000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438840834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2438840834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3536731038
Short name T127
Test name
Test status
Simulation time 270203692 ps
CPU time 36.94 seconds
Started Oct 09 04:49:11 AM UTC 24
Finished Oct 09 04:49:49 AM UTC 24
Peak memory 217884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536731038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3536731038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2694659606
Short name T39
Test name
Test status
Simulation time 252035497 ps
CPU time 104.77 seconds
Started Oct 09 04:49:19 AM UTC 24
Finished Oct 09 04:51:06 AM UTC 24
Peak memory 219940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694659606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.2694659606
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.4231050402
Short name T261
Test name
Test status
Simulation time 836813751 ps
CPU time 13.22 seconds
Started Oct 09 04:49:04 AM UTC 24
Finished Oct 09 04:49:18 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231050402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4231050402
Directory /workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest
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