Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1568490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249611

1

T1

12

T2

19

T3

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617335	1			T1	34		T2	34		T3	140
values[0x0]	583191	1			T1	35		T2	44		T3	127
values[0x1]	617575	1			T1	31		T2	33		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1211786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606315

1

T1

27

T2

40

T3

142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29004	1			T2	3		T3	10		T8	18
valid_sources[0x01]	28505	1			T3	13		T8	18		T9	58
valid_sources[0x02]	29388	1			T1	9		T3	5		T8	29
valid_sources[0x03]	28458	1			T2	3		T8	3		T9	43
valid_sources[0x04]	28202	1			T1	1		T3	8		T8	20
valid_sources[0x05]	28699	1			T2	2		T3	4		T8	14
valid_sources[0x06]	28616	1			T1	1		T3	4		T8	44
valid_sources[0x07]	28872	1			T3	6		T8	7		T9	11
valid_sources[0x08]	26777	1			T1	2		T3	6		T8	15
valid_sources[0x09]	28410	1			T1	3		T2	4		T3	8
valid_sources[0x0a]	27754	1			T3	5		T8	21		T9	19
valid_sources[0x0b]	28604	1			T3	6		T8	18		T10	2
valid_sources[0x0c]	28183	1			T1	3		T2	7		T3	11
valid_sources[0x0d]	28616	1			T2	1		T3	9		T8	22
valid_sources[0x0e]	29470	1			T3	8		T8	3		T10	3
valid_sources[0x0f]	28634	1			T3	10		T8	12		T9	14
valid_sources[0x10]	28371	1			T3	1		T8	12		T9	5
valid_sources[0x11]	28383	1			T2	5		T3	7		T8	9
valid_sources[0x12]	28394	1			T2	8		T3	4		T8	8
valid_sources[0x13]	27123	1			T1	3		T3	5		T8	10
valid_sources[0x14]	27529	1			T2	1		T3	1		T8	6
valid_sources[0x15]	28809	1			T3	3		T8	11		T11	4
valid_sources[0x16]	28935	1			T2	2		T3	3		T8	21
valid_sources[0x17]	28044	1			T1	6		T2	6		T3	12
valid_sources[0x18]	28038	1			T1	2		T2	2		T3	9
valid_sources[0x19]	27739	1			T3	8		T8	11		T9	6
valid_sources[0x1a]	28427	1			T8	10		T9	17		T10	4
valid_sources[0x1b]	28668	1			T3	9		T8	17		T9	11
valid_sources[0x1c]	27452	1			T2	1		T3	7		T8	15
valid_sources[0x1d]	27717	1			T2	6		T3	2		T8	6
valid_sources[0x1e]	28189	1			T1	1		T2	4		T3	10
valid_sources[0x1f]	27404	1			T1	3		T3	7		T8	24
valid_sources[0x20]	27782	1			T1	6		T2	4		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26361

1

T1

1

T2

1

T3

7

values[0x0]

all_enables

biggest_size

196832

1

T1

10

T2

17

T3

41

values[0x1]

all_enables

biggest_size

26418

1

T1

1

T2

1

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1587949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258376

1

T1

32

T2

21

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632720	1			T1	56		T2	63		T3	172
values[0x0]	580747	1			T1	59		T2	71		T3	190
values[0x1]	632858	1			T1	62		T2	55		T3	176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1218545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

627780

1

T1

61

T2

61

T3

186

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28590	1			T1	4		T2	2		T8	8
valid_sources[0x01]	28319	1			T2	4		T3	9		T8	10
valid_sources[0x02]	29301	1			T1	7		T2	3		T3	10
valid_sources[0x03]	29264	1			T1	1		T2	1		T8	17
valid_sources[0x04]	28668	1			T2	3		T3	7		T8	5
valid_sources[0x05]	28997	1			T1	8		T2	1		T3	1
valid_sources[0x06]	28849	1			T1	4		T2	7		T3	3
valid_sources[0x07]	28200	1			T1	3		T2	3		T3	10
valid_sources[0x08]	28339	1			T1	4		T2	1		T3	21
valid_sources[0x09]	28799	1			T1	4		T2	1		T3	24
valid_sources[0x0a]	28365	1			T1	4		T3	7		T8	17
valid_sources[0x0b]	28222	1			T1	3		T2	4		T8	4
valid_sources[0x0c]	28551	1			T1	3		T3	1		T8	13
valid_sources[0x0d]	28293	1			T1	7		T2	2		T3	16
valid_sources[0x0e]	29376	1			T1	4		T2	2		T3	13
valid_sources[0x0f]	29526	1			T1	3		T2	4		T8	19
valid_sources[0x10]	28875	1			T1	1		T2	4		T3	10
valid_sources[0x11]	28854	1			T1	3		T2	1		T3	7
valid_sources[0x12]	28339	1			T1	4		T2	1		T3	3
valid_sources[0x13]	29303	1			T2	10		T3	4		T8	3
valid_sources[0x14]	28523	1			T1	4		T2	2		T3	12
valid_sources[0x15]	28640	1			T1	2		T2	4		T3	11
valid_sources[0x16]	28585	1			T1	1		T2	2		T3	9
valid_sources[0x17]	29206	1			T1	1		T2	4		T3	13
valid_sources[0x18]	29512	1			T1	2		T2	2		T3	6
valid_sources[0x19]	28169	1			T1	8		T2	1		T3	7
valid_sources[0x1a]	28365	1			T1	6		T2	5		T3	3
valid_sources[0x1b]	28697	1			T1	7		T2	1		T3	6
valid_sources[0x1c]	28377	1			T1	8		T2	4		T8	6
valid_sources[0x1d]	28437	1			T1	3		T2	3		T3	25
valid_sources[0x1e]	28656	1			T1	3		T2	3		T3	2
valid_sources[0x1f]	28617	1			T1	2		T2	3		T3	8
valid_sources[0x20]	28489	1			T1	5		T2	2		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27148

1

T1

5

T2

1

T3

4

values[0x0]

all_enables

biggest_size

204116

1

T1

25

T2

18

T3

64

values[0x1]

all_enables

biggest_size

27112

1

T1

2

T2

2

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1584643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251992

1

T1

16

T2

19

T3

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	623467	1			T1	46		T2	70		T3	149
values[0x0]	589349	1			T1	50		T2	57		T3	147
values[0x1]	623819	1			T1	50		T2	68		T3	160

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1224163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

612472

1

T1

36

T2

54

T3

139

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28892	1			T2	1		T3	13		T8	15
valid_sources[0x01]	27533	1			T2	3		T3	9		T8	16
valid_sources[0x02]	28756	1			T1	1		T2	4		T3	6
valid_sources[0x03]	29002	1			T1	3		T2	6		T8	21
valid_sources[0x04]	28581	1			T2	5		T3	5		T8	17
valid_sources[0x05]	28790	1			T1	4		T2	4		T3	12
valid_sources[0x06]	28971	1			T1	1		T3	8		T8	10
valid_sources[0x07]	28146	1			T1	5		T2	1		T3	5
valid_sources[0x08]	28182	1			T1	7		T2	5		T3	9
valid_sources[0x09]	28365	1			T1	4		T2	3		T3	6
valid_sources[0x0a]	28028	1			T1	3		T2	1		T3	7
valid_sources[0x0b]	29682	1			T2	2		T3	9		T8	8
valid_sources[0x0c]	27754	1			T1	6		T2	2		T3	7
valid_sources[0x0d]	28224	1			T1	4		T2	5		T3	9
valid_sources[0x0e]	29760	1			T1	1		T2	3		T3	7
valid_sources[0x0f]	28597	1			T1	6		T2	3		T3	7
valid_sources[0x10]	28625	1			T2	6		T3	7		T8	12
valid_sources[0x11]	28656	1			T1	5		T2	2		T3	1
valid_sources[0x12]	29022	1			T2	5		T3	2		T8	9
valid_sources[0x13]	28869	1			T1	1		T2	3		T3	6
valid_sources[0x14]	28865	1			T1	1		T2	5		T3	6
valid_sources[0x15]	28740	1			T1	10		T2	5		T3	5
valid_sources[0x16]	28110	1			T1	6		T2	2		T3	5
valid_sources[0x17]	29140	1			T1	3		T2	1		T3	9
valid_sources[0x18]	29201	1			T1	3		T2	4		T3	12
valid_sources[0x19]	29560	1			T2	4		T3	7		T8	19
valid_sources[0x1a]	28323	1			T2	2		T3	10		T8	20
valid_sources[0x1b]	28481	1			T2	4		T3	8		T8	27
valid_sources[0x1c]	28029	1			T2	8		T3	5		T8	9
valid_sources[0x1d]	29058	1			T1	3		T2	3		T3	7
valid_sources[0x1e]	28373	1			T1	6		T2	1		T3	4
valid_sources[0x1f]	28250	1			T2	4		T3	6		T8	10
valid_sources[0x20]	29015	1			T2	3		T3	8		T8	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26588

1

T1

2

T2

2

T3

5

values[0x0]

all_enables

biggest_size

198912

1

T1

14

T2

13

T3

49

values[0x1]

all_enables

biggest_size

26492

1

T2

4

T3

6

T8

14