Unified Coverage Report :: Module

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8089425	0	0
GntImpliesValid_A	2147483647	8089425	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8089425	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	292457545	0	0
ReadyAndValidImplyGrant_A	2147483647	8089425	0	0
ReqAndReadyImplyGrant_A	2147483647	8089425	0	0
ReqImpliesValid_A	2147483647	28723169	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50085	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8089425	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	268560	267360
T2	50952	50280
T3	420336	419112
T7	458832	458256
T8	105648	105336
T9	111768	111576
T10	239208	238344
T11	59928	58656
T12	1021560	1020192
T13	842256	841128

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	21600	21600
T1	24	24
T2	24	24
T3	24	24
T7	24	24
T8	24	24
T9	24	24
T10	24	24
T11	24	24
T12	24	24
T13	24	24

GntImpliesReady_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

GntImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

GrantKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	268560	267360
T2	50952	50280
T3	420336	419112
T7	458832	458256
T8	105648	105336
T9	111768	111576
T10	239208	238344
T11	59928	58656
T12	1021560	1020192
T13	842256	841128

IdxKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	268560	267360
T2	50952	50280
T3	420336	419112
T7	458832	458256
T8	105648	105336
T9	111768	111576
T10	239208	238344
T11	59928	58656
T12	1021560	1020192
T13	842256	841128

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	2147483647	292457545
T1	268560	12756
T2	50952	565
T3	420336	26449
T7	458832	29646
T8	105648	2755
T9	111768	1985
T10	239208	11357
T11	59928	721
T12	1021560	56707
T13	842256	50219

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	28723169
T1	268560	1017
T2	50952	555
T3	420336	3824
T7	458832	4273
T8	105648	3063
T9	111768	1902
T10	239208	938
T11	59928	616
T12	1021560	5883
T13	842256	4917

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	2147483647	50085	21600
T4	30662	0	2
T7	38236	0	2
T8	8804	15	2
T9	9314	4	2
T10	19934	0	2
T11	4994	0	2
T12	85130	2	2
T13	70188	0	2
T14	0	2	0
T15	0	14	0
T16	0	42	0
T17	0	16	0
T18	0	8	0
T19	0	20	0
T20	0	21	0
T21	0	1	0
T22	0	515	0
T23	0	20	0
T24	0	7	0
T25	548618	0	2
T26	23248	0	2

ValidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	268560	267360
T2	50952	50280
T3	420336	419112
T7	458832	458256
T8	105648	105336
T9	111768	111576
T10	239208	238344
T11	59928	58656
T12	1021560	1020192
T13	842256	841128

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	2147483647	8089425
T1	268560	423
T2	50952	494
T3	420336	1413
T7	458832	1927
T8	105648	2672
T9	111768	1863
T10	239208	390
T11	59928	528
T12	1021560	2790
T13	842256	2316

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	907522	0	0
GntImpliesValid_A	260875270	907522	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	907522	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	8666740	0	0
ReadyAndValidImplyGrant_A	260875270	907522	0	0
ReqAndReadyImplyGrant_A	260875270	907522	0	0
ReqImpliesValid_A	260875270	2144278	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	907522	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	8666740
T1	11190	384
T2	2123	48
T3	17514	1107
T7	19118	1687
T8	4402	236
T9	4657	217
T10	9967	285
T11	2497	53
T12	42565	2363
T13	35094	1760

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	2144278
T1	11190	74
T2	2123	67
T3	17514	294
T7	19118	361
T8	4402	395
T9	4657	236
T10	9967	41
T11	2497	102
T12	42565	458
T13	35094	325

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	907522
T1	11190	50
T2	2123	57
T3	17514	168
T7	19118	226
T8	4402	315
T9	4657	226
T10	9967	40
T11	2497	77
T12	42565	304
T13	35094	237

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	909739	0	0
GntImpliesValid_A	260875270	909739	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	909739	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	8630237	0	0
ReadyAndValidImplyGrant_A	260875270	909739	0	0
ReqAndReadyImplyGrant_A	260875270	909739	0	0
ReqImpliesValid_A	260875270	2145513	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	909739	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	8630237
T1	11190	400
T2	2123	47
T3	17514	1140
T7	19118	1619
T8	4402	235
T9	4657	192
T10	9967	270
T11	2497	41
T12	42565	2149
T13	35094	1920

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	2145513
T1	11190	76
T2	2123	74
T3	17514	304
T7	19118	408
T8	4402	416
T9	4657	201
T10	9967	47
T11	2497	78
T12	42565	580
T13	35094	401

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	909739
T1	11190	54
T2	2123	60
T3	17514	163
T7	19118	218
T8	4402	325
T9	4657	196
T10	9967	40
T11	2497	59
T12	42565	304
T13	35094	265

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T8 T7 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T7,T12

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T7,T12
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	209814	0	0
GntImpliesValid_A	260875270	209814	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	209814	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2080667	0	0
ReadyAndValidImplyGrant_A	260875270	209814	0	0
ReqAndReadyImplyGrant_A	260875270	209814	0	0
ReqImpliesValid_A	260875270	472970	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	209814	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2080667
T1	11190	86
T2	2123	16
T3	17514	179
T7	19118	351
T8	4402	77
T9	4657	56
T10	9967	82
T11	2497	13
T12	42565	611
T13	35094	448

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	472970
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	65
T8	4402	84
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	115
T13	35094	61

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	209814
T1	11190	13
T2	2123	15
T3	17514	25
T7	19118	44
T8	4402	80
T9	4657	55
T10	9967	11
T11	2497	12
T12	42565	77
T13	35094	57

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	224053	0	0
GntImpliesValid_A	260875270	224053	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	224053	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2136366	0	0
ReadyAndValidImplyGrant_A	260875270	224053	0	0
ReqAndReadyImplyGrant_A	260875270	224053	0	0
ReqImpliesValid_A	260875270	536388	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	224053	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2136366
T1	11190	61
T2	2123	19
T3	17514	340
T7	19118	614
T8	4402	62
T9	4657	50
T10	9967	75
T11	2497	16
T12	42565	530
T13	35094	444

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	536388
T1	11190	13
T2	2123	18
T3	17514	52
T7	19118	76
T8	4402	63
T9	4657	49
T10	9967	13
T11	2497	17
T12	42565	96
T13	35094	86

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	224053
T1	11190	10
T2	2123	18
T3	17514	43
T7	19118	73
T8	4402	62
T9	4657	49
T10	9967	7
T11	2497	16
T12	42565	83
T13	35094	63

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	225960	0	0
GntImpliesValid_A	260875270	225960	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	225960	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	4461975	0	0
ReadyAndValidImplyGrant_A	260875270	225960	0	0
ReqAndReadyImplyGrant_A	260875270	225960	0	0
ReqImpliesValid_A	260875270	1296928	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	225960	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	4461975
T1	11190	364
T2	2123	79
T3	17514	304
T7	19118	735
T8	4402	394
T9	4657	171
T10	9967	169
T11	2497	175
T12	42565	1918
T13	35094	770

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	1296928
T1	11190	22
T2	2123	26
T3	17514	30
T7	19118	118
T8	4402	134
T9	4657	61
T10	9967	25
T11	2497	42
T12	42565	244
T13	35094	92

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	225960
T1	11190	14
T2	2123	12
T3	17514	26
T7	19118	44
T8	4402	59
T9	4657	51
T10	9967	9
T11	2497	18
T12	42565	94
T13	35094	66

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	223342	0	0
GntImpliesValid_A	260875270	223342	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	223342	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	4041287	0	0
ReadyAndValidImplyGrant_A	260875270	223342	0	0
ReqAndReadyImplyGrant_A	260875270	223342	0	0
ReqImpliesValid_A	260875270	1116369	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	223342	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	4041287
T1	11190	144
T2	2123	47
T3	17514	2723
T7	19118	758
T8	4402	303
T9	4657	225
T10	9967	128
T11	2497	86
T12	42565	672
T13	35094	886

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	1116369
T1	11190	12
T2	2123	20
T3	17514	477
T7	19118	101
T8	4402	125
T9	4657	63
T10	9967	19
T11	2497	19
T12	42565	90
T13	35094	115

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	223342
T1	11190	12
T2	2123	10
T3	17514	39
T7	19118	46
T8	4402	78
T9	4657	63
T10	9967	12
T11	2497	14
T12	42565	62
T13	35094	64

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	215810	0	0
GntImpliesValid_A	260875270	215810	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	215810	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	3954197	0	0
ReadyAndValidImplyGrant_A	260875270	215810	0	0
ReqAndReadyImplyGrant_A	260875270	215810	0	0
ReqImpliesValid_A	260875270	985085	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	215810	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	3954197
T1	11190	198
T2	2123	74
T3	17514	419
T7	19118	275
T8	4402	223
T9	4657	176
T10	9967	123
T11	2497	71
T12	42565	1036
T13	35094	1064

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	985085
T1	11190	11
T2	2123	20
T3	17514	62
T7	19118	48
T8	4402	91
T9	4657	54
T10	9967	39
T11	2497	22
T12	42565	86
T13	35094	71

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	215810
T1	11190	9
T2	2123	17
T3	17514	32
T7	19118	38
T8	4402	70
T9	4657	46
T10	9967	8
T11	2497	15
T12	42565	64
T13	35094	49

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	219688	0	0
GntImpliesValid_A	260875270	219688	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	219688	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	3614155	0	0
ReadyAndValidImplyGrant_A	260875270	219688	0	0
ReqAndReadyImplyGrant_A	260875270	219688	0	0
ReqImpliesValid_A	260875270	1056363	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	219688	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	3614155
T1	11190	57
T2	2123	46
T3	17514	936
T7	19118	361
T8	4402	226
T9	4657	151
T10	9967	87
T11	2497	69
T12	42565	1205
T13	35094	4275

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	1056363
T1	11190	5
T2	2123	10
T3	17514	94
T7	19118	54
T8	4402	88
T9	4657	42
T10	9967	27
T11	2497	11
T12	42565	140
T13	35094	252

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	219688
T1	11190	5
T2	2123	10
T3	17514	41
T7	19118	53
T8	4402	70
T9	4657	42
T10	9967	12
T11	2497	11
T12	42565	85
T13	35094	75

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	212907	0	0
GntImpliesValid_A	260875270	212907	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	212907	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2148560	0	0
ReadyAndValidImplyGrant_A	260875270	212907	0	0
ReqAndReadyImplyGrant_A	260875270	212907	0	0
ReqImpliesValid_A	260875270	476061	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	212907	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2148560
T1	11190	84
T2	2123	18
T3	17514	366
T7	19118	442
T8	4402	64
T9	4657	60
T10	9967	84
T11	2497	19
T12	42565	656
T13	35094	482

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	476061
T1	11190	18
T2	2123	19
T3	17514	51
T7	19118	61
T8	4402	71
T9	4657	59
T10	9967	8
T11	2497	20
T12	42565	107
T13	35094	93

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	212907
T1	11190	11
T2	2123	18
T3	17514	42
T7	19118	54
T8	4402	67
T9	4657	59
T10	9967	8
T11	2497	19
T12	42565	84
T13	35094	70

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	222286	0	0
GntImpliesValid_A	260875270	222286	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	222286	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2129819	0	0
ReadyAndValidImplyGrant_A	260875270	222286	0	0
ReqAndReadyImplyGrant_A	260875270	222286	0	0
ReqImpliesValid_A	260875270	524321	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	222286	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2129819
T1	11190	74
T2	2123	8
T3	17514	242
T7	19118	419
T8	4402	80
T9	4657	48
T10	9967	114
T11	2497	8
T12	42565	541
T13	35094	425

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	524321
T1	11190	10
T2	2123	7
T3	17514	41
T7	19118	84
T8	4402	93
T9	4657	47
T10	9967	27
T11	2497	7
T12	42565	76
T13	35094	60

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	222286
T1	11190	10
T2	2123	7
T3	17514	35
T7	19118	56
T8	4402	86
T9	4657	47
T10	9967	12
T11	2497	7
T12	42565	69
T13	35094	52

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	230301	0	0
GntImpliesValid_A	260875270	230301	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	230301	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2139793	0	0
ReadyAndValidImplyGrant_A	260875270	230301	0	0
ReqAndReadyImplyGrant_A	260875270	230301	0	0
ReqImpliesValid_A	260875270	543106	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	230301	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2139793
T1	11190	67
T2	2123	9
T3	17514	261
T7	19118	372
T8	4402	74
T9	4657	56
T10	9967	90
T11	2497	20
T12	42565	689
T13	35094	420

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	543106
T1	11190	10
T2	2123	10
T3	17514	34
T7	19118	72
T8	4402	83
T9	4657	55
T10	9967	17
T11	2497	21
T12	42565	111
T13	35094	63

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	230301
T1	11190	10
T2	2123	9
T3	17514	32
T7	19118	53
T8	4402	78
T9	4657	55
T10	9967	12
T11	2497	20
T12	42565	87
T13	35094	58

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	218630	0	0
GntImpliesValid_A	260875270	218630	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	218630	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2134872	0	0
ReadyAndValidImplyGrant_A	260875270	218630	0	0
ReqAndReadyImplyGrant_A	260875270	218630	0	0
ReqImpliesValid_A	260875270	496391	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	218630	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2134872
T1	11190	59
T2	2123	11
T3	17514	281
T7	19118	438
T8	4402	78
T9	4657	56
T10	9967	85
T11	2497	14
T12	42565	625
T13	35094	411

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	496391
T1	11190	7
T2	2123	12
T3	17514	56
T7	19118	68
T8	4402	87
T9	4657	57
T10	9967	10
T11	2497	13
T12	42565	112
T13	35094	69

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	218630
T1	11190	7
T2	2123	11
T3	17514	38
T7	19118	53
T8	4402	82
T9	4657	56
T10	9967	10
T11	2497	13
T12	42565	86
T13	35094	68

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	220145	0	0
GntImpliesValid_A	260875270	220145	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	220145	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2125989	0	0
ReadyAndValidImplyGrant_A	260875270	220145	0	0
ReqAndReadyImplyGrant_A	260875270	220145	0	0
ReqImpliesValid_A	260875270	542834	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	220145	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2125989
T1	11190	94
T2	2123	15
T3	17514	284
T7	19118	437
T8	4402	66
T9	4657	48
T10	9967	62
T11	2497	18
T12	42565	387
T13	35094	540

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	542834
T1	11190	13
T2	2123	14
T3	17514	82
T7	19118	96
T8	4402	73
T9	4657	47
T10	9967	10
T11	2497	17
T12	42565	81
T13	35094	80

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	220145
T1	11190	13
T2	2123	14
T3	17514	43
T7	19118	62
T8	4402	69
T9	4657	47
T10	9967	8
T11	2497	17
T12	42565	64
T13	35094	73

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	229683	0	0
GntImpliesValid_A	260875270	229683	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	229683	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2165765	0	0
ReadyAndValidImplyGrant_A	260875270	229683	0	0
ReqAndReadyImplyGrant_A	260875270	229683	0	0
ReqImpliesValid_A	260875270	553948	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	229683	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2165765
T1	11190	88
T2	2123	20
T3	17514	327
T7	19118	437
T8	4402	75
T9	4657	58
T10	9967	102
T11	2497	14
T12	42565	657
T13	35094	466

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	553948
T1	11190	11
T2	2123	21
T3	17514	44
T7	19118	87
T8	4402	78
T9	4657	61
T10	9967	12
T11	2497	13
T12	42565	107
T13	35094	70

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	229683
T1	11190	10
T2	2123	20
T3	17514	39
T7	19118	62
T8	4402	76
T9	4657	59
T10	9967	12
T11	2497	13
T12	42565	81
T13	35094	60

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	236832	0	0
GntImpliesValid_A	260875270	236832	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	236832	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2161184	0	0
ReadyAndValidImplyGrant_A	260875270	236832	0	0
ReqAndReadyImplyGrant_A	260875270	236832	0	0
ReqImpliesValid_A	260875270	569351	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	236832	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2161184
T1	11190	80
T2	2123	18
T3	17514	236
T7	19118	314
T8	4402	75
T9	4657	49
T10	9967	61
T11	2497	13
T12	42565	482
T13	35094	474

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	569351
T1	11190	8
T2	2123	19
T3	17514	34
T7	19118	47
T8	4402	84
T9	4657	48
T10	9967	16
T11	2497	12
T12	42565	102
T13	35094	75

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	236832
T1	11190	8
T2	2123	18
T3	17514	29
T7	19118	45
T8	4402	79
T9	4657	48
T10	9967	11
T11	2497	12
T12	42565	74
T13	35094	62

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T8 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T7

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	221344	0	0
GntImpliesValid_A	260875270	221344	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	221344	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2159624	0	0
ReadyAndValidImplyGrant_A	260875270	221344	0	0
ReqAndReadyImplyGrant_A	260875270	221344	0	0
ReqImpliesValid_A	260875270	510696	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	221344	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2159624
T1	11190	66
T2	2123	15
T3	17514	320
T7	19118	349
T8	4402	89
T9	4657	59
T10	9967	32
T11	2497	16
T12	42565	515
T13	35094	548

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	510696
T1	11190	7
T2	2123	16
T3	17514	44
T7	19118	67
T8	4402	100
T9	4657	58
T10	9967	5
T11	2497	17
T12	42565	106
T13	35094	70

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	221344
T1	11190	7
T2	2123	15
T3	17514	44
T7	19118	53
T8	4402	94
T9	4657	58
T10	9967	5
T11	2497	16
T12	42565	75
T13	35094	70

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	232830	0	0
GntImpliesValid_A	260875270	232830	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	232830	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2228877	0	0
ReadyAndValidImplyGrant_A	260875270	232830	0	0
ReqAndReadyImplyGrant_A	260875270	232830	0	0
ReqImpliesValid_A	260875270	509124	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	232830	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2228877
T1	11190	59
T2	2123	11
T3	17514	296
T7	19118	347
T8	4402	64
T9	4657	47
T10	9967	130
T11	2497	12
T12	42565	898
T13	35094	757

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	509124
T1	11190	29
T2	2123	14
T3	17514	73
T7	19118	52
T8	4402	67
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	193
T13	35094	152

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	232830
T1	11190	10
T2	2123	12
T3	17514	44
T7	19118	44
T8	4402	65
T9	4657	46
T10	9967	13
T11	2497	11
T12	42565	130
T13	35094	100

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	221684	0	0
GntImpliesValid_A	260875270	221684	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	221684	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2187658	0	0
ReadyAndValidImplyGrant_A	260875270	221684	0	0
ReqAndReadyImplyGrant_A	260875270	221684	0	0
ReqImpliesValid_A	260875270	513541	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	221684	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2187658
T1	11190	59
T2	2123	14
T3	17514	274
T7	19118	353
T8	4402	67
T9	4657	52
T10	9967	50
T11	2497	11
T12	42565	475
T13	35094	517

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	513541
T1	11190	9
T2	2123	15
T3	17514	59
T7	19118	40
T8	4402	74
T9	4657	55
T10	9967	24
T11	2497	12
T12	42565	72
T13	35094	106

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	221684
T1	11190	9
T2	2123	14
T3	17514	34
T7	19118	40
T8	4402	70
T9	4657	53
T10	9967	11
T11	2497	11
T12	42565	65
T13	35094	66

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	229805	0	0
GntImpliesValid_A	260875270	229805	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	229805	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2135492	0	0
ReadyAndValidImplyGrant_A	260875270	229805	0	0
ReqAndReadyImplyGrant_A	260875270	229805	0	0
ReqImpliesValid_A	260875270	572009	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	229805	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2135492
T1	11190	81
T2	2123	16
T3	17514	200
T7	19118	354
T8	4402	64
T9	4657	54
T10	9967	92
T11	2497	11
T12	42565	618
T13	35094	522

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	572009
T1	11190	36
T2	2123	15
T3	17514	36
T7	19118	63
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	12
T12	42565	96
T13	35094	72

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	229805
T1	11190	13
T2	2123	15
T3	17514	29
T7	19118	46
T8	4402	63
T9	4657	53
T10	9967	12
T11	2497	11
T12	42565	83
T13	35094	67

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	218901	0	0
GntImpliesValid_A	260875270	218901	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	218901	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2143199	0	0
ReadyAndValidImplyGrant_A	260875270	218901	0	0
ReqAndReadyImplyGrant_A	260875270	218901	0	0
ReqImpliesValid_A	260875270	522587	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	218901	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2143199
T1	11190	77
T2	2123	13
T3	17514	253
T7	19118	416
T8	4402	74
T9	4657	53
T10	9967	116
T11	2497	10
T12	42565	680
T13	35094	469

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	522587
T1	11190	12
T2	2123	12
T3	17514	30
T7	19118	72
T8	4402	83
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	97
T13	35094	83

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	218901
T1	11190	10
T2	2123	12
T3	17514	29
T7	19118	49
T8	4402	78
T9	4657	52
T10	9967	13
T11	2497	9
T12	42565	85
T13	35094	62

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	226725	0	0
GntImpliesValid_A	260875270	226725	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	226725	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2120218	0	0
ReadyAndValidImplyGrant_A	260875270	226725	0	0
ReqAndReadyImplyGrant_A	260875270	226725	0	0
ReqImpliesValid_A	260875270	494941	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	226725	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2120218
T1	11190	124
T2	2123	9
T3	17514	234
T7	19118	425
T8	4402	63
T9	4657	54
T10	9967	47
T11	2497	15
T12	42565	535
T13	35094	414

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	494941
T1	11190	21
T2	2123	8
T3	17514	49
T7	19118	78
T8	4402	64
T9	4657	53
T10	9967	18
T11	2497	16
T12	42565	93
T13	35094	54

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	226725
T1	11190	18
T2	2123	8
T3	17514	35
T7	19118	51
T8	4402	63
T9	4657	53
T10	9967	7
T11	2497	15
T12	42565	73
T13	35094	46

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	231512	0	0
GntImpliesValid_A	260875270	231512	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	231512	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	2159547	0	0
ReadyAndValidImplyGrant_A	260875270	231512	0	0
ReqAndReadyImplyGrant_A	260875270	231512	0	0
ReqImpliesValid_A	260875270	563675	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	0	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	231512	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	2159547
T1	11190	43
T2	2123	10
T3	17514	369
T7	19118	425
T8	4402	64
T9	4657	51
T10	9967	84
T11	2497	14
T12	42565	641
T13	35094	499

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	563675
T1	11190	6
T2	2123	11
T3	17514	61
T7	19118	67
T8	4402	71
T9	4657	52
T10	9967	32
T11	2497	15
T12	42565	128
T13	35094	77

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	231512
T1	11190	6
T2	2123	10
T3	17514	44
T7	19118	53
T8	4402	67
T9	4657	51
T10	9967	14
T11	2497	14
T12	42565	78
T13	35094	76

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	908691	0	0
GntImpliesValid_A	260875270	908691	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	908691	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	8014387	0	0
ReadyAndValidImplyGrant_A	260875270	908691	0	0
ReqAndReadyImplyGrant_A	260875270	908691	0	0
ReqImpliesValid_A	260875270	2018580	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	20681	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	908691	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	8014387
T1	11190	345
T2	2123	1
T3	17514	1247
T7	19118	1795
T8	4402	1
T9	4657	1
T10	9967	334
T11	2497	1
T12	42565	2004
T13	35094	1663

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	2018580
T1	11190	86
T2	2123	53
T3	17514	351
T7	19118	432
T8	4402	286
T9	4657	197
T10	9967	69
T11	2497	62
T12	42565	402
T13	35094	332

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	260875270	20681	900
T4	15331	0	1
T7	19118	0	1
T8	4402	10	1
T9	4657	4	1
T10	9967	0	1
T11	2497	0	1
T12	42565	0	1
T13	35094	0	1
T15	0	5	0
T16	0	19	0
T17	0	6	0
T18	0	4	0
T19	0	9	0
T20	0	21	0
T23	0	20	0
T24	0	7	0
T25	274309	0	1
T26	11624	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	908691
T1	11190	55
T2	2123	53
T3	17514	183
T7	19118	254
T8	4402	286
T9	4657	197
T10	9967	51
T11	2497	62
T12	42565	301
T13	35094	255

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00



54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T7 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	260875270	260733876	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	260875270	891221	0	0
GntImpliesValid_A	260875270	891221	0	0
GrantKnown_A	260875270	260733876	0	0
IdxKnown_A	260875270	260733876	0	0
IndexIsCorrect_A	260875270	891221	0	0
LockArbDecision_A	260875270	0	0	0
NoReadyValidNoGrant_A	260875270	216716937	0	0
ReadyAndValidImplyGrant_A	260875270	891221	0	0
ReqAndReadyImplyGrant_A	260875270	891221	0	0
ReqImpliesValid_A	260875270	9558110	0	0
ReqStaysHighUntilGranted0_M	260875270	0	0	0
RoundRobin_A	260875270	29404	0	900
ValidKnown_A	260875270	260733876	0	0
gen_data_port_assertion.DataFlow_A	260875270	891221	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

GntImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

GrantKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IdxKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	260875270	216716937
T1	11190	9662
T2	2123	1
T3	17514	14111
T7	19118	15923
T8	4402	1
T9	4657	1
T10	9967	8655
T11	2497	1
T12	42565	35820
T13	35094	30045

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	260875270	9558110
T1	11190	508
T2	2123	59
T3	17514	1441
T7	19118	1656
T8	4402	290
T9	4657	201
T10	9967	430
T11	2497	56
T12	42565	2191
T13	35094	2058

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	260875270	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	260875270	29404	900
T4	15331	0	1
T7	19118	0	1
T8	4402	5	1
T9	4657	0	1
T10	9967	0	1
T11	2497	0	1
T12	42565	2	1
T13	35094	0	1
T14	0	2	0
T15	0	9	0
T16	0	23	0
T17	0	10	0
T18	0	4	0
T19	0	11	0
T21	0	1	0
T22	0	515	0
T25	274309	0	1
T26	11624	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	260875270	260733876
T1	11190	11140
T2	2123	2095
T3	17514	17463
T7	19118	19094
T8	4402	4389
T9	4657	4649
T10	9967	9931
T11	2497	2444
T12	42565	42508
T13	35094	35047

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	260875270	891221
T1	11190	59
T2	2123	59
T3	17514	176
T7	19118	210
T8	4402	290
T9	4657	201
T10	9967	52
T11	2497	56
T12	42565	282
T13	35094	255

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children